ecp5: Do not use specify in generate in cells_sim.v.

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index a5f905cf819a19f1928c5b3d233d99fc8b237f2c..76099f4939e98405141137f9d34678a38d14bab9 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -355,37 +355,24 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
                end
        endgenerate
 
-       generate
-               // TODO
-               if (CLKMUX == "INV")
-                       specify
-                               $setup(DI, negedge CLK, 0);
-                               $setup(CE, negedge CLK, 0);
-                               $setup(LSR, negedge CLK, 0);
-`ifndef YOSYS
-                               if (SRMODE == "ASYNC" && muxlsr) (negedge CLK => (Q : srval)) = 0;
-`else
-                               if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0;        // Technically, this should be an edge sensitive path
-                                                                                       // but for facilitating a bypass box, let's pretend it's
-                                                                                       // a simple path
-`endif
-                               if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0;
-                       endspecify
-               else
-                       specify
-                               $setup(DI, posedge CLK, 0);
-                               $setup(CE, posedge CLK, 0);
-                               $setup(LSR, posedge CLK, 0);
+       specify
+               $setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
+               $setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
+               $setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
+               $setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
+               $setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
+               $setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
 `ifndef YOSYS
-                               if (SRMODE == "ASYNC" && muxlsr) (posedge CLK => (Q : srval)) = 0;
+               if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
+               if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
 `else
-                               if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0;        // Technically, this should be an edge sensitive path
-                                                                                       // but for facilitating a bypass box, let's pretend it's
-                                                                                       // a simple path
+               if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0;        // Technically, this should be an edge sensitive path
+                                                                       // but for facilitating a bypass box, let's pretend it's
+                                                                       // a simple path
 `endif
-                               if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0;
-                       endspecify
-       endgenerate
+               if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
+               if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
+       endspecify
 endmodule
 
 // ---------------------------------------