+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu1]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu2]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl2.sequencer.slave[0]
-
-[system.cpu3]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl3.sequencer.slave[0]
-
-[system.cpu4]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl4.sequencer.slave[0]
-
-[system.cpu5]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl5.sequencer.slave[0]
-
-[system.cpu6]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl6.sequencer.slave[0]
-
-[system.cpu7]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl7.sequencer.slave[0]
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:268435455
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=8
-number_of_virtual_networks=3
-phys_mem=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory requestToDir responseFromDir responseFromMemory responseToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-eventq_index=0
-number_of_TBEs=256
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_mem_ctrl_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[19]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[27]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[20]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-enable_prefetch=false
-eventq_index=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-optionalQueue=system.ruby.l1_cntrl0.optionalQueue
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-to_l2_latency=1
-transitions_per_cycle=32
-unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.optionalQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-eventq_index=0
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-sys=system
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.cpu0.port
-
-[system.ruby.l1_cntrl0.unblockFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
-L1Dcache=system.ruby.l1_cntrl1.L1Dcache
-L1Icache=system.ruby.l1_cntrl1.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-enable_prefetch=false
-eventq_index=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl1.mandatoryQueue
-number_of_TBEs=256
-optionalQueue=system.ruby.l1_cntrl1.optionalQueue
-prefetcher=system.ruby.l1_cntrl1.prefetcher
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl1.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl1.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl1.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl1.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl1.sequencer
-system=system
-to_l2_latency=1
-transitions_per_cycle=32
-unblockFromL1Cache=system.ruby.l1_cntrl1.unblockFromL1Cache
-version=1
-
-[system.ruby.l1_cntrl1.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl1.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl1.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl1.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl1.optionalQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl1.prefetcher]
-type=Prefetcher
-cross_page=false
-eventq_index=0
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-sys=system
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl1.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.l1_cntrl1.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.l1_cntrl1.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.l1_cntrl1.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.l1_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl1.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl1.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-slave=system.cpu1.port
-
-[system.ruby.l1_cntrl1.unblockFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.l1_cntrl2]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
-L1Dcache=system.ruby.l1_cntrl2.L1Dcache
-L1Icache=system.ruby.l1_cntrl2.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-enable_prefetch=false
-eventq_index=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl2.mandatoryQueue
-number_of_TBEs=256
-optionalQueue=system.ruby.l1_cntrl2.optionalQueue
-prefetcher=system.ruby.l1_cntrl2.prefetcher
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl2.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl2.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl2.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl2.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl2.sequencer
-system=system
-to_l2_latency=1
-transitions_per_cycle=32
-unblockFromL1Cache=system.ruby.l1_cntrl2.unblockFromL1Cache
-version=2
-
-[system.ruby.l1_cntrl2.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl2.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl2.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl2.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl2.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl2.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl2.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl2.optionalQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl2.prefetcher]
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-
-[system.ruby.l1_cntrl2.requestFromL1Cache]
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-
-[system.ruby.l1_cntrl2.requestToL1Cache]
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-
-[system.ruby.l1_cntrl2.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl2.responseToL1Cache]
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-
-[system.ruby.l1_cntrl2.sequencer]
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-
-[system.ruby.l1_cntrl2.unblockFromL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl3]
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-
-[system.ruby.l1_cntrl3.L1Dcache]
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-
-[system.ruby.l1_cntrl3.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl3.L1Icache]
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-
-[system.ruby.l1_cntrl3.L1Icache.replacement_policy]
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-
-[system.ruby.l1_cntrl3.mandatoryQueue]
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-
-[system.ruby.l1_cntrl3.optionalQueue]
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-
-[system.ruby.l1_cntrl3.prefetcher]
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-
-[system.ruby.l1_cntrl3.requestFromL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl3.requestToL1Cache]
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-
-[system.ruby.l1_cntrl3.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl3.responseToL1Cache]
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-
-[system.ruby.l1_cntrl3.sequencer]
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-
-[system.ruby.l1_cntrl3.unblockFromL1Cache]
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-
-[system.ruby.l1_cntrl4]
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-
-[system.ruby.l1_cntrl4.L1Dcache]
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-
-[system.ruby.l1_cntrl4.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl4.L1Icache]
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-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl4.L1Icache.replacement_policy]
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-
-[system.ruby.l1_cntrl4.mandatoryQueue]
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-
-[system.ruby.l1_cntrl4.optionalQueue]
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-
-[system.ruby.l1_cntrl4.prefetcher]
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-
-[system.ruby.l1_cntrl4.requestFromL1Cache]
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-
-[system.ruby.l1_cntrl4.requestToL1Cache]
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-
-[system.ruby.l1_cntrl4.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl4.responseToL1Cache]
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-
-[system.ruby.l1_cntrl4.sequencer]
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-[system.ruby.l1_cntrl4.unblockFromL1Cache]
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-[system.ruby.l1_cntrl5]
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-
-[system.ruby.l1_cntrl5.L1Dcache]
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-[system.ruby.l1_cntrl5.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl5.L1Icache]
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-
-[system.ruby.l1_cntrl5.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl5.mandatoryQueue]
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-[system.ruby.l1_cntrl5.optionalQueue]
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-[system.ruby.l1_cntrl5.prefetcher]
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-
-[system.ruby.l1_cntrl5.requestFromL1Cache]
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-[system.ruby.l1_cntrl5.requestToL1Cache]
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-[system.ruby.l1_cntrl5.responseFromL1Cache]
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-[system.ruby.l1_cntrl5.responseToL1Cache]
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-[system.ruby.l1_cntrl5.sequencer]
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-
-[system.ruby.l1_cntrl5.unblockFromL1Cache]
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-
-[system.ruby.l1_cntrl6]
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-
-[system.ruby.l1_cntrl6.L1Dcache]
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-
-[system.ruby.l1_cntrl6.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl6.L1Icache]
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-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl6.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-[system.ruby.l1_cntrl6.mandatoryQueue]
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-[system.ruby.l1_cntrl6.optionalQueue]
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-
-[system.ruby.l1_cntrl6.prefetcher]
-type=Prefetcher
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-
-[system.ruby.l1_cntrl6.requestFromL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl6.requestToL1Cache]
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-[system.ruby.l1_cntrl6.responseFromL1Cache]
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-[system.ruby.l1_cntrl6.responseToL1Cache]
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-[system.ruby.l1_cntrl6.sequencer]
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-
-[system.ruby.l1_cntrl6.unblockFromL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl7]
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-
-[system.ruby.l1_cntrl7.L1Dcache]
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-
-[system.ruby.l1_cntrl7.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl7.L1Icache]
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-
-[system.ruby.l1_cntrl7.L1Icache.replacement_policy]
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-
-[system.ruby.l1_cntrl7.mandatoryQueue]
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-
-[system.ruby.l1_cntrl7.optionalQueue]
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-
-[system.ruby.l1_cntrl7.prefetcher]
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-[system.ruby.l1_cntrl7.requestFromL1Cache]
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-[system.ruby.l1_cntrl7.requestToL1Cache]
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-[system.ruby.l1_cntrl7.responseFromL1Cache]
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-[system.ruby.l1_cntrl7.responseToL1Cache]
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-[system.ruby.l1_cntrl7.sequencer]
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-[system.ruby.l1_cntrl7.unblockFromL1Cache]
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-[system.ruby.l2_cntrl0]
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-[system.ruby.l2_cntrl0.DirRequestFromL2Cache]
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-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
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-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
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-[system.ruby.l2_cntrl0.L2cache]
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-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
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-[system.ruby.l2_cntrl0.responseFromL2Cache]
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-[system.ruby.l2_cntrl0.responseToL2Cache]
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-[system.ruby.l2_cntrl0.unblockToL2Cache]
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-[system.ruby.memctrl_clk_domain]
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-[system.ruby.network]
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-netifs=
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-
-[system.ruby.network.ext_links0]
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-[system.ruby.network.ext_links1]
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-
-[system.ruby.network.ext_links2]
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-
-[system.ruby.network.ext_links3]
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-
-[system.ruby.network.ext_links4]
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-
-[system.ruby.network.ext_links5]
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-
-[system.ruby.network.ext_links6]
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-
-[system.ruby.network.ext_links7]
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-
-[system.ruby.network.ext_links8]
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-
-[system.ruby.network.ext_links9]
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-[system.ruby.network.int_link_buffers00]
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-[system.ruby.network.int_link_buffers01]
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-[system.ruby.network.int_link_buffers02]
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-[system.ruby.network.int_link_buffers03]
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-[system.ruby.network.int_link_buffers04]
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-[system.ruby.network.int_link_buffers05]
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-[system.ruby.network.int_link_buffers06]
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-[system.ruby.network.int_link_buffers07]
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-[system.ruby.network.int_link_buffers08]
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-[system.ruby.network.int_link_buffers09]
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-[system.ruby.network.int_link_buffers10]
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-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers36]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers37]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers38]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers39]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers40]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers41]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers42]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers43]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers44]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers45]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers46]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers47]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers48]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers49]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers50]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers51]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers52]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers53]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers54]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers55]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers56]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers57]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers58]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers59]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-system.cpu1: completed 10000 read, 5477 write accesses @993312
-system.cpu2: completed 10000 read, 5544 write accesses @996128
-system.cpu0: completed 10000 read, 5458 write accesses @996536
-system.cpu3: completed 10000 read, 5546 write accesses @998087
-system.cpu4: completed 10000 read, 5425 write accesses @1001440
-system.cpu7: completed 10000 read, 5725 write accesses @1002290
-system.cpu5: completed 10000 read, 5563 write accesses @1012962
-system.cpu6: completed 10000 read, 5626 write accesses @1026878
-system.cpu2: completed 20000 read, 11014 write accesses @1990757
-system.cpu7: completed 20000 read, 11213 write accesses @1998586
-system.cpu4: completed 20000 read, 10862 write accesses @2006179
-system.cpu1: completed 20000 read, 11109 write accesses @2009839
-system.cpu0: completed 20000 read, 11055 write accesses @2010590
-system.cpu3: completed 20000 read, 11147 write accesses @2011164
-system.cpu6: completed 20000 read, 11117 write accesses @2017946
-system.cpu5: completed 20000 read, 11249 write accesses @2044887
-system.cpu2: completed 30000 read, 16622 write accesses @2998924
-system.cpu7: completed 30000 read, 16766 write accesses @3010333
-system.cpu6: completed 30000 read, 16539 write accesses @3010945
-system.cpu0: completed 30000 read, 16681 write accesses @3021428
-system.cpu3: completed 30000 read, 16672 write accesses @3029534
-system.cpu1: completed 30000 read, 16667 write accesses @3029754
-system.cpu4: completed 30000 read, 16456 write accesses @3042339
-system.cpu5: completed 30000 read, 16900 write accesses @3057264
-system.cpu2: completed 40000 read, 22183 write accesses @4005170
-system.cpu0: completed 40000 read, 22112 write accesses @4017560
-system.cpu4: completed 40000 read, 21876 write accesses @4020474
-system.cpu7: completed 40000 read, 22317 write accesses @4024853
-system.cpu1: completed 40000 read, 22148 write accesses @4025120
-system.cpu3: completed 40000 read, 22291 write accesses @4025351
-system.cpu6: completed 40000 read, 22140 write accesses @4027478
-system.cpu5: completed 40000 read, 22522 write accesses @4053741
-system.cpu0: completed 50000 read, 27630 write accesses @5009643
-system.cpu3: completed 50000 read, 27709 write accesses @5018121
-system.cpu4: completed 50000 read, 27303 write accesses @5018876
-system.cpu2: completed 50000 read, 27685 write accesses @5024854
-system.cpu6: completed 50000 read, 27549 write accesses @5033153
-system.cpu7: completed 50000 read, 27925 write accesses @5035089
-system.cpu1: completed 50000 read, 27578 write accesses @5049644
-system.cpu5: completed 50000 read, 28161 write accesses @5067105
-system.cpu2: completed 60000 read, 33061 write accesses @6010104
-system.cpu3: completed 60000 read, 33252 write accesses @6011525
-system.cpu0: completed 60000 read, 33086 write accesses @6024049
-system.cpu7: completed 60000 read, 33494 write accesses @6044846
-system.cpu5: completed 60000 read, 33651 write accesses @6053289
-system.cpu4: completed 60000 read, 33094 write accesses @6056073
-system.cpu6: completed 60000 read, 33179 write accesses @6057027
-system.cpu1: completed 60000 read, 33046 write accesses @6072711
-system.cpu3: completed 70000 read, 38860 write accesses @7016441
-system.cpu2: completed 70000 read, 38631 write accesses @7032041
-system.cpu0: completed 70000 read, 38682 write accesses @7034544
-system.cpu5: completed 70000 read, 39256 write accesses @7040358
-system.cpu4: completed 70000 read, 38757 write accesses @7060040
-system.cpu6: completed 70000 read, 38734 write accesses @7064210
-system.cpu1: completed 70000 read, 38475 write accesses @7072466
-system.cpu7: completed 70000 read, 39003 write accesses @7074119
-system.cpu2: completed 80000 read, 44130 write accesses @8023565
-system.cpu3: completed 80000 read, 44287 write accesses @8037401
-system.cpu0: completed 80000 read, 44183 write accesses @8039617
-system.cpu7: completed 80000 read, 44442 write accesses @8065674
-system.cpu6: completed 80000 read, 44372 write accesses @8065734
-system.cpu4: completed 80000 read, 44321 write accesses @8067105
-system.cpu5: completed 80000 read, 45042 write accesses @8083622
-system.cpu1: completed 80000 read, 43978 write accesses @8094612
-system.cpu2: completed 90000 read, 49635 write accesses @9035560
-system.cpu0: completed 90000 read, 49823 write accesses @9061621
-system.cpu6: completed 90000 read, 50006 write accesses @9066745
-system.cpu3: completed 90000 read, 49847 write accesses @9070290
-system.cpu7: completed 90000 read, 49983 write accesses @9079579
-system.cpu4: completed 90000 read, 49962 write accesses @9089553
-system.cpu5: completed 90000 read, 50588 write accesses @9109500
-system.cpu1: completed 90000 read, 49692 write accesses @9124269
-system.cpu2: completed 100000 read, 55115 write accesses @10021833
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 14:01:33
-gem5 started Jan 21 2016 14:02:10
-gem5 executing on zizzer, pid 44714
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 10021833 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.010022 # Number of seconds simulated
-sim_ticks 10021833 # Number of ticks simulated
-final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 187111 # Simulator tick rate (ticks/s)
-host_mem_usage 467772 # Number of bytes of host memory used
-host_seconds 53.56 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39622272 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14218944 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 14218944 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 619098 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 619098 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 222171 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 222171 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 3953595315 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 3953595315 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1418796741 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1418796741 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 5372392056 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 5372392056 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 619101 # Number of read requests accepted
-system.mem_ctrls.writeReqs 222171 # Number of write requests accepted
-system.mem_ctrls.readBursts 619101 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 222171 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 39234688 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 387776 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 14090496 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39622464 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 14218944 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 6059 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 1977 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 76712 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 76619 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 76862 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 76984 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 76352 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 76556 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 76570 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 76387 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 27545 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 27285 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 27557 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 27826 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 27514 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 27565 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 27642 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 27230 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 10021798 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 619101 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 222171 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 32087 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 65566 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 105076 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 135661 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 128982 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 85695 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 43990 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 15985 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 16 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 68 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 1655 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 5385 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 9439 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 12632 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 14319 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 15430 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 15929 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 16152 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 15943 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 15642 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 15180 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 14917 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 14784 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 14795 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 14883 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 15369 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 4463 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 1876 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 780 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 324 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 113 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 50 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 19 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 10 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 3 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 333023 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 160.121361 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 125.956156 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 126.041045 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 135519 40.69% 40.69% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 125870 37.80% 78.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 44087 13.24% 91.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 17315 5.20% 96.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 6630 1.99% 98.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 2388 0.72% 99.64% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 800 0.24% 99.88% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 268 0.08% 99.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 146 0.04% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 333023 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 13749 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 44.585133 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 43.567355 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 9.556105 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-15 1 0.01% 0.01% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-19 13 0.09% 0.10% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-23 50 0.36% 0.47% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-27 236 1.72% 2.18% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::28-31 654 4.76% 6.94% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-35 1404 10.21% 17.15% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-39 1971 14.34% 31.49% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-43 2304 16.76% 48.24% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::44-47 2255 16.40% 64.64% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-51 1821 13.24% 77.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::52-55 1248 9.08% 86.97% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-59 870 6.33% 93.29% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::60-63 460 3.35% 96.64% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-67 257 1.87% 98.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::68-71 103 0.75% 99.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-75 53 0.39% 99.64% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::76-79 28 0.20% 99.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-83 12 0.09% 99.93% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::84-87 5 0.04% 99.97% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-91 1 0.01% 99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::92-95 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::100-103 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::116-119 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 13749 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 13749 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.013092 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.012104 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.190256 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13662 99.37% 99.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 31 0.23% 99.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 36 0.26% 99.85% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 11 0.08% 99.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 5 0.04% 99.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 2 0.01% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 13749 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 29074956 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 40722754 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3065210 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 47.43 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 66.43 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 3914.92 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1405.98 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 3953.61 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1418.80 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 41.57 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 30.59 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.98 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 5.50 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 26.51 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 286090 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 214085 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 46.67 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 97.23 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 11.91 # Average gap between requests
-system.mem_ctrls.pageHitRate 60.03 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 2517434640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1398574800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7649928000 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2282494464 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 654516720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 6829590204 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 21655800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 21354194628 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2130.971273 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 18 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 334620 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 9686250 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 654516720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 216555768 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 5822535600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 6693608088 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.969562 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 9686222 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 334620 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99423 # number of read accesses completed
-system.cpu0.num_writes 55170 # number of write accesses completed
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 98761 # number of read accesses completed
-system.cpu1.num_writes 54523 # number of write accesses completed
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 100000 # number of read accesses completed
-system.cpu2.num_writes 55115 # number of write accesses completed
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 99531 # number of read accesses completed
-system.cpu3.num_writes 55151 # number of write accesses completed
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 99248 # number of read accesses completed
-system.cpu4.num_writes 55036 # number of write accesses completed
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 99097 # number of read accesses completed
-system.cpu5.num_writes 55621 # number of write accesses completed
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 99456 # number of read accesses completed
-system.cpu6.num_writes 55200 # number of write accesses completed
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 99560 # number of read accesses completed
-system.cpu7.num_writes 55285 # number of write accesses completed
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 32 # delay histogram for all message
-system.ruby.delayHist::max_bucket 319 # delay histogram for all message
-system.ruby.delayHist::samples 4985028 # delay histogram for all message
-system.ruby.delayHist::mean 6.537266 # delay histogram for all message
-system.ruby.delayHist::stdev 17.581596 # delay histogram for all message
-system.ruby.delayHist | 4675734 93.80% 93.80% | 147874 2.97% 96.76% | 121251 2.43% 99.19% | 34910 0.70% 99.89% | 4283 0.09% 99.98% | 711 0.01% 99.99% | 211 0.00% 100.00% | 36 0.00% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 4985028 # delay histogram for all message
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 624868
-system.ruby.outstanding_req_hist_seqr::mean 15.998456
-system.ruby.outstanding_req_hist_seqr::gmean 15.997188
-system.ruby.outstanding_req_hist_seqr::stdev 0.126020
-system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 624743 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 624868
-system.ruby.latency_hist_seqr::bucket_size 1024
-system.ruby.latency_hist_seqr::max_bucket 10239
-system.ruby.latency_hist_seqr::samples 624741
-system.ruby.latency_hist_seqr::mean 2053.034201
-system.ruby.latency_hist_seqr::gmean 1585.285080
-system.ruby.latency_hist_seqr::stdev 1206.859039
-system.ruby.latency_hist_seqr | 164671 26.36% 26.36% | 154480 24.73% 51.09% | 150906 24.15% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 624741
-system.ruby.hit_latency_hist_seqr::bucket_size 1
-system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 10
-system.ruby.hit_latency_hist_seqr::mean 1
-system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 10
-system.ruby.miss_latency_hist_seqr::bucket_size 1024
-system.ruby.miss_latency_hist_seqr::max_bucket 10239
-system.ruby.miss_latency_hist_seqr::samples 624731
-system.ruby.miss_latency_hist_seqr::mean 2053.067048
-system.ruby.miss_latency_hist_seqr::gmean 1585.472070
-system.ruby.miss_latency_hist_seqr::stdev 1206.840773
-system.ruby.miss_latency_hist_seqr | 164661 26.36% 26.36% | 154480 24.73% 51.08% | 150906 24.16% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 624731
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 78237 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78237 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 3 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 77673 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77676 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 78377 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78378 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl2.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl2.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl2.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl2.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl2.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl2.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 78097 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78098 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl3.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl3.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl3.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl3.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl3.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl3.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses 78248 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78249 # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.L1Dcache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses 77823 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77823 # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.L1Dcache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses 78233 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78235 # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.L1Dcache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses 78071 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78073 # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl7.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl7.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl7.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl7.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl7.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl7.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.L2cache.demand_hits 35 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 624702 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 624737 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.fully_busy_cycles 3 # cycles for which number of transistions == max transitions
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers00.percent_links_utilized 4.083916
-system.ruby.network.routers00.msg_count.Control::0 78237
-system.ruby.network.routers00.msg_count.Request_Control::2 76723
-system.ruby.network.routers00.msg_count.Response_Data::1 78781
-system.ruby.network.routers00.msg_count.Response_Control::1 65104
-system.ruby.network.routers00.msg_count.Response_Control::2 77592
-system.ruby.network.routers00.msg_count.Writeback_Data::0 14761
-system.ruby.network.routers00.msg_count.Writeback_Data::1 52359
-system.ruby.network.routers00.msg_count.Writeback_Control::0 26368
-system.ruby.network.routers00.msg_bytes.Control::0 625896
-system.ruby.network.routers00.msg_bytes.Request_Control::2 613784
-system.ruby.network.routers00.msg_bytes.Response_Data::1 5672232
-system.ruby.network.routers00.msg_bytes.Response_Control::1 520832
-system.ruby.network.routers00.msg_bytes.Response_Control::2 620736
-system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1062792
-system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3769848
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0 210944
-system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers01.percent_links_utilized 4.041267
-system.ruby.network.routers01.msg_count.Control::0 77673
-system.ruby.network.routers01.msg_count.Request_Control::2 76172
-system.ruby.network.routers01.msg_count.Response_Data::1 78150
-system.ruby.network.routers01.msg_count.Response_Control::1 64711
-system.ruby.network.routers01.msg_count.Response_Control::2 77032
-system.ruby.network.routers01.msg_count.Writeback_Data::0 14582
-system.ruby.network.routers01.msg_count.Writeback_Data::1 51557
-system.ruby.network.routers01.msg_count.Writeback_Control::0 25847
-system.ruby.network.routers01.msg_bytes.Control::0 621384
-system.ruby.network.routers01.msg_bytes.Request_Control::2 609376
-system.ruby.network.routers01.msg_bytes.Response_Data::1 5626800
-system.ruby.network.routers01.msg_bytes.Response_Control::1 517688
-system.ruby.network.routers01.msg_bytes.Response_Control::2 616256
-system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1049904
-system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3712104
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0 206776
-system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers02.percent_links_utilized 4.088773
-system.ruby.network.routers02.msg_count.Control::0 78377
-system.ruby.network.routers02.msg_count.Request_Control::2 76766
-system.ruby.network.routers02.msg_count.Response_Data::1 78910
-system.ruby.network.routers02.msg_count.Response_Control::1 65384
-system.ruby.network.routers02.msg_count.Response_Control::2 77765
-system.ruby.network.routers02.msg_count.Writeback_Data::0 14879
-system.ruby.network.routers02.msg_count.Writeback_Data::1 52258
-system.ruby.network.routers02.msg_count.Writeback_Control::0 26370
-system.ruby.network.routers02.msg_bytes.Control::0 627016
-system.ruby.network.routers02.msg_bytes.Request_Control::2 614128
-system.ruby.network.routers02.msg_bytes.Response_Data::1 5681520
-system.ruby.network.routers02.msg_bytes.Response_Control::1 523072
-system.ruby.network.routers02.msg_bytes.Response_Control::2 622120
-system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1071288
-system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3762576
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0 210960
-system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers03.percent_links_utilized 4.065454
-system.ruby.network.routers03.msg_count.Control::0 78097
-system.ruby.network.routers03.msg_count.Request_Control::2 76565
-system.ruby.network.routers03.msg_count.Response_Data::1 78649
-system.ruby.network.routers03.msg_count.Response_Control::1 65111
-system.ruby.network.routers03.msg_count.Response_Control::2 77450
-system.ruby.network.routers03.msg_count.Writeback_Data::0 14609
-system.ruby.network.routers03.msg_count.Writeback_Data::1 51886
-system.ruby.network.routers03.msg_count.Writeback_Control::0 26213
-system.ruby.network.routers03.msg_bytes.Control::0 624776
-system.ruby.network.routers03.msg_bytes.Request_Control::2 612520
-system.ruby.network.routers03.msg_bytes.Response_Data::1 5662728
-system.ruby.network.routers03.msg_bytes.Response_Control::1 520888
-system.ruby.network.routers03.msg_bytes.Response_Control::2 619600
-system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1051848
-system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3735792
-system.ruby.network.routers03.msg_bytes.Writeback_Control::0 209704
-system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers04.percent_links_utilized 4.076620
-system.ruby.network.routers04.msg_count.Control::0 78248
-system.ruby.network.routers04.msg_count.Request_Control::2 76737
-system.ruby.network.routers04.msg_count.Response_Data::1 78779
-system.ruby.network.routers04.msg_count.Response_Control::1 65220
-system.ruby.network.routers04.msg_count.Response_Control::2 77622
-system.ruby.network.routers04.msg_count.Writeback_Data::0 14629
-system.ruby.network.routers04.msg_count.Writeback_Data::1 52148
-system.ruby.network.routers04.msg_count.Writeback_Control::0 26377
-system.ruby.network.routers04.msg_bytes.Control::0 625984
-system.ruby.network.routers04.msg_bytes.Request_Control::2 613896
-system.ruby.network.routers04.msg_bytes.Response_Data::1 5672088
-system.ruby.network.routers04.msg_bytes.Response_Control::1 521760
-system.ruby.network.routers04.msg_bytes.Response_Control::2 620976
-system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1053288
-system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3754656
-system.ruby.network.routers04.msg_bytes.Writeback_Control::0 211016
-system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers05.percent_links_utilized 4.060382
-system.ruby.network.routers05.msg_count.Control::0 77823
-system.ruby.network.routers05.msg_count.Request_Control::2 76343
-system.ruby.network.routers05.msg_count.Response_Data::1 78351
-system.ruby.network.routers05.msg_count.Response_Control::1 64553
-system.ruby.network.routers05.msg_count.Response_Control::2 77203
-system.ruby.network.routers05.msg_count.Writeback_Data::0 14778
-system.ruby.network.routers05.msg_count.Writeback_Data::1 51980
-system.ruby.network.routers05.msg_count.Writeback_Control::0 25796
-system.ruby.network.routers05.msg_bytes.Control::0 622584
-system.ruby.network.routers05.msg_bytes.Request_Control::2 610744
-system.ruby.network.routers05.msg_bytes.Response_Data::1 5641272
-system.ruby.network.routers05.msg_bytes.Response_Control::1 516424
-system.ruby.network.routers05.msg_bytes.Response_Control::2 617624
-system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1064016
-system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3742560
-system.ruby.network.routers05.msg_bytes.Writeback_Control::0 206368
-system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers06.percent_links_utilized 4.079877
-system.ruby.network.routers06.msg_count.Control::0 78233
-system.ruby.network.routers06.msg_count.Request_Control::2 76715
-system.ruby.network.routers06.msg_count.Response_Data::1 78791
-system.ruby.network.routers06.msg_count.Response_Control::1 65281
-system.ruby.network.routers06.msg_count.Response_Control::2 77590
-system.ruby.network.routers06.msg_count.Writeback_Data::0 14729
-system.ruby.network.routers06.msg_count.Writeback_Data::1 52178
-system.ruby.network.routers06.msg_count.Writeback_Control::0 26413
-system.ruby.network.routers06.msg_bytes.Control::0 625864
-system.ruby.network.routers06.msg_bytes.Request_Control::2 613720
-system.ruby.network.routers06.msg_bytes.Response_Data::1 5672952
-system.ruby.network.routers06.msg_bytes.Response_Control::1 522248
-system.ruby.network.routers06.msg_bytes.Response_Control::2 620720
-system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1060488
-system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3756816
-system.ruby.network.routers06.msg_bytes.Writeback_Control::0 211304
-system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers07.percent_links_utilized 4.070416
-system.ruby.network.routers07.msg_count.Control::0 78071
-system.ruby.network.routers07.msg_count.Request_Control::2 76560
-system.ruby.network.routers07.msg_count.Response_Data::1 78636
-system.ruby.network.routers07.msg_count.Response_Control::1 64981
-system.ruby.network.routers07.msg_count.Response_Control::2 77413
-system.ruby.network.routers07.msg_count.Writeback_Data::0 14746
-system.ruby.network.routers07.msg_count.Writeback_Data::1 52018
-system.ruby.network.routers07.msg_count.Writeback_Control::0 26096
-system.ruby.network.routers07.msg_bytes.Control::0 624568
-system.ruby.network.routers07.msg_bytes.Request_Control::2 612480
-system.ruby.network.routers07.msg_bytes.Response_Data::1 5661792
-system.ruby.network.routers07.msg_bytes.Response_Control::1 519848
-system.ruby.network.routers07.msg_bytes.Response_Control::2 619304
-system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1061712
-system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3745296
-system.ruby.network.routers07.msg_bytes.Writeback_Control::0 208768
-system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers08.percent_links_utilized 55.328626
-system.ruby.network.routers08.msg_count.Control::0 1243860
-system.ruby.network.routers08.msg_count.Request_Control::2 608794
-system.ruby.network.routers08.msg_count.Response_Data::1 1461646
-system.ruby.network.routers08.msg_count.Response_Control::1 1536291
-system.ruby.network.routers08.msg_count.Response_Control::2 619666
-system.ruby.network.routers08.msg_count.Writeback_Data::0 117713
-system.ruby.network.routers08.msg_count.Writeback_Data::1 416384
-system.ruby.network.routers08.msg_count.Writeback_Control::0 209480
-system.ruby.network.routers08.msg_bytes.Control::0 9950880
-system.ruby.network.routers08.msg_bytes.Request_Control::2 4870352
-system.ruby.network.routers08.msg_bytes.Response_Data::1 105238512
-system.ruby.network.routers08.msg_bytes.Response_Control::1 12290328
-system.ruby.network.routers08.msg_bytes.Response_Control::2 4957328
-system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8475336
-system.ruby.network.routers08.msg_bytes.Writeback_Data::1 29979648
-system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1675840
-system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers09.percent_links_utilized 22.966170
-system.ruby.network.routers09.msg_count.Control::0 619101
-system.ruby.network.routers09.msg_count.Response_Data::1 841268
-system.ruby.network.routers09.msg_count.Response_Control::1 1016015
-system.ruby.network.routers09.msg_bytes.Control::0 4952808
-system.ruby.network.routers09.msg_bytes.Response_Data::1 60571296
-system.ruby.network.routers09.msg_bytes.Response_Control::1 8128120
-system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers10.percent_links_utilized 11.092782
-system.ruby.network.routers10.msg_count.Control::0 1243860
-system.ruby.network.routers10.msg_count.Request_Control::2 612581
-system.ruby.network.routers10.msg_count.Response_Data::1 1467247
-system.ruby.network.routers10.msg_count.Response_Control::1 1536326
-system.ruby.network.routers10.msg_count.Response_Control::2 619667
-system.ruby.network.routers10.msg_count.Writeback_Data::0 117713
-system.ruby.network.routers10.msg_count.Writeback_Data::1 416384
-system.ruby.network.routers10.msg_count.Writeback_Control::0 209480
-system.ruby.network.routers10.msg_bytes.Control::0 9950880
-system.ruby.network.routers10.msg_bytes.Request_Control::2 4900648
-system.ruby.network.routers10.msg_bytes.Response_Data::1 105641784
-system.ruby.network.routers10.msg_bytes.Response_Control::1 12290608
-system.ruby.network.routers10.msg_bytes.Response_Control::2 4957336
-system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8475336
-system.ruby.network.routers10.msg_bytes.Writeback_Data::1 29979648
-system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1675840
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 3731580
-system.ruby.network.msg_count.Request_Control 1833956
-system.ruby.network.msg_count.Response_Data 4399208
-system.ruby.network.msg_count.Response_Control 6467977
-system.ruby.network.msg_count.Writeback_Data 1602291
-system.ruby.network.msg_count.Writeback_Control 628440
-system.ruby.network.msg_byte.Control 29852640
-system.ruby.network.msg_byte.Request_Control 14671648
-system.ruby.network.msg_byte.Response_Data 316742976
-system.ruby.network.msg_byte.Response_Control 51743816
-system.ruby.network.msg_byte.Writeback_Data 115364952
-system.ruby.network.msg_byte.Writeback_Control 5027520
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers00.throttle0.link_utilization 4.100802
-system.ruby.network.routers00.throttle0.msg_count.Request_Control::2 76723
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::1 78233
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::1 41131
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-system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 1675840
-system.ruby.network.routers10.throttle9.link_utilization 15.044962
-system.ruby.network.routers10.throttle9.msg_count.Control::0 619101
-system.ruby.network.routers10.throttle9.msg_count.Response_Data::1 222171
-system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 396922
-system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4952808
-system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15996312
-system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3175376
-system.ruby.delayVCHist.vnet_0::bucket_size 32 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::max_bucket 319 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 1571585 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 16.631308 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 28.252150 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 1262919 80.36% 80.36% | 147246 9.37% 89.73% | 121251 7.72% 97.44% | 34910 2.22% 99.67% | 4283 0.27% 99.94% | 711 0.05% 99.98% | 211 0.01% 100.00% | 36 0.00% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 1571585 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 2800862 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 2.301244 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 4.225794 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 2428288 86.70% 86.70% | 302747 10.81% 97.51% | 60957 2.18% 99.68% | 8242 0.29% 99.98% | 602 0.02% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 2800862 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 612581 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.008929 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.133339 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 609846 99.55% 99.55% | 0 0.00% 99.55% | 2735 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 612581 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 1024
-system.ruby.LD.latency_hist_seqr::max_bucket 10239
-system.ruby.LD.latency_hist_seqr::samples 401903
-system.ruby.LD.latency_hist_seqr::mean 2053.043401
-system.ruby.LD.latency_hist_seqr::gmean 1585.283402
-system.ruby.LD.latency_hist_seqr::stdev 1206.884955
-system.ruby.LD.latency_hist_seqr | 106001 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 401903
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 7
-system.ruby.LD.hit_latency_hist_seqr::mean 1
-system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 7
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 1024
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 10239
-system.ruby.LD.miss_latency_hist_seqr::samples 401896
-system.ruby.LD.miss_latency_hist_seqr::mean 2053.079142
-system.ruby.LD.miss_latency_hist_seqr::gmean 1585.486872
-system.ruby.LD.miss_latency_hist_seqr::stdev 1206.865080
-system.ruby.LD.miss_latency_hist_seqr | 105994 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 401896
-system.ruby.ST.latency_hist_seqr::bucket_size 1024
-system.ruby.ST.latency_hist_seqr::max_bucket 10239
-system.ruby.ST.latency_hist_seqr::samples 222838
-system.ruby.ST.latency_hist_seqr::mean 2053.017609
-system.ruby.ST.latency_hist_seqr::gmean 1585.288106
-system.ruby.ST.latency_hist_seqr::stdev 1206.815003
-system.ruby.ST.latency_hist_seqr | 58670 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 222838
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
-system.ruby.ST.hit_latency_hist_seqr::samples 3
-system.ruby.ST.hit_latency_hist_seqr::mean 1
-system.ruby.ST.hit_latency_hist_seqr::gmean 1
-system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 3
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 1024
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 10239
-system.ruby.ST.miss_latency_hist_seqr::samples 222835
-system.ruby.ST.miss_latency_hist_seqr::mean 2053.045235
-system.ruby.ST.miss_latency_hist_seqr::gmean 1585.445376
-system.ruby.ST.miss_latency_hist_seqr::stdev 1206.799639
-system.ruby.ST.miss_latency_hist_seqr | 58667 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 222835
-system.ruby.Directory_Controller.Fetch 619101 0.00% 0.00%
-system.ruby.Directory_Controller.Data 222171 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 619097 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 222171 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 396922 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 619101 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 222171 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 396922 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 619097 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 222171 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50255 12.50% 12.50% | 50036 12.45% 24.95% | 50411 12.54% 37.49% | 50415 12.54% 50.04% | 50500 12.56% 62.60% | 49698 12.36% 74.97% | 50454 12.55% 87.52% | 50164 12.48% 100.00%
-system.ruby.L1Cache_Controller.Load::total 401933
-system.ruby.L1Cache_Controller.Store | 27984 12.56% 12.56% | 27641 12.40% 24.96% | 27968 12.55% 37.51% | 27685 12.42% 49.93% | 27750 12.45% 62.39% | 28127 12.62% 75.01% | 27782 12.47% 87.47% | 27912 12.53% 100.00%
-system.ruby.L1Cache_Controller.Store::total 222849
-system.ruby.L1Cache_Controller.Inv | 76332 12.52% 12.52% | 75835 12.44% 24.97% | 76387 12.53% 37.50% | 76173 12.50% 50.00% | 76356 12.53% 62.52% | 75957 12.46% 74.98% | 76316 12.52% 87.51% | 76157 12.49% 100.00%
-system.ruby.L1Cache_Controller.Inv::total 609513
-system.ruby.L1Cache_Controller.L1_Replacement | 552371 12.53% 12.53% | 550621 12.49% 25.01% | 551224 12.50% 37.51% | 552517 12.53% 50.04% | 551365 12.50% 62.54% | 548546 12.44% 74.98% | 551692 12.51% 87.49% | 551725 12.51% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 4410061
-system.ruby.L1Cache_Controller.Fwd_GETX | 234 12.86% 12.86% | 193 10.60% 23.46% | 223 12.25% 35.71% | 228 12.53% 48.24% | 227 12.47% 60.71% | 241 13.24% 73.96% | 236 12.97% 86.92% | 238 13.08% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 1820
-system.ruby.L1Cache_Controller.Fwd_GETS | 157 12.58% 12.58% | 144 11.54% 24.12% | 156 12.50% 36.62% | 164 13.14% 49.76% | 154 12.34% 62.10% | 145 11.62% 73.72% | 163 13.06% 86.78% | 165 13.22% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 1248
-system.ruby.L1Cache_Controller.Data | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.Data::total 17
-system.ruby.L1Cache_Controller.Data_Exclusive | 49438 12.50% 12.50% | 49246 12.45% 24.95% | 49647 12.55% 37.50% | 49605 12.54% 50.04% | 49712 12.57% 62.60% | 48909 12.36% 74.97% | 49665 12.55% 87.52% | 49363 12.48% 100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total 395585
-system.ruby.L1Cache_Controller.DataS_fromL1 | 172 13.78% 13.78% | 145 11.62% 25.40% | 152 12.18% 37.58% | 161 12.90% 50.48% | 163 13.06% 63.54% | 168 13.46% 77.00% | 147 11.78% 88.78% | 140 11.22% 100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total 1248
-system.ruby.L1Cache_Controller.Data_all_Acks | 28621 12.56% 12.56% | 28275 12.41% 24.97% | 28573 12.54% 37.51% | 28325 12.43% 49.94% | 28365 12.45% 62.38% | 28742 12.61% 75.00% | 28416 12.47% 87.47% | 28564 12.53% 100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total 227881
-system.ruby.L1Cache_Controller.Ack | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 17
-system.ruby.L1Cache_Controller.Ack_all | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.Ack_all::total 17
-system.ruby.L1Cache_Controller.WB_Ack | 41127 12.57% 12.57% | 40427 12.36% 24.93% | 41249 12.61% 37.53% | 40820 12.48% 50.01% | 41004 12.53% 62.54% | 40574 12.40% 74.94% | 41141 12.57% 87.52% | 40840 12.48% 100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total 327182
-system.ruby.L1Cache_Controller.NP.Load | 50249 12.50% 12.50% | 50019 12.45% 24.95% | 50402 12.54% 37.49% | 50402 12.54% 50.04% | 50493 12.57% 62.60% | 49692 12.37% 74.97% | 50442 12.55% 87.52% | 50154 12.48% 100.00%
-system.ruby.L1Cache_Controller.NP.Load::total 401853
-system.ruby.L1Cache_Controller.NP.Store | 27983 12.56% 12.56% | 27632 12.40% 24.96% | 27961 12.55% 37.51% | 27680 12.42% 49.93% | 27747 12.45% 62.39% | 28122 12.62% 75.01% | 27776 12.47% 87.48% | 27901 12.52% 100.00%
-system.ruby.L1Cache_Controller.NP.Store::total 222802
-system.ruby.L1Cache_Controller.NP.Inv | 218 13.12% 13.12% | 171 10.30% 23.42% | 208 12.52% 35.94% | 206 12.40% 48.34% | 219 13.18% 61.53% | 202 12.16% 73.69% | 218 13.12% 86.82% | 219 13.18% 100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total 1661
-system.ruby.L1Cache_Controller.I.Load | 5 7.81% 7.81% | 13 20.31% 28.12% | 7 10.94% 39.06% | 10 15.62% 54.69% | 7 10.94% 65.62% | 5 7.81% 73.44% | 11 17.19% 90.62% | 6 9.38% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 64
-system.ruby.L1Cache_Controller.I.Store | 0 0.00% 0.00% | 9 22.50% 22.50% | 7 17.50% 40.00% | 5 12.50% 52.50% | 1 2.50% 55.00% | 4 10.00% 65.00% | 4 10.00% 75.00% | 10 25.00% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 40
-system.ruby.L1Cache_Controller.I.L1_Replacement | 36955 12.47% 12.47% | 37106 12.52% 24.99% | 36973 12.48% 37.47% | 37122 12.53% 50.00% | 37081 12.51% 62.51% | 37099 12.52% 75.03% | 36939 12.47% 87.49% | 37064 12.51% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 296339
-system.ruby.L1Cache_Controller.S.Inv | 576 12.71% 12.71% | 579 12.77% 25.48% | 543 11.98% 37.46% | 579 12.77% 50.23% | 549 12.11% 62.34% | 556 12.27% 74.61% | 580 12.80% 87.40% | 571 12.60% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 4533
-system.ruby.L1Cache_Controller.S.L1_Replacement | 144 13.20% 13.20% | 112 10.27% 23.46% | 137 12.56% 36.02% | 134 12.28% 48.30% | 149 13.66% 61.96% | 137 12.56% 74.52% | 133 12.19% 86.71% | 145 13.29% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 1091
-system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 2 40.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
-system.ruby.L1Cache_Controller.E.Load::total 5
-system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.E.Store::total 2
-system.ruby.L1Cache_Controller.E.Inv | 23003 12.40% 12.40% | 23352 12.58% 24.98% | 23212 12.51% 37.49% | 23319 12.57% 50.05% | 23269 12.54% 62.59% | 23047 12.42% 75.01% | 23189 12.50% 87.51% | 23179 12.49% 100.00%
-system.ruby.L1Cache_Controller.E.Inv::total 185570
-system.ruby.L1Cache_Controller.E.L1_Replacement | 26368 12.59% 12.59% | 25847 12.34% 24.93% | 26370 12.59% 37.51% | 26213 12.51% 50.03% | 26377 12.59% 62.62% | 25796 12.31% 74.93% | 26413 12.61% 87.54% | 26096 12.46% 100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total 209480
-system.ruby.L1Cache_Controller.E.Fwd_GETX | 64 13.31% 13.31% | 40 8.32% 21.62% | 55 11.43% 33.06% | 67 13.93% 46.99% | 60 12.47% 59.46% | 63 13.10% 72.56% | 54 11.23% 83.78% | 78 16.22% 100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total 481
-system.ruby.L1Cache_Controller.E.Fwd_GETS | 3 6.00% 6.00% | 7 14.00% 20.00% | 8 16.00% 36.00% | 6 12.00% 48.00% | 5 10.00% 58.00% | 3 6.00% 64.00% | 8 16.00% 80.00% | 10 20.00% 100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total 50
-system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 2
-system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 1
-system.ruby.L1Cache_Controller.M.Inv | 13117 12.56% 12.56% | 12975 12.43% 24.99% | 13007 12.46% 37.45% | 12982 12.43% 49.89% | 13030 12.48% 62.37% | 13257 12.70% 75.07% | 12964 12.42% 87.48% | 13067 12.52% 100.00%
-system.ruby.L1Cache_Controller.M.Inv::total 104399
-system.ruby.L1Cache_Controller.M.L1_Replacement | 14761 12.54% 12.54% | 14582 12.39% 24.93% | 14879 12.64% 37.57% | 14609 12.41% 49.98% | 14629 12.43% 62.41% | 14778 12.55% 74.96% | 14729 12.51% 87.47% | 14746 12.53% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 117713
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 46 17.10% 17.10% | 26 9.67% 26.77% | 22 8.18% 34.94% | 35 13.01% 47.96% | 31 11.52% 59.48% | 33 12.27% 71.75% | 39 14.50% 86.25% | 37 13.75% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 269
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 58 12.72% 12.72% | 58 12.72% 25.44% | 59 12.94% 38.38% | 58 12.72% 51.10% | 58 12.72% 63.82% | 58 12.72% 76.54% | 47 10.31% 86.84% | 60 13.16% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 456
-system.ruby.L1Cache_Controller.IS.Inv | 154 12.91% 12.91% | 156 13.08% 25.98% | 148 12.41% 38.39% | 155 12.99% 51.38% | 150 12.57% 63.96% | 153 12.82% 76.78% | 128 10.73% 87.51% | 149 12.49% 100.00%
-system.ruby.L1Cache_Controller.IS.Inv::total 1193
-system.ruby.L1Cache_Controller.IS.L1_Replacement | 304731 12.52% 12.52% | 304693 12.51% 25.03% | 304216 12.49% 37.53% | 306147 12.57% 50.10% | 305838 12.56% 62.66% | 299900 12.32% 74.98% | 305125 12.53% 87.51% | 304082 12.49% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2434732
-system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49438 12.50% 12.50% | 49246 12.45% 24.95% | 49647 12.55% 37.50% | 49605 12.54% 50.04% | 49712 12.57% 62.60% | 48909 12.36% 74.97% | 49665 12.55% 87.52% | 49363 12.48% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395585
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 172 13.78% 13.78% | 145 11.62% 25.40% | 152 12.18% 37.58% | 161 12.90% 50.48% | 163 13.06% 63.54% | 168 13.46% 77.00% | 147 11.78% 88.78% | 140 11.22% 100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1248
-system.ruby.L1Cache_Controller.IS.Data_all_Acks | 487 12.58% 12.58% | 481 12.43% 25.01% | 461 11.91% 36.93% | 488 12.61% 49.53% | 472 12.20% 61.73% | 464 11.99% 73.72% | 511 13.20% 86.93% | 506 13.07% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 3870
-system.ruby.L1Cache_Controller.IM.L1_Replacement | 169412 12.54% 12.54% | 168281 12.46% 25.00% | 168649 12.49% 37.49% | 168292 12.46% 49.95% | 167291 12.39% 62.33% | 170836 12.65% 74.98% | 168353 12.46% 87.44% | 169592 12.56% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1350706
-system.ruby.L1Cache_Controller.IM.Data | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 17
-system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27980 12.56% 12.56% | 27638 12.40% 24.96% | 27964 12.55% 37.51% | 27682 12.42% 49.93% | 27743 12.45% 62.39% | 28125 12.62% 75.01% | 27777 12.47% 87.47% | 27909 12.53% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 222818
-system.ruby.L1Cache_Controller.SM.Ack | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 17
-system.ruby.L1Cache_Controller.SM.Ack_all | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total 17
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 154 12.91% 12.91% | 156 13.08% 25.98% | 148 12.41% 38.39% | 155 12.99% 51.38% | 150 12.57% 63.96% | 153 12.82% 76.78% | 128 10.73% 87.51% | 149 12.49% 100.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 1193
-system.ruby.L1Cache_Controller.M_I.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
-system.ruby.L1Cache_Controller.M_I.Load::total 2
-system.ruby.L1Cache_Controller.M_I.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M_I.Store::total 1
-system.ruby.L1Cache_Controller.M_I.Inv | 39242 12.58% 12.58% | 38582 12.37% 24.94% | 39251 12.58% 37.53% | 38904 12.47% 50.00% | 39118 12.54% 62.53% | 38723 12.41% 74.95% | 39214 12.57% 87.52% | 38951 12.48% 100.00%
-system.ruby.L1Cache_Controller.M_I.Inv::total 311985
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 124 11.59% 11.59% | 127 11.87% 23.46% | 146 13.64% 37.10% | 126 11.78% 48.88% | 136 12.71% 61.59% | 145 13.55% 75.14% | 143 13.36% 88.50% | 123 11.50% 100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1070
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 96 12.94% 12.94% | 79 10.65% 23.58% | 89 11.99% 35.58% | 100 13.48% 49.06% | 91 12.26% 61.32% | 84 11.32% 72.64% | 108 14.56% 87.20% | 95 12.80% 100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 742
-system.ruby.L1Cache_Controller.M_I.WB_Ack | 1667 12.44% 12.44% | 1641 12.25% 24.69% | 1763 13.16% 37.85% | 1692 12.63% 50.49% | 1661 12.40% 62.88% | 1622 12.11% 74.99% | 1677 12.52% 87.51% | 1673 12.49% 100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total 13396
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 1 14.29% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 7
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 3
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 22 12.79% 12.79% | 20 11.63% 24.42% | 18 10.47% 34.88% | 28 16.28% 51.16% | 21 12.21% 63.37% | 19 11.05% 74.42% | 23 13.37% 87.79% | 21 12.21% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 172
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39460 12.58% 12.58% | 38786 12.36% 24.94% | 39486 12.58% 37.52% | 39128 12.47% 49.99% | 39343 12.54% 62.53% | 38952 12.41% 74.94% | 39464 12.58% 87.52% | 39167 12.48% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 313786
-system.ruby.L2Cache_Controller.L1_GETS 403525 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 225164 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 15509 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old 317752 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 6260 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 4973424 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 619096 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 619092 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 217296 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 200336 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack 3770 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 189325 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 1248 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 618418 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 398107 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 220994 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old 310098 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 17 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX 585 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 1182 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2573 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 4880 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8504 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 1248 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 1820 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 13396 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX_old 802 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 601946 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETS 31 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETX 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 1745 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 619092 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETS 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETX 53 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 4549 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 216101 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 200276 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 185569 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 2583 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 2573 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 1187 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 1182 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETS 2524 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETX 1390 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 243 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2228535 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 395579 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETS 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L1_PUTX_old 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14781 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 2524 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETS 1430 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETX 771 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L1_PUTX_old 309 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1244298 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 220993 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L2_Replacement 11 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 17 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 115 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX 83 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 915 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 869948 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 618401 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 609 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2783 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1008 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 194 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 180 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 14 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 179 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 1054 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu1]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu2]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl2.sequencer.slave[0]
-
-[system.cpu3]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl3.sequencer.slave[0]
-
-[system.cpu4]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl4.sequencer.slave[0]
-
-[system.cpu5]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl5.sequencer.slave[0]
-
-[system.cpu6]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl6.sequencer.slave[0]
-
-[system.cpu7]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl7.sequencer.slave[0]
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:268435455
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=8
-number_of_virtual_networks=3
-phys_mem=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory forwardFromDir requestToDir responseFromDir responseFromMemory responseToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-number_of_TBEs=256
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[20]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[19]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[19]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[20]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-l2_select_num_bits=0
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-[system.ruby.l1_cntrl0.L1Dcache]
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-[system.ruby.l1_cntrl0.L1Icache]
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-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl1.L1Dcache.replacement_policy]
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-[system.ruby.l1_cntrl1.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl2.L1Dcache]
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-[system.ruby.l1_cntrl2.L1Dcache.replacement_policy]
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-[system.ruby.l1_cntrl2.L1Icache]
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-[system.ruby.l1_cntrl2.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl2.sequencer]
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-[system.ruby.l1_cntrl3.sequencer]
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-[system.ruby.l1_cntrl3.triggerQueue]
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-[system.ruby.l1_cntrl4]
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-[system.ruby.l1_cntrl4.L1Dcache]
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-[system.ruby.l1_cntrl4.L1Dcache.replacement_policy]
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-[system.ruby.l1_cntrl4.L1Icache]
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-[system.ruby.l1_cntrl4.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl4.mandatoryQueue]
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-[system.ruby.l1_cntrl4.sequencer]
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-[system.ruby.l1_cntrl4.triggerQueue]
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-[system.ruby.l1_cntrl5]
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-[system.ruby.l1_cntrl5.L1Dcache]
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-
-[system.ruby.l1_cntrl5.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl5.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl5.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl5.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl5.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl5.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.ruby.l1_cntrl5.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.ruby.l1_cntrl5.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[11]
-
-[system.ruby.l1_cntrl5.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[11]
-
-[system.ruby.l1_cntrl5.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl5.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl5.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=5
-slave=system.cpu5.port
-
-[system.ruby.l1_cntrl5.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.l1_cntrl6]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue
-L1Dcache=system.ruby.l1_cntrl6.L1Dcache
-L1Icache=system.ruby.l1_cntrl6.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl6.mandatoryQueue
-number_of_TBEs=256
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl6.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl6.requestToL1Cache
-request_latency=2
-responseFromL1Cache=system.ruby.l1_cntrl6.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl6.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl6.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl6.triggerQueue
-use_timeout_latency=50
-version=6
-
-[system.ruby.l1_cntrl6.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl6.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl6.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl6.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl6.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl6.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[12]
-
-[system.ruby.l1_cntrl6.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[12]
-
-[system.ruby.l1_cntrl6.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[13]
-
-[system.ruby.l1_cntrl6.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.ruby.l1_cntrl6.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl6.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl6.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=6
-slave=system.cpu6.port
-
-[system.ruby.l1_cntrl6.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.l1_cntrl7]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue
-L1Dcache=system.ruby.l1_cntrl7.L1Dcache
-L1Icache=system.ruby.l1_cntrl7.L1Icache
-buffer_size=0
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl7.mandatoryQueue
-number_of_TBEs=256
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl7.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl7.requestToL1Cache
-request_latency=2
-responseFromL1Cache=system.ruby.l1_cntrl7.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl7.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl7.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl7.triggerQueue
-use_timeout_latency=50
-version=7
-
-[system.ruby.l1_cntrl7.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl7.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl7.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl7.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl7.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl7.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl7.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl7.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[14]
-
-[system.ruby.l1_cntrl7.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[14]
-
-[system.ruby.l1_cntrl7.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[15]
-
-[system.ruby.l1_cntrl7.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[15]
-
-[system.ruby.l1_cntrl7.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl7.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl7.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=7
-slave=system.cpu7.port
-
-[system.ruby.l1_cntrl7.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache triggerQueue
-GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache
-GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache
-L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-eventq_index=0
-number_of_TBEs=256
-recycle_latency=10
-request_latency=2
-responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
-responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
-response_latency=2
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l2_cntrl0.triggerQueue
-version=0
-
-[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[16]
-
-[system.ruby.l2_cntrl0.GlobalRequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[16]
-
-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[17]
-
-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[17]
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l2_cntrl0.responseFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[18]
-
-[system.ruby.l2_cntrl0.responseToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[18]
-
-[system.ruby.l2_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9
-netifs=
-number_of_virtual_networks=3
-routers=system.ruby.network.routers00 system.ruby.network.routers01 system.ruby.network.routers02 system.ruby.network.routers03 system.ruby.network.routers04 system.ruby.network.routers05 system.ruby.network.routers06 system.ruby.network.routers07 system.ruby.network.routers08 system.ruby.network.routers09 system.ruby.network.routers10
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l1_cntrl1.requestToL1Cache.slave system.ruby.l1_cntrl1.responseToL1Cache.slave system.ruby.l1_cntrl2.requestToL1Cache.slave system.ruby.l1_cntrl2.responseToL1Cache.slave system.ruby.l1_cntrl3.requestToL1Cache.slave system.ruby.l1_cntrl3.responseToL1Cache.slave system.ruby.l1_cntrl4.requestToL1Cache.slave system.ruby.l1_cntrl4.responseToL1Cache.slave system.ruby.l1_cntrl5.requestToL1Cache.slave system.ruby.l1_cntrl5.responseToL1Cache.slave system.ruby.l1_cntrl6.requestToL1Cache.slave system.ruby.l1_cntrl6.responseToL1Cache.slave system.ruby.l1_cntrl7.requestToL1Cache.slave system.ruby.l1_cntrl7.responseToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl1.requestFromL1Cache.master system.ruby.l1_cntrl1.responseFromL1Cache.master system.ruby.l1_cntrl2.requestFromL1Cache.master system.ruby.l1_cntrl2.responseFromL1Cache.master system.ruby.l1_cntrl3.requestFromL1Cache.master system.ruby.l1_cntrl3.responseFromL1Cache.master system.ruby.l1_cntrl4.requestFromL1Cache.master system.ruby.l1_cntrl4.responseFromL1Cache.master system.ruby.l1_cntrl5.requestFromL1Cache.master system.ruby.l1_cntrl5.responseFromL1Cache.master system.ruby.l1_cntrl6.requestFromL1Cache.master system.ruby.l1_cntrl6.responseFromL1Cache.master system.ruby.l1_cntrl7.requestFromL1Cache.master system.ruby.l1_cntrl7.responseFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers00
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl1
-int_node=system.ruby.network.routers01
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl2
-int_node=system.ruby.network.routers02
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.ext_links3]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl3
-int_node=system.ruby.network.routers03
-latency=1
-link_id=3
-weight=1
-
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-clk_domain=system.ruby.clk_domain
-eventq_index=0
-port_buffers=system.ruby.network.routers10.port_buffers00 system.ruby.network.routers10.port_buffers01 system.ruby.network.routers10.port_buffers02 system.ruby.network.routers10.port_buffers03 system.ruby.network.routers10.port_buffers04 system.ruby.network.routers10.port_buffers05 system.ruby.network.routers10.port_buffers06 system.ruby.network.routers10.port_buffers07 system.ruby.network.routers10.port_buffers08 system.ruby.network.routers10.port_buffers09 system.ruby.network.routers10.port_buffers10 system.ruby.network.routers10.port_buffers11 system.ruby.network.routers10.port_buffers12 system.ruby.network.routers10.port_buffers13 system.ruby.network.routers10.port_buffers14 system.ruby.network.routers10.port_buffers15 system.ruby.network.routers10.port_buffers16 system.ruby.network.routers10.port_buffers17 system.ruby.network.routers10.port_buffers18 system.ruby.network.routers10.port_buffers19 system.ruby.network.routers10.port_buffers20 system.ruby.network.routers10.port_buffers21 system.ruby.network.routers10.port_buffers22 system.ruby.network.routers10.port_buffers23 system.ruby.network.routers10.port_buffers24 system.ruby.network.routers10.port_buffers25 system.ruby.network.routers10.port_buffers26 system.ruby.network.routers10.port_buffers27 system.ruby.network.routers10.port_buffers28 system.ruby.network.routers10.port_buffers29 system.ruby.network.routers10.port_buffers30 system.ruby.network.routers10.port_buffers31 system.ruby.network.routers10.port_buffers32 system.ruby.network.routers10.port_buffers33 system.ruby.network.routers10.port_buffers34 system.ruby.network.routers10.port_buffers35 system.ruby.network.routers10.port_buffers36 system.ruby.network.routers10.port_buffers37 system.ruby.network.routers10.port_buffers38 system.ruby.network.routers10.port_buffers39 system.ruby.network.routers10.port_buffers40 system.ruby.network.routers10.port_buffers41 system.ruby.network.routers10.port_buffers42 system.ruby.network.routers10.port_buffers43 system.ruby.network.routers10.port_buffers44 system.ruby.network.routers10.port_buffers45 system.ruby.network.routers10.port_buffers46 system.ruby.network.routers10.port_buffers47 system.ruby.network.routers10.port_buffers48 system.ruby.network.routers10.port_buffers49 system.ruby.network.routers10.port_buffers50 system.ruby.network.routers10.port_buffers51 system.ruby.network.routers10.port_buffers52 system.ruby.network.routers10.port_buffers53 system.ruby.network.routers10.port_buffers54 system.ruby.network.routers10.port_buffers55 system.ruby.network.routers10.port_buffers56 system.ruby.network.routers10.port_buffers57 system.ruby.network.routers10.port_buffers58 system.ruby.network.routers10.port_buffers59
-router_id=10
-virt_nets=3
-
-[system.ruby.network.routers10.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers03]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers06]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers07]
-type=MessageBuffer
-buffer_size=0
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-randomization=false
-
-[system.ruby.network.routers10.port_buffers08]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers11]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers25]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers36]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers37]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers38]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers39]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers40]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers41]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers42]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers43]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers44]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers45]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers46]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers47]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers48]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers49]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers50]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers51]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers52]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers53]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers54]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers55]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers56]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers57]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers58]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers59]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-system.cpu0: completed 10000 read, 5508 write accesses @738866
-system.cpu3: completed 10000 read, 5629 write accesses @739336
-system.cpu1: completed 10000 read, 5566 write accesses @740014
-system.cpu2: completed 10000 read, 5452 write accesses @740145
-system.cpu7: completed 10000 read, 5492 write accesses @749235
-system.cpu6: completed 10000 read, 5560 write accesses @753933
-system.cpu4: completed 10000 read, 5642 write accesses @754605
-system.cpu5: completed 10000 read, 5631 write accesses @755018
-system.cpu0: completed 20000 read, 11092 write accesses @1475405
-system.cpu3: completed 20000 read, 11222 write accesses @1487700
-system.cpu7: completed 20000 read, 11015 write accesses @1488166
-system.cpu5: completed 20000 read, 11145 write accesses @1493697
-system.cpu1: completed 20000 read, 11221 write accesses @1496331
-system.cpu2: completed 20000 read, 11098 write accesses @1497419
-system.cpu4: completed 20000 read, 11227 write accesses @1505460
-system.cpu6: completed 20000 read, 11297 write accesses @1522234
-system.cpu2: completed 30000 read, 16610 write accesses @2227880
-system.cpu5: completed 30000 read, 16694 write accesses @2227884
-system.cpu7: completed 30000 read, 16430 write accesses @2229017
-system.cpu0: completed 30000 read, 16662 write accesses @2230891
-system.cpu3: completed 30000 read, 16917 write accesses @2234709
-system.cpu1: completed 30000 read, 16703 write accesses @2243507
-system.cpu4: completed 30000 read, 16821 write accesses @2245691
-system.cpu6: completed 30000 read, 16865 write accesses @2274986
-system.cpu2: completed 40000 read, 22186 write accesses @2969541
-system.cpu7: completed 40000 read, 21963 write accesses @2976706
-system.cpu5: completed 40000 read, 22081 write accesses @2977360
-system.cpu0: completed 40000 read, 22245 write accesses @2983600
-system.cpu4: completed 40000 read, 22353 write accesses @2983927
-system.cpu3: completed 40000 read, 22562 write accesses @2989463
-system.cpu1: completed 40000 read, 22203 write accesses @2993172
-system.cpu6: completed 40000 read, 22494 write accesses @3024614
-system.cpu5: completed 50000 read, 27602 write accesses @3707212
-system.cpu2: completed 50000 read, 27827 write accesses @3709656
-system.cpu0: completed 50000 read, 27788 write accesses @3720088
-system.cpu7: completed 50000 read, 27585 write accesses @3729952
-system.cpu3: completed 50000 read, 28225 write accesses @3741336
-system.cpu1: completed 50000 read, 27693 write accesses @3741643
-system.cpu4: completed 50000 read, 28024 write accesses @3746153
-system.cpu6: completed 50000 read, 27944 write accesses @3769575
-system.cpu2: completed 60000 read, 33396 write accesses @4457825
-system.cpu7: completed 60000 read, 33181 write accesses @4461083
-system.cpu0: completed 60000 read, 33524 write accesses @4471000
-system.cpu5: completed 60000 read, 33268 write accesses @4471818
-system.cpu3: completed 60000 read, 33936 write accesses @4490069
-system.cpu1: completed 60000 read, 33523 write accesses @4502736
-system.cpu4: completed 60000 read, 33611 write accesses @4508744
-system.cpu6: completed 60000 read, 33455 write accesses @4516682
-system.cpu2: completed 70000 read, 39052 write accesses @5195824
-system.cpu7: completed 70000 read, 38804 write accesses @5216520
-system.cpu0: completed 70000 read, 39132 write accesses @5221104
-system.cpu5: completed 70000 read, 38946 write accesses @5224763
-system.cpu3: completed 70000 read, 39374 write accesses @5234775
-system.cpu1: completed 70000 read, 39108 write accesses @5247582
-system.cpu4: completed 70000 read, 39073 write accesses @5249170
-system.cpu6: completed 70000 read, 38942 write accesses @5256670
-system.cpu2: completed 80000 read, 44560 write accesses @5927724
-system.cpu5: completed 80000 read, 44421 write accesses @5949764
-system.cpu3: completed 80000 read, 44834 write accesses @5973715
-system.cpu0: completed 80000 read, 44677 write accesses @5979429
-system.cpu7: completed 80000 read, 44408 write accesses @5979747
-system.cpu1: completed 80000 read, 44732 write accesses @5992417
-system.cpu4: completed 80000 read, 44550 write accesses @5998783
-system.cpu6: completed 80000 read, 44539 write accesses @6005684
-system.cpu2: completed 90000 read, 50191 write accesses @6684061
-system.cpu5: completed 90000 read, 50073 write accesses @6691954
-system.cpu3: completed 90000 read, 50398 write accesses @6725412
-system.cpu1: completed 90000 read, 50260 write accesses @6729032
-system.cpu7: completed 90000 read, 49856 write accesses @6729292
-system.cpu0: completed 90000 read, 50333 write accesses @6730369
-system.cpu4: completed 90000 read, 50097 write accesses @6738499
-system.cpu6: completed 90000 read, 50144 write accesses @6754135
-system.cpu5: completed 100000 read, 55687 write accesses @7436579
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 14:06:59
-gem5 started Jan 21 2016 14:07:35
-gem5 executing on zizzer, pid 50082
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 7436579 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.007437 # Number of seconds simulated
-sim_ticks 7436579 # Number of ticks simulated
-final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 82813 # Simulator tick rate (ticks/s)
-host_mem_usage 469820 # Number of bytes of host memory used
-host_seconds 89.80 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39411840 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14207680 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 14207680 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 615810 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 615810 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 221995 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 221995 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 5299727200 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 5299727200 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1910512885 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1910512885 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 7210240085 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 7210240085 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 615810 # Number of read requests accepted
-system.mem_ctrls.writeReqs 221995 # Number of write requests accepted
-system.mem_ctrls.readBursts 615810 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 221995 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 38929216 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 482624 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 14125184 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39411840 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 14207680 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 7541 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 1261 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 76231 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 76213 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 75957 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 75931 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 76493 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 75719 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 75833 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 75892 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 27537 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 27586 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 27586 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 27772 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 27583 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 27668 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 27492 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 27482 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 7436498 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 615810 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 221995 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 30449 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 21561 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 21067 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 21018 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 20984 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 20961 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 20980 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 20969 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 21010 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 21084 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 21146 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 21129 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 21110 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 21093 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 21035 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 20973 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 20827 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 20851 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 21366 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 23438 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 20522 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 20526 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 20692 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 21175 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 19524 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 18773 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 17374 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 14929 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 11206 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 6963 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 2993 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 541 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 1535 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 1606 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 2940 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 4414 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 5795 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 7172 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 8185 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 9155 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 10156 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 11124 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 12920 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 44902 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 22210 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 13816 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 13613 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 13742 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 13679 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 13617 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 1792 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 1038 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 879 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 821 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 762 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 704 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 635 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 574 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 527 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 442 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 381 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 322 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 271 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 227 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 184 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 155 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 123 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 96 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 66 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 50 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 35 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 28 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 17 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 9 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 217346 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 244.098166 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 202.416903 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 150.509893 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 27506 12.66% 12.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 89777 41.31% 53.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 57089 26.27% 80.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 26035 11.98% 92.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 10776 4.96% 97.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 4097 1.89% 99.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1420 0.65% 99.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 436 0.20% 99.90% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 210 0.10% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 217346 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 13325 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 45.646679 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 42.587501 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 16.167834 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7 23 0.17% 0.17% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15 31 0.23% 0.41% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23 111 0.83% 1.24% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31 4805 36.06% 37.30% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39 1443 10.83% 48.13% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47 177 1.33% 49.46% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55 620 4.65% 54.11% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63 5467 41.03% 95.14% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71 305 2.29% 97.43% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79 81 0.61% 98.03% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87 128 0.96% 98.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95 130 0.98% 99.97% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-103 3 0.02% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::168-175 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 13325 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 13325 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.563302 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.520349 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.274530 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 10488 78.71% 78.71% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 442 3.32% 82.03% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 1047 7.86% 89.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 903 6.78% 96.66% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 233 1.75% 98.41% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 111 0.83% 99.24% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 54 0.41% 99.65% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 14 0.11% 99.75% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 9 0.07% 99.82% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 4 0.03% 99.85% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 6 0.05% 99.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 4 0.03% 99.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 3 0.02% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 2 0.02% 99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 2 0.02% 99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32 2 0.02% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 13325 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 69903381 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 81460492 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3041345 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 114.92 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 133.92 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 5234.83 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1899.42 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 5299.73 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1910.51 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 55.74 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 40.90 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 14.84 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 20.93 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 27.84 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 397576 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 214045 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 65.36 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 96.97 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 8.88 # Average gap between requests
-system.mem_ctrls.pageHitRate 73.78 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1642961880 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 912756600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7590311040 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2287948032 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 485674800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 5067708804 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 16181400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 18003542556 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2421.165233 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 104 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 248300 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 7187510 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 485674800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 160692120 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 4320567600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 4966934520 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.968982 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 7187590 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 248300 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99533 # number of read accesses completed
-system.cpu0.num_writes 55594 # number of write accesses completed
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 99397 # number of read accesses completed
-system.cpu1.num_writes 55662 # number of write accesses completed
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 99976 # number of read accesses completed
-system.cpu2.num_writes 55789 # number of write accesses completed
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 99413 # number of read accesses completed
-system.cpu3.num_writes 55629 # number of write accesses completed
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 99342 # number of read accesses completed
-system.cpu4.num_writes 55223 # number of write accesses completed
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 100000 # number of read accesses completed
-system.cpu5.num_writes 55687 # number of write accesses completed
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 99314 # number of read accesses completed
-system.cpu6.num_writes 55046 # number of write accesses completed
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 99437 # number of read accesses completed
-system.cpu7.num_writes 55128 # number of write accesses completed
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 627422
-system.ruby.outstanding_req_hist_seqr::mean 15.998440
-system.ruby.outstanding_req_hist_seqr::gmean 15.997176
-system.ruby.outstanding_req_hist_seqr::stdev 0.125852
-system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 35 0.01% 0.02% | 627283 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 627422
-system.ruby.latency_hist_seqr::bucket_size 2048
-system.ruby.latency_hist_seqr::max_bucket 20479
-system.ruby.latency_hist_seqr::samples 627294
-system.ruby.latency_hist_seqr::mean 1517.095464
-system.ruby.latency_hist_seqr::gmean 959.020860
-system.ruby.latency_hist_seqr::stdev 1631.310093
-system.ruby.latency_hist_seqr | 473909 75.55% 75.55% | 104367 16.64% 92.19% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 627294
-system.ruby.hit_latency_hist_seqr::bucket_size 1
-system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 141
-system.ruby.hit_latency_hist_seqr::mean 1
-system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 141 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 141
-system.ruby.miss_latency_hist_seqr::bucket_size 2048
-system.ruby.miss_latency_hist_seqr::max_bucket 20479
-system.ruby.miss_latency_hist_seqr::samples 627153
-system.ruby.miss_latency_hist_seqr::mean 1517.436321
-system.ruby.miss_latency_hist_seqr::gmean 960.502379
-system.ruby.miss_latency_hist_seqr::stdev 1631.335046
-system.ruby.miss_latency_hist_seqr | 473768 75.54% 75.54% | 104367 16.64% 92.18% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 627153
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 22 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 78254 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78276 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 78372 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78381 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 78709 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78728 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 78281 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78298 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.L1Dcache.demand_hits 23 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses 78290 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78313 # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.L1Dcache.demand_hits 11 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses 78570 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78581 # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.L1Dcache.demand_hits 23 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses 78475 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78498 # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.L1Dcache.demand_hits 17 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses 78224 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78241 # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.L2cache.demand_hits 4647 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 622511 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 627158 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers00.percent_links_utilized 5.789295
-system.ruby.network.routers00.msg_count.Request_Control::0 78254
-system.ruby.network.routers00.msg_count.Response_Data::2 76885
-system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 587
-system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1652
-system.ruby.network.routers00.msg_count.Response_Control::2 604
-system.ruby.network.routers00.msg_count.Writeback_Data::2 77175
-system.ruby.network.routers00.msg_count.Writeback_Control::0 156408
-system.ruby.network.routers00.msg_count.Forwarded_Control::0 873
-system.ruby.network.routers00.msg_count.Invalidate_Control::0 239
-system.ruby.network.routers00.msg_count.Unblock_Control::2 79033
-system.ruby.network.routers00.msg_bytes.Request_Control::0 626032
-system.ruby.network.routers00.msg_bytes.Response_Data::2 5535720
-system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 42264
-system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 118944
-system.ruby.network.routers00.msg_bytes.Response_Control::2 4832
-system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5556600
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1251264
-system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6984
-system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1912
-system.ruby.network.routers00.msg_bytes.Unblock_Control::2 632264
-system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers01.percent_links_utilized 5.798120
-system.ruby.network.routers01.msg_count.Request_Control::0 78372
-system.ruby.network.routers01.msg_count.Response_Data::2 76915
-system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 595
-system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1758
-system.ruby.network.routers01.msg_count.Response_Control::2 636
-system.ruby.network.routers01.msg_count.Writeback_Data::2 77261
-system.ruby.network.routers01.msg_count.Writeback_Control::0 156637
-system.ruby.network.routers01.msg_count.Forwarded_Control::0 897
-system.ruby.network.routers01.msg_count.Invalidate_Control::0 228
-system.ruby.network.routers01.msg_count.Unblock_Control::2 79196
-system.ruby.network.routers01.msg_bytes.Request_Control::0 626976
-system.ruby.network.routers01.msg_bytes.Response_Data::2 5537880
-system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 42840
-system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 126576
-system.ruby.network.routers01.msg_bytes.Response_Control::2 5088
-system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5562792
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1253096
-system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 7176
-system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1824
-system.ruby.network.routers01.msg_bytes.Unblock_Control::2 633568
-system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers02.percent_links_utilized 5.822099
-system.ruby.network.routers02.msg_count.Request_Control::0 78709
-system.ruby.network.routers02.msg_count.Response_Data::2 77304
-system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 573
-system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1661
-system.ruby.network.routers02.msg_count.Response_Control::2 620
-system.ruby.network.routers02.msg_count.Writeback_Data::2 77646
-system.ruby.network.routers02.msg_count.Writeback_Control::0 157329
-system.ruby.network.routers02.msg_count.Forwarded_Control::0 832
-system.ruby.network.routers02.msg_count.Invalidate_Control::0 240
-system.ruby.network.routers02.msg_count.Unblock_Control::2 79474
-system.ruby.network.routers02.msg_bytes.Request_Control::0 629672
-system.ruby.network.routers02.msg_bytes.Response_Data::2 5565888
-system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 41256
-system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 119592
-system.ruby.network.routers02.msg_bytes.Response_Control::2 4960
-system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5590512
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1258632
-system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6656
-system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1920
-system.ruby.network.routers02.msg_bytes.Unblock_Control::2 635792
-system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers03.percent_links_utilized 5.790606
-system.ruby.network.routers03.msg_count.Request_Control::0 78281
-system.ruby.network.routers03.msg_count.Response_Data::2 76851
-system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 577
-system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 1709
-system.ruby.network.routers03.msg_count.Response_Control::2 618
-system.ruby.network.routers03.msg_count.Writeback_Data::2 77193
-system.ruby.network.routers03.msg_count.Writeback_Control::0 156460
-system.ruby.network.routers03.msg_count.Forwarded_Control::0 860
-system.ruby.network.routers03.msg_count.Invalidate_Control::0 224
-system.ruby.network.routers03.msg_count.Unblock_Control::2 79079
-system.ruby.network.routers03.msg_bytes.Request_Control::0 626248
-system.ruby.network.routers03.msg_bytes.Response_Data::2 5533272
-system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 41544
-system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 123048
-system.ruby.network.routers03.msg_bytes.Response_Control::2 4944
-system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5557896
-system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1251680
-system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6880
-system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1792
-system.ruby.network.routers03.msg_bytes.Unblock_Control::2 632632
-system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers04.percent_links_utilized 5.791907
-system.ruby.network.routers04.msg_count.Request_Control::0 78290
-system.ruby.network.routers04.msg_count.Response_Data::2 76878
-system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 592
-system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1671
-system.ruby.network.routers04.msg_count.Response_Control::2 602
-system.ruby.network.routers04.msg_count.Writeback_Data::2 77230
-system.ruby.network.routers04.msg_count.Writeback_Control::0 156495
-system.ruby.network.routers04.msg_count.Forwarded_Control::0 853
-system.ruby.network.routers04.msg_count.Invalidate_Control::0 215
-system.ruby.network.routers04.msg_count.Unblock_Control::2 79085
-system.ruby.network.routers04.msg_bytes.Request_Control::0 626320
-system.ruby.network.routers04.msg_bytes.Response_Data::2 5535216
-system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 42624
-system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 120312
-system.ruby.network.routers04.msg_bytes.Response_Control::2 4816
-system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5560560
-system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1251960
-system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6824
-system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1720
-system.ruby.network.routers04.msg_bytes.Unblock_Control::2 632680
-system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers05.percent_links_utilized 5.809960
-system.ruby.network.routers05.msg_count.Request_Control::0 78570
-system.ruby.network.routers05.msg_count.Response_Data::2 77119
-system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 582
-system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 1651
-system.ruby.network.routers05.msg_count.Response_Control::2 643
-system.ruby.network.routers05.msg_count.Writeback_Data::2 77495
-system.ruby.network.routers05.msg_count.Writeback_Control::0 157040
-system.ruby.network.routers05.msg_count.Forwarded_Control::0 785
-system.ruby.network.routers05.msg_count.Invalidate_Control::0 264
-system.ruby.network.routers05.msg_count.Unblock_Control::2 79327
-system.ruby.network.routers05.msg_bytes.Request_Control::0 628560
-system.ruby.network.routers05.msg_bytes.Response_Data::2 5552568
-system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 41904
-system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 118872
-system.ruby.network.routers05.msg_bytes.Response_Control::2 5144
-system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5579640
-system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1256320
-system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6280
-system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 2112
-system.ruby.network.routers05.msg_bytes.Unblock_Control::2 634616
-system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers06.percent_links_utilized 5.804383
-system.ruby.network.routers06.msg_count.Request_Control::0 78475
-system.ruby.network.routers06.msg_count.Response_Data::2 77081
-system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 559
-system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 1654
-system.ruby.network.routers06.msg_count.Response_Control::2 595
-system.ruby.network.routers06.msg_count.Writeback_Data::2 77412
-system.ruby.network.routers06.msg_count.Writeback_Control::0 156860
-system.ruby.network.routers06.msg_count.Forwarded_Control::0 823
-system.ruby.network.routers06.msg_count.Invalidate_Control::0 222
-system.ruby.network.routers06.msg_count.Unblock_Control::2 79261
-system.ruby.network.routers06.msg_bytes.Request_Control::0 627800
-system.ruby.network.routers06.msg_bytes.Response_Data::2 5549832
-system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 40248
-system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 119088
-system.ruby.network.routers06.msg_bytes.Response_Control::2 4760
-system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5573664
-system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1254880
-system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6584
-system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1776
-system.ruby.network.routers06.msg_bytes.Unblock_Control::2 634088
-system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers07.percent_links_utilized 5.784636
-system.ruby.network.routers07.msg_count.Request_Control::0 78224
-system.ruby.network.routers07.msg_count.Response_Data::2 76772
-system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 582
-system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 1646
-system.ruby.network.routers07.msg_count.Response_Control::2 591
-system.ruby.network.routers07.msg_count.Writeback_Data::2 77168
-system.ruby.network.routers07.msg_count.Writeback_Control::0 156378
-system.ruby.network.routers07.msg_count.Forwarded_Control::0 778
-system.ruby.network.routers07.msg_count.Invalidate_Control::0 226
-system.ruby.network.routers07.msg_count.Unblock_Control::2 79007
-system.ruby.network.routers07.msg_bytes.Request_Control::0 625792
-system.ruby.network.routers07.msg_bytes.Response_Data::2 5527584
-system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 41904
-system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 118512
-system.ruby.network.routers07.msg_bytes.Response_Control::2 4728
-system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5556096
-system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1251024
-system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6224
-system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 1808
-system.ruby.network.routers07.msg_bytes.Unblock_Control::2 632056
-system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers08.percent_links_utilized 76.954202
-system.ruby.network.routers08.msg_count.Request_Control::0 627158
-system.ruby.network.routers08.msg_count.Request_Control::1 615810
-system.ruby.network.routers08.msg_count.Response_Data::2 1231612
-system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 4647
-system.ruby.network.routers08.msg_count.Response_Control::2 1193
-system.ruby.network.routers08.msg_count.Writeback_Data::2 840575
-system.ruby.network.routers08.msg_count.Writeback_Control::0 1253590
-system.ruby.network.routers08.msg_count.Writeback_Control::1 443999
-system.ruby.network.routers08.msg_count.Forwarded_Control::0 6701
-system.ruby.network.routers08.msg_count.Invalidate_Control::0 1852
-system.ruby.network.routers08.msg_count.Unblock_Control::2 1249240
-system.ruby.network.routers08.msg_bytes.Request_Control::0 5017264
-system.ruby.network.routers08.msg_bytes.Request_Control::1 4926480
-system.ruby.network.routers08.msg_bytes.Response_Data::2 88676064
-system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 334584
-system.ruby.network.routers08.msg_bytes.Response_Control::2 9544
-system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60521400
-system.ruby.network.routers08.msg_bytes.Writeback_Control::0 10028720
-system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3551992
-system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 53608
-system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14816
-system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9993920
-system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers09.percent_links_utilized 30.981463
-system.ruby.network.routers09.msg_count.Request_Control::1 615810
-system.ruby.network.routers09.msg_count.Response_Data::2 615809
-system.ruby.network.routers09.msg_count.Writeback_Data::2 221995
-system.ruby.network.routers09.msg_count.Writeback_Control::1 444008
-system.ruby.network.routers09.msg_count.Unblock_Control::2 615790
-system.ruby.network.routers09.msg_bytes.Request_Control::1 4926480
-system.ruby.network.routers09.msg_bytes.Response_Data::2 44338248
-system.ruby.network.routers09.msg_bytes.Writeback_Data::2 15983640
-system.ruby.network.routers09.msg_bytes.Writeback_Control::1 3552064
-system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4926320
-system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers10.percent_links_utilized 15.432642
-system.ruby.network.routers10.msg_count.Request_Control::0 627158
-system.ruby.network.routers10.msg_count.Request_Control::1 615810
-system.ruby.network.routers10.msg_count.Response_Data::2 1231611
-system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 4647
-system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 6701
-system.ruby.network.routers10.msg_count.Response_Control::2 3051
-system.ruby.network.routers10.msg_count.Writeback_Data::2 840575
-system.ruby.network.routers10.msg_count.Writeback_Control::0 1253590
-system.ruby.network.routers10.msg_count.Writeback_Control::1 443999
-system.ruby.network.routers10.msg_count.Forwarded_Control::0 6701
-system.ruby.network.routers10.msg_count.Invalidate_Control::0 1858
-system.ruby.network.routers10.msg_count.Unblock_Control::2 1249240
-system.ruby.network.routers10.msg_bytes.Request_Control::0 5017264
-system.ruby.network.routers10.msg_bytes.Request_Control::1 4926480
-system.ruby.network.routers10.msg_bytes.Response_Data::2 88675992
-system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 334584
-system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 482472
-system.ruby.network.routers10.msg_bytes.Response_Control::2 24408
-system.ruby.network.routers10.msg_bytes.Writeback_Data::2 60521400
-system.ruby.network.routers10.msg_bytes.Writeback_Control::0 10028720
-system.ruby.network.routers10.msg_bytes.Writeback_Control::1 3551992
-system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 53608
-system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14864
-system.ruby.network.routers10.msg_bytes.Unblock_Control::2 9993920
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control 3728921
-system.ruby.network.msg_count.Response_Data 3694837
-system.ruby.network.msg_count.ResponseL2hit_Data 13941
-system.ruby.network.msg_count.ResponseLocal_Data 20103
-system.ruby.network.msg_count.Response_Control 9153
-system.ruby.network.msg_count.Writeback_Data 2521725
-system.ruby.network.msg_count.Writeback_Control 5092793
-system.ruby.network.msg_count.Forwarded_Control 20103
-system.ruby.network.msg_count.Invalidate_Control 5568
-system.ruby.network.msg_count.Unblock_Control 3747732
-system.ruby.network.msg_byte.Request_Control 29831368
-system.ruby.network.msg_byte.Response_Data 266028264
-system.ruby.network.msg_byte.ResponseL2hit_Data 1003752
-system.ruby.network.msg_byte.ResponseLocal_Data 1447416
-system.ruby.network.msg_byte.Response_Control 73224
-system.ruby.network.msg_byte.Writeback_Data 181564200
-system.ruby.network.msg_byte.Writeback_Control 40742344
-system.ruby.network.msg_byte.Forwarded_Control 160824
-system.ruby.network.msg_byte.Invalidate_Control 44544
-system.ruby.network.msg_byte.Unblock_Control 29981856
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers00.throttle0.link_utilization 5.270831
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 76885
-system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 587
-system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::2 779
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::2 365
-system.ruby.network.routers00.throttle0.msg_count.Writeback_Control::0 78203
-system.ruby.network.routers00.throttle0.msg_count.Forwarded_Control::0 873
-system.ruby.network.routers00.throttle0.msg_count.Invalidate_Control::0 239
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::2 5535720
-system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::2 42264
-system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::2 56088
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::2 2920
-system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Control::0 625624
-system.ruby.network.routers00.throttle0.msg_bytes.Forwarded_Control::0 6984
-system.ruby.network.routers00.throttle0.msg_bytes.Invalidate_Control::0 1912
-system.ruby.network.routers00.throttle1.link_utilization 6.307759
-system.ruby.network.routers00.throttle1.msg_count.Request_Control::0 78254
-system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::2 873
-system.ruby.network.routers00.throttle1.msg_count.Response_Control::2 239
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::2 77175
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0 78205
-system.ruby.network.routers00.throttle1.msg_count.Unblock_Control::2 79033
-system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::0 626032
-system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::2 62856
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2 1912
-system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::2 5556600
-system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0 625640
-system.ruby.network.routers00.throttle1.msg_bytes.Unblock_Control::2 632264
-system.ruby.network.routers01.throttle0.link_utilization 5.279242
-system.ruby.network.routers01.throttle0.msg_count.Response_Data::2 76915
-system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::2 595
-system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::2 861
-system.ruby.network.routers01.throttle0.msg_count.Response_Control::2 408
-system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::0 78318
-system.ruby.network.routers01.throttle0.msg_count.Forwarded_Control::0 897
-system.ruby.network.routers01.throttle0.msg_count.Invalidate_Control::0 228
-system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::2 5537880
-system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::2 42840
-system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::2 61992
-system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::2 3264
-system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::0 626544
-system.ruby.network.routers01.throttle0.msg_bytes.Forwarded_Control::0 7176
-system.ruby.network.routers01.throttle0.msg_bytes.Invalidate_Control::0 1824
-system.ruby.network.routers01.throttle1.link_utilization 6.316997
-system.ruby.network.routers01.throttle1.msg_count.Request_Control::0 78372
-system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::2 897
-system.ruby.network.routers01.throttle1.msg_count.Response_Control::2 228
-system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::2 77261
-system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::0 78319
-system.ruby.network.routers01.throttle1.msg_count.Unblock_Control::2 79196
-system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::0 626976
-system.ruby.network.routers01.throttle1.msg_bytes.ResponseLocal_Data::2 64584
-system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::2 1824
-system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::2 5562792
-system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Control::0 626552
-system.ruby.network.routers01.throttle1.msg_bytes.Unblock_Control::2 633568
-system.ruby.network.routers02.throttle0.link_utilization 5.301288
-system.ruby.network.routers02.throttle0.msg_count.Response_Data::2 77304
-system.ruby.network.routers02.throttle0.msg_count.ResponseL2hit_Data::2 573
-system.ruby.network.routers02.throttle0.msg_count.ResponseLocal_Data::2 829
-system.ruby.network.routers02.throttle0.msg_count.Response_Control::2 380
-system.ruby.network.routers02.throttle0.msg_count.Writeback_Control::0 78663
-system.ruby.network.routers02.throttle0.msg_count.Forwarded_Control::0 832
-system.ruby.network.routers02.throttle0.msg_count.Invalidate_Control::0 240
-system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::2 5565888
-system.ruby.network.routers02.throttle0.msg_bytes.ResponseL2hit_Data::2 41256
-system.ruby.network.routers02.throttle0.msg_bytes.ResponseLocal_Data::2 59688
-system.ruby.network.routers02.throttle0.msg_bytes.Response_Control::2 3040
-system.ruby.network.routers02.throttle0.msg_bytes.Writeback_Control::0 629304
-system.ruby.network.routers02.throttle0.msg_bytes.Forwarded_Control::0 6656
-system.ruby.network.routers02.throttle0.msg_bytes.Invalidate_Control::0 1920
-system.ruby.network.routers02.throttle1.link_utilization 6.342910
-system.ruby.network.routers02.throttle1.msg_count.Request_Control::0 78709
-system.ruby.network.routers02.throttle1.msg_count.ResponseLocal_Data::2 832
-system.ruby.network.routers02.throttle1.msg_count.Response_Control::2 240
-system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::2 77646
-system.ruby.network.routers02.throttle1.msg_count.Writeback_Control::0 78666
-system.ruby.network.routers02.throttle1.msg_count.Unblock_Control::2 79474
-system.ruby.network.routers02.throttle1.msg_bytes.Request_Control::0 629672
-system.ruby.network.routers02.throttle1.msg_bytes.ResponseLocal_Data::2 59904
-system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::2 1920
-system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::2 5590512
-system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Control::0 629328
-system.ruby.network.routers02.throttle1.msg_bytes.Unblock_Control::2 635792
-system.ruby.network.routers03.throttle0.link_utilization 5.272579
-system.ruby.network.routers03.throttle0.msg_count.Response_Data::2 76851
-system.ruby.network.routers03.throttle0.msg_count.ResponseL2hit_Data::2 577
-system.ruby.network.routers03.throttle0.msg_count.ResponseLocal_Data::2 849
-system.ruby.network.routers03.throttle0.msg_count.Response_Control::2 394
-system.ruby.network.routers03.throttle0.msg_count.Writeback_Control::0 78228
-system.ruby.network.routers03.throttle0.msg_count.Forwarded_Control::0 860
-system.ruby.network.routers03.throttle0.msg_count.Invalidate_Control::0 224
-system.ruby.network.routers03.throttle0.msg_bytes.Response_Data::2 5533272
-system.ruby.network.routers03.throttle0.msg_bytes.ResponseL2hit_Data::2 41544
-system.ruby.network.routers03.throttle0.msg_bytes.ResponseLocal_Data::2 61128
-system.ruby.network.routers03.throttle0.msg_bytes.Response_Control::2 3152
-system.ruby.network.routers03.throttle0.msg_bytes.Writeback_Control::0 625824
-system.ruby.network.routers03.throttle0.msg_bytes.Forwarded_Control::0 6880
-system.ruby.network.routers03.throttle0.msg_bytes.Invalidate_Control::0 1792
-system.ruby.network.routers03.throttle1.link_utilization 6.308633
-system.ruby.network.routers03.throttle1.msg_count.Request_Control::0 78281
-system.ruby.network.routers03.throttle1.msg_count.ResponseLocal_Data::2 860
-system.ruby.network.routers03.throttle1.msg_count.Response_Control::2 224
-system.ruby.network.routers03.throttle1.msg_count.Writeback_Data::2 77193
-system.ruby.network.routers03.throttle1.msg_count.Writeback_Control::0 78232
-system.ruby.network.routers03.throttle1.msg_count.Unblock_Control::2 79079
-system.ruby.network.routers03.throttle1.msg_bytes.Request_Control::0 626248
-system.ruby.network.routers03.throttle1.msg_bytes.ResponseLocal_Data::2 61920
-system.ruby.network.routers03.throttle1.msg_bytes.Response_Control::2 1792
-system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Data::2 5557896
-system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Control::0 625856
-system.ruby.network.routers03.throttle1.msg_bytes.Unblock_Control::2 632632
-system.ruby.network.routers04.throttle0.link_utilization 5.273218
-system.ruby.network.routers04.throttle0.msg_count.Response_Data::2 76878
-system.ruby.network.routers04.throttle0.msg_count.ResponseL2hit_Data::2 592
-system.ruby.network.routers04.throttle0.msg_count.ResponseLocal_Data::2 818
-system.ruby.network.routers04.throttle0.msg_count.Response_Control::2 387
-system.ruby.network.routers04.throttle0.msg_count.Writeback_Control::0 78247
-system.ruby.network.routers04.throttle0.msg_count.Forwarded_Control::0 853
-system.ruby.network.routers04.throttle0.msg_count.Invalidate_Control::0 215
-system.ruby.network.routers04.throttle0.msg_bytes.Response_Data::2 5535216
-system.ruby.network.routers04.throttle0.msg_bytes.ResponseL2hit_Data::2 42624
-system.ruby.network.routers04.throttle0.msg_bytes.ResponseLocal_Data::2 58896
-system.ruby.network.routers04.throttle0.msg_bytes.Response_Control::2 3096
-system.ruby.network.routers04.throttle0.msg_bytes.Writeback_Control::0 625976
-system.ruby.network.routers04.throttle0.msg_bytes.Forwarded_Control::0 6824
-system.ruby.network.routers04.throttle0.msg_bytes.Invalidate_Control::0 1720
-system.ruby.network.routers04.throttle1.link_utilization 6.310597
-system.ruby.network.routers04.throttle1.msg_count.Request_Control::0 78290
-system.ruby.network.routers04.throttle1.msg_count.ResponseLocal_Data::2 853
-system.ruby.network.routers04.throttle1.msg_count.Response_Control::2 215
-system.ruby.network.routers04.throttle1.msg_count.Writeback_Data::2 77230
-system.ruby.network.routers04.throttle1.msg_count.Writeback_Control::0 78248
-system.ruby.network.routers04.throttle1.msg_count.Unblock_Control::2 79085
-system.ruby.network.routers04.throttle1.msg_bytes.Request_Control::0 626320
-system.ruby.network.routers04.throttle1.msg_bytes.ResponseLocal_Data::2 61416
-system.ruby.network.routers04.throttle1.msg_bytes.Response_Control::2 1720
-system.ruby.network.routers04.throttle1.msg_bytes.Writeback_Data::2 5560560
-system.ruby.network.routers04.throttle1.msg_bytes.Writeback_Control::0 625984
-system.ruby.network.routers04.throttle1.msg_bytes.Unblock_Control::2 632680
-system.ruby.network.routers05.throttle0.link_utilization 5.291728
-system.ruby.network.routers05.throttle0.msg_count.Response_Data::2 77119
-system.ruby.network.routers05.throttle0.msg_count.ResponseL2hit_Data::2 582
-system.ruby.network.routers05.throttle0.msg_count.ResponseLocal_Data::2 866
-system.ruby.network.routers05.throttle0.msg_count.Response_Control::2 379
-system.ruby.network.routers05.throttle0.msg_count.Writeback_Control::0 78519
-system.ruby.network.routers05.throttle0.msg_count.Forwarded_Control::0 785
-system.ruby.network.routers05.throttle0.msg_count.Invalidate_Control::0 264
-system.ruby.network.routers05.throttle0.msg_bytes.Response_Data::2 5552568
-system.ruby.network.routers05.throttle0.msg_bytes.ResponseL2hit_Data::2 41904
-system.ruby.network.routers05.throttle0.msg_bytes.ResponseLocal_Data::2 62352
-system.ruby.network.routers05.throttle0.msg_bytes.Response_Control::2 3032
-system.ruby.network.routers05.throttle0.msg_bytes.Writeback_Control::0 628152
-system.ruby.network.routers05.throttle0.msg_bytes.Forwarded_Control::0 6280
-system.ruby.network.routers05.throttle0.msg_bytes.Invalidate_Control::0 2112
-system.ruby.network.routers05.throttle1.link_utilization 6.328192
-system.ruby.network.routers05.throttle1.msg_count.Request_Control::0 78570
-system.ruby.network.routers05.throttle1.msg_count.ResponseLocal_Data::2 785
-system.ruby.network.routers05.throttle1.msg_count.Response_Control::2 264
-system.ruby.network.routers05.throttle1.msg_count.Writeback_Data::2 77495
-system.ruby.network.routers05.throttle1.msg_count.Writeback_Control::0 78521
-system.ruby.network.routers05.throttle1.msg_count.Unblock_Control::2 79327
-system.ruby.network.routers05.throttle1.msg_bytes.Request_Control::0 628560
-system.ruby.network.routers05.throttle1.msg_bytes.ResponseLocal_Data::2 56520
-system.ruby.network.routers05.throttle1.msg_bytes.Response_Control::2 2112
-system.ruby.network.routers05.throttle1.msg_bytes.Writeback_Data::2 5579640
-system.ruby.network.routers05.throttle1.msg_bytes.Writeback_Control::0 628168
-system.ruby.network.routers05.throttle1.msg_bytes.Unblock_Control::2 634616
-system.ruby.network.routers06.throttle0.link_utilization 5.285266
-system.ruby.network.routers06.throttle0.msg_count.Response_Data::2 77081
-system.ruby.network.routers06.throttle0.msg_count.ResponseL2hit_Data::2 559
-system.ruby.network.routers06.throttle0.msg_count.ResponseLocal_Data::2 831
-system.ruby.network.routers06.throttle0.msg_count.Response_Control::2 373
-system.ruby.network.routers06.throttle0.msg_count.Writeback_Control::0 78429
-system.ruby.network.routers06.throttle0.msg_count.Forwarded_Control::0 823
-system.ruby.network.routers06.throttle0.msg_count.Invalidate_Control::0 222
-system.ruby.network.routers06.throttle0.msg_bytes.Response_Data::2 5549832
-system.ruby.network.routers06.throttle0.msg_bytes.ResponseL2hit_Data::2 40248
-system.ruby.network.routers06.throttle0.msg_bytes.ResponseLocal_Data::2 59832
-system.ruby.network.routers06.throttle0.msg_bytes.Response_Control::2 2984
-system.ruby.network.routers06.throttle0.msg_bytes.Writeback_Control::0 627432
-system.ruby.network.routers06.throttle0.msg_bytes.Forwarded_Control::0 6584
-system.ruby.network.routers06.throttle0.msg_bytes.Invalidate_Control::0 1776
-system.ruby.network.routers06.throttle1.link_utilization 6.323499
-system.ruby.network.routers06.throttle1.msg_count.Request_Control::0 78475
-system.ruby.network.routers06.throttle1.msg_count.ResponseLocal_Data::2 823
-system.ruby.network.routers06.throttle1.msg_count.Response_Control::2 222
-system.ruby.network.routers06.throttle1.msg_count.Writeback_Data::2 77412
-system.ruby.network.routers06.throttle1.msg_count.Writeback_Control::0 78431
-system.ruby.network.routers06.throttle1.msg_count.Unblock_Control::2 79261
-system.ruby.network.routers06.throttle1.msg_bytes.Request_Control::0 627800
-system.ruby.network.routers06.throttle1.msg_bytes.ResponseLocal_Data::2 59256
-system.ruby.network.routers06.throttle1.msg_bytes.Response_Control::2 1776
-system.ruby.network.routers06.throttle1.msg_bytes.Writeback_Data::2 5573664
-system.ruby.network.routers06.throttle1.msg_bytes.Writeback_Control::0 627448
-system.ruby.network.routers06.throttle1.msg_bytes.Unblock_Control::2 634088
-system.ruby.network.routers07.throttle0.link_utilization 5.268249
-system.ruby.network.routers07.throttle0.msg_count.Response_Data::2 76772
-system.ruby.network.routers07.throttle0.msg_count.ResponseL2hit_Data::2 582
-system.ruby.network.routers07.throttle0.msg_count.ResponseLocal_Data::2 868
-system.ruby.network.routers07.throttle0.msg_count.Response_Control::2 365
-system.ruby.network.routers07.throttle0.msg_count.Writeback_Control::0 78188
-system.ruby.network.routers07.throttle0.msg_count.Forwarded_Control::0 778
-system.ruby.network.routers07.throttle0.msg_count.Invalidate_Control::0 226
-system.ruby.network.routers07.throttle0.msg_bytes.Response_Data::2 5527584
-system.ruby.network.routers07.throttle0.msg_bytes.ResponseL2hit_Data::2 41904
-system.ruby.network.routers07.throttle0.msg_bytes.ResponseLocal_Data::2 62496
-system.ruby.network.routers07.throttle0.msg_bytes.Response_Control::2 2920
-system.ruby.network.routers07.throttle0.msg_bytes.Writeback_Control::0 625504
-system.ruby.network.routers07.throttle0.msg_bytes.Forwarded_Control::0 6224
-system.ruby.network.routers07.throttle0.msg_bytes.Invalidate_Control::0 1808
-system.ruby.network.routers07.throttle1.link_utilization 6.301022
-system.ruby.network.routers07.throttle1.msg_count.Request_Control::0 78224
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-system.ruby.LD.latency_hist_seqr | 304613 75.53% 75.53% | 66895 16.59% 92.12% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00%
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-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.LD.miss_latency_hist_seqr | 304507 75.52% 75.52% | 66895 16.59% 92.11% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00%
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-system.ruby.ST.latency_hist_seqr | 169296 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.25% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00%
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-system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 35 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.ST.miss_latency_hist_seqr | 169261 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.26% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00%
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-system.ruby.Directory_Controller.IS.Unblock 143585 0.00% 0.00%
-system.ruby.Directory_Controller.IS.Memory_Data 143590 0.00% 0.00%
-system.ruby.Directory_Controller.IS.Memory_Ack 112 0.00% 0.00%
-system.ruby.Directory_Controller.SS.GETX 3 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock 250191 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Memory_Data 250195 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock 222014 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Memory_Data 222024 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Memory_Ack 60 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback 221890 0.00% 0.00%
-system.ruby.Directory_Controller.MIS.Dirty_Writeback 105 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50374 12.49% 12.49% | 50325 12.48% 24.96% | 50647 12.56% 37.52% | 50182 12.44% 49.96% | 50433 12.50% 62.46% | 50587 12.54% 75.00% | 50571 12.54% 87.54% | 50265 12.46% 100.00%
-system.ruby.L1Cache_Controller.Load::total 403384
-system.ruby.L1Cache_Controller.Store | 27948 12.47% 12.47% | 28058 12.52% 25.00% | 28087 12.54% 37.53% | 28119 12.55% 50.08% | 27905 12.45% 62.54% | 28006 12.50% 75.04% | 27945 12.47% 87.51% | 27982 12.49% 100.00%
-system.ruby.L1Cache_Controller.Store::total 224050
-system.ruby.L1Cache_Controller.L1_Replacement | 9444943 12.51% 12.51% | 9438529 12.50% 25.01% | 9427861 12.49% 37.50% | 9443150 12.51% 50.00% | 9440429 12.50% 62.51% | 9432698 12.49% 75.00% | 9432851 12.49% 87.49% | 9442432 12.51% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 75502893
-system.ruby.L1Cache_Controller.Fwd_GETX | 175 13.50% 13.50% | 165 12.73% 26.23% | 169 13.04% 39.27% | 177 13.66% 52.93% | 160 12.35% 65.28% | 143 11.03% 76.31% | 171 13.19% 89.51% | 136 10.49% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 1296
-system.ruby.L1Cache_Controller.Fwd_GETS | 752 13.09% 13.09% | 775 13.49% 26.58% | 721 12.55% 39.12% | 733 12.76% 51.88% | 720 12.53% 64.41% | 672 11.70% 76.11% | 694 12.08% 88.18% | 679 11.82% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 5746
-system.ruby.L1Cache_Controller.Inv | 239 12.86% 12.86% | 228 12.27% 25.13% | 240 12.92% 38.05% | 224 12.06% 50.11% | 215 11.57% 61.68% | 264 14.21% 75.89% | 222 11.95% 87.84% | 226 12.16% 100.00%
-system.ruby.L1Cache_Controller.Inv::total 1858
-system.ruby.L1Cache_Controller.Ack | 365 11.96% 11.96% | 408 13.37% 25.34% | 380 12.45% 37.79% | 394 12.91% 50.70% | 387 12.68% 63.39% | 379 12.42% 75.81% | 373 12.23% 88.04% | 365 11.96% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 3051
-system.ruby.L1Cache_Controller.Data | 50182 12.49% 12.49% | 50097 12.47% 24.96% | 50442 12.56% 37.52% | 49978 12.44% 49.96% | 50201 12.50% 62.46% | 50372 12.54% 75.00% | 50365 12.54% 87.54% | 50046 12.46% 100.00%
-system.ruby.L1Cache_Controller.Data::total 401683
-system.ruby.L1Cache_Controller.Exclusive_Data | 28069 12.45% 12.45% | 28274 12.54% 24.99% | 28264 12.54% 37.52% | 28299 12.55% 50.08% | 28087 12.46% 62.53% | 28195 12.50% 75.04% | 28106 12.47% 87.50% | 28176 12.50% 100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total 225470
-system.ruby.L1Cache_Controller.Writeback_Ack | 637 12.18% 12.18% | 690 13.19% 25.36% | 632 12.08% 37.44% | 666 12.73% 50.17% | 656 12.54% 62.71% | 638 12.19% 74.90% | 639 12.21% 87.12% | 674 12.88% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 5232
-system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77320 12.48% 12.48% | 77396 12.49% 24.97% | 77782 12.55% 37.52% | 77329 12.48% 50.00% | 77371 12.49% 62.49% | 77618 12.53% 75.01% | 77563 12.52% 87.53% | 77279 12.47% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 619658
-system.ruby.L1Cache_Controller.Writeback_Nack | 246 12.91% 12.91% | 232 12.18% 25.09% | 249 13.07% 38.16% | 233 12.23% 50.39% | 220 11.55% 61.94% | 263 13.81% 75.75% | 227 11.92% 87.66% | 235 12.34% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total 1905
-system.ruby.L1Cache_Controller.All_acks | 27913 12.46% 12.46% | 28056 12.53% 24.99% | 28076 12.54% 37.53% | 28112 12.55% 50.08% | 27887 12.45% 62.53% | 27999 12.50% 75.03% | 27936 12.47% 87.51% | 27976 12.49% 100.00%
-system.ruby.L1Cache_Controller.All_acks::total 223955
-system.ruby.L1Cache_Controller.Use_Timeout | 28069 12.45% 12.45% | 28272 12.54% 24.99% | 28263 12.54% 37.52% | 28299 12.55% 50.08% | 28087 12.46% 62.53% | 28195 12.51% 75.04% | 28106 12.47% 87.50% | 28175 12.50% 100.00%
-system.ruby.L1Cache_Controller.Use_Timeout::total 225466
-system.ruby.L1Cache_Controller.I.Load | 50341 12.49% 12.49% | 50316 12.48% 24.96% | 50632 12.56% 37.52% | 50168 12.44% 49.96% | 50401 12.50% 62.46% | 50569 12.54% 75.00% | 50536 12.53% 87.54% | 50248 12.46% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 403211
-system.ruby.L1Cache_Controller.I.Store | 27912 12.46% 12.46% | 28052 12.53% 24.99% | 28073 12.54% 37.53% | 28110 12.55% 50.08% | 27883 12.45% 62.53% | 28000 12.50% 75.03% | 27934 12.47% 87.51% | 27974 12.49% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 223938
-system.ruby.L1Cache_Controller.I.L1_Replacement | 62 14.80% 14.80% | 57 13.60% 28.40% | 54 12.89% 41.29% | 60 14.32% 55.61% | 45 10.74% 66.35% | 54 12.89% 79.24% | 45 10.74% 89.98% | 42 10.02% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 419
-system.ruby.L1Cache_Controller.S.Load | 7 13.46% 13.46% | 6 11.54% 25.00% | 5 9.62% 34.62% | 5 9.62% 44.23% | 9 17.31% 61.54% | 4 7.69% 69.23% | 8 15.38% 84.62% | 8 15.38% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 52
-system.ruby.L1Cache_Controller.S.Store | 1 3.85% 3.85% | 4 15.38% 19.23% | 4 15.38% 34.62% | 3 11.54% 46.15% | 6 23.08% 69.23% | 1 3.85% 73.08% | 5 19.23% 92.31% | 2 7.69% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 26
-system.ruby.L1Cache_Controller.S.L1_Replacement | 50169 12.49% 12.49% | 50086 12.47% 24.96% | 50429 12.56% 37.52% | 49967 12.44% 49.96% | 50185 12.50% 62.46% | 50360 12.54% 75.00% | 50354 12.54% 87.54% | 50040 12.46% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 401590
-system.ruby.L1Cache_Controller.S.Fwd_GETS | 33 9.38% 9.38% | 53 15.06% 24.43% | 45 12.78% 37.22% | 42 11.93% 49.15% | 49 13.92% 63.07% | 42 11.93% 75.00% | 44 12.50% 87.50% | 44 12.50% 100.00%
-system.ruby.L1Cache_Controller.S.Fwd_GETS::total 352
-system.ruby.L1Cache_Controller.S.Inv | 11 17.74% 17.74% | 6 9.68% 27.42% | 9 14.52% 41.94% | 8 12.90% 54.84% | 8 12.90% 67.74% | 10 16.13% 83.87% | 6 9.68% 93.55% | 4 6.45% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 62
-system.ruby.L1Cache_Controller.O.L1_Replacement | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total 6
-system.ruby.L1Cache_Controller.M.L1_Replacement | 153 10.15% 10.15% | 217 14.39% 24.54% | 188 12.47% 37.00% | 186 12.33% 49.34% | 200 13.26% 62.60% | 196 13.00% 75.60% | 170 11.27% 86.87% | 198 13.13% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 1508
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 1
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 6
-system.ruby.L1Cache_Controller.M_W.L1_Replacement | 567 12.42% 12.42% | 715 15.67% 28.09% | 542 11.88% 39.96% | 587 12.86% 52.83% | 335 7.34% 60.17% | 455 9.97% 70.14% | 721 15.80% 85.93% | 642 14.07% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4564
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 4 57.14% 57.14% | 2 28.57% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 7
-system.ruby.L1Cache_Controller.M_W.Use_Timeout | 156 10.30% 10.30% | 218 14.39% 24.69% | 188 12.41% 37.10% | 187 12.34% 49.44% | 200 13.20% 62.64% | 196 12.94% 75.58% | 170 11.22% 86.80% | 200 13.20% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1515
-system.ruby.L1Cache_Controller.MM.Load | 1 7.14% 7.14% | 1 7.14% 14.29% | 2 14.29% 28.57% | 1 7.14% 35.71% | 3 21.43% 57.14% | 0 0.00% 57.14% | 3 21.43% 78.57% | 3 21.43% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 14
-system.ruby.L1Cache_Controller.MM.Store | 3 25.00% 25.00% | 1 8.33% 33.33% | 2 16.67% 50.00% | 1 8.33% 58.33% | 1 8.33% 66.67% | 0 0.00% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 12
-system.ruby.L1Cache_Controller.MM.L1_Replacement | 27862 12.46% 12.46% | 28003 12.52% 24.99% | 28030 12.54% 37.52% | 28061 12.55% 50.07% | 27850 12.46% 62.53% | 27955 12.50% 75.03% | 27897 12.48% 87.51% | 27936 12.49% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total 223594
-system.ruby.L1Cache_Controller.MM.Fwd_GETX | 13 11.61% 11.61% | 18 16.07% 27.68% | 15 13.39% 41.07% | 20 17.86% 58.93% | 13 11.61% 70.54% | 16 14.29% 84.82% | 5 4.46% 89.29% | 12 10.71% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 112
-system.ruby.L1Cache_Controller.MM.Fwd_GETS | 38 15.57% 15.57% | 33 13.52% 29.10% | 30 12.30% 41.39% | 31 12.70% 54.10% | 24 9.84% 63.93% | 28 11.48% 75.41% | 34 13.93% 89.34% | 26 10.66% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 244
-system.ruby.L1Cache_Controller.MM_W.Load | 5 12.50% 12.50% | 0 0.00% 12.50% | 5 12.50% 25.00% | 6 15.00% 40.00% | 8 20.00% 60.00% | 5 12.50% 72.50% | 7 17.50% 90.00% | 4 10.00% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 40
-system.ruby.L1Cache_Controller.MM_W.Store | 6 26.09% 26.09% | 1 4.35% 30.43% | 5 21.74% 52.17% | 4 17.39% 69.57% | 2 8.70% 78.26% | 2 8.70% 86.96% | 2 8.70% 95.65% | 1 4.35% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total 23
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 618993 12.55% 12.55% | 615472 12.48% 25.04% | 618093 12.54% 37.57% | 615714 12.49% 50.06% | 613249 12.44% 62.50% | 615741 12.49% 74.99% | 616966 12.51% 87.50% | 616397 12.50% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4930625
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 17 16.50% 16.50% | 12 11.65% 28.16% | 18 17.48% 45.63% | 20 19.42% 65.05% | 5 4.85% 69.90% | 4 3.88% 73.79% | 14 13.59% 87.38% | 13 12.62% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 103
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 33 14.29% 14.29% | 29 12.55% 26.84% | 40 17.32% 44.16% | 30 12.99% 57.14% | 22 9.52% 66.67% | 26 11.26% 77.92% | 28 12.12% 90.04% | 23 9.96% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 231
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27913 12.46% 12.46% | 28054 12.53% 24.99% | 28075 12.54% 37.53% | 28112 12.55% 50.08% | 27887 12.45% 62.53% | 27999 12.50% 75.03% | 27936 12.47% 87.51% | 27975 12.49% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 223951
-system.ruby.L1Cache_Controller.IM.L1_Replacement | 3111214 12.42% 12.42% | 3124415 12.47% 24.89% | 3120162 12.45% 37.34% | 3163564 12.63% 49.97% | 3121043 12.46% 62.43% | 3124051 12.47% 74.89% | 3147596 12.56% 87.46% | 3142627 12.54% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25054672
-system.ruby.L1Cache_Controller.IM.Ack | 130 10.89% 10.89% | 165 13.82% 24.71% | 151 12.65% 37.35% | 153 12.81% 50.17% | 141 11.81% 61.98% | 157 13.15% 75.13% | 151 12.65% 87.77% | 146 12.23% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 1194
-system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27912 12.46% 12.46% | 28052 12.53% 24.99% | 28072 12.54% 37.53% | 28109 12.55% 50.08% | 27881 12.45% 62.53% | 27998 12.50% 75.03% | 27931 12.47% 87.51% | 27974 12.49% 100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 223929
-system.ruby.L1Cache_Controller.SM.L1_Replacement | 481 11.34% 11.34% | 642 15.13% 26.47% | 663 15.63% 42.10% | 403 9.50% 51.60% | 896 21.12% 72.73% | 30 0.71% 73.43% | 885 20.86% 94.30% | 242 5.70% 100.00%
-system.ruby.L1Cache_Controller.SM.L1_Replacement::total 4242
-system.ruby.L1Cache_Controller.SM.Exclusive_Data | 1 3.85% 3.85% | 4 15.38% 19.23% | 4 15.38% 34.62% | 3 11.54% 46.15% | 6 23.08% 69.23% | 1 3.85% 73.08% | 5 19.23% 92.31% | 2 7.69% 100.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 26
-system.ruby.L1Cache_Controller.OM.L1_Replacement | 22139 12.48% 12.48% | 23425 13.21% 25.69% | 21656 12.21% 37.90% | 22952 12.94% 50.84% | 22585 12.73% 63.57% | 21353 12.04% 75.61% | 22440 12.65% 88.26% | 20828 11.74% 100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total 177378
-system.ruby.L1Cache_Controller.OM.Ack | 235 12.65% 12.65% | 243 13.09% 25.74% | 229 12.33% 38.07% | 241 12.98% 51.05% | 246 13.25% 64.30% | 222 11.95% 76.25% | 222 11.95% 88.21% | 219 11.79% 100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total 1857
-system.ruby.L1Cache_Controller.OM.All_acks | 27913 12.46% 12.46% | 28056 12.53% 24.99% | 28076 12.54% 37.53% | 28112 12.55% 50.08% | 27887 12.45% 62.53% | 27999 12.50% 75.03% | 27936 12.47% 87.51% | 27976 12.49% 100.00%
-system.ruby.L1Cache_Controller.OM.All_acks::total 223955
-system.ruby.L1Cache_Controller.IS.L1_Replacement | 5613300 12.56% 12.56% | 5595496 12.52% 25.07% | 5588044 12.50% 37.57% | 5561656 12.44% 50.01% | 5604041 12.54% 62.55% | 5592503 12.51% 75.06% | 5565777 12.45% 87.51% | 5583478 12.49% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44704295
-system.ruby.L1Cache_Controller.IS.Data | 50182 12.49% 12.49% | 50097 12.47% 24.96% | 50442 12.56% 37.52% | 49978 12.44% 49.96% | 50201 12.50% 62.46% | 50372 12.54% 75.00% | 50365 12.54% 87.54% | 50046 12.46% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 401683
-system.ruby.L1Cache_Controller.IS.Exclusive_Data | 156 10.30% 10.30% | 218 14.39% 24.69% | 188 12.41% 37.10% | 187 12.34% 49.44% | 200 13.20% 62.64% | 196 12.94% 75.58% | 170 11.22% 86.80% | 200 13.20% 100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1515
-system.ruby.L1Cache_Controller.SI.Load | 11 26.19% 26.19% | 1 2.38% 28.57% | 2 4.76% 33.33% | 1 2.38% 35.71% | 1 2.38% 38.10% | 9 21.43% 59.52% | 16 38.10% 97.62% | 1 2.38% 100.00%
-system.ruby.L1Cache_Controller.SI.Load::total 42
-system.ruby.L1Cache_Controller.SI.Store | 15 41.67% 41.67% | 0 0.00% 41.67% | 2 5.56% 47.22% | 1 2.78% 50.00% | 13 36.11% 86.11% | 1 2.78% 88.89% | 0 0.00% 88.89% | 4 11.11% 100.00%
-system.ruby.L1Cache_Controller.SI.Store::total 36
-system.ruby.L1Cache_Controller.SI.Fwd_GETS | 394 13.59% 13.59% | 405 13.97% 27.56% | 386 13.31% 40.88% | 361 12.45% 53.33% | 355 12.25% 65.57% | 314 10.83% 76.41% | 339 11.69% 88.10% | 345 11.90% 100.00%
-system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2899
-system.ruby.L1Cache_Controller.SI.Inv | 228 12.69% 12.69% | 222 12.36% 25.06% | 231 12.86% 37.92% | 216 12.03% 49.94% | 207 11.53% 61.47% | 254 14.14% 75.61% | 216 12.03% 87.64% | 222 12.36% 100.00%
-system.ruby.L1Cache_Controller.SI.Inv::total 1796
-system.ruby.L1Cache_Controller.SI.Writeback_Ack | 637 12.19% 12.19% | 688 13.17% 25.36% | 631 12.08% 37.44% | 665 12.73% 50.16% | 655 12.54% 62.70% | 637 12.19% 74.89% | 639 12.23% 87.12% | 673 12.88% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5225
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49302 12.50% 12.50% | 49175 12.46% 24.96% | 49565 12.56% 37.52% | 49084 12.44% 49.96% | 49323 12.50% 62.46% | 49467 12.54% 75.00% | 49498 12.55% 87.54% | 49145 12.46% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 394559
-system.ruby.L1Cache_Controller.OI.Fwd_GETX | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 4
-system.ruby.L1Cache_Controller.OI.Fwd_GETS | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 6
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 250 12.48% 12.48% | 250 12.48% 24.96% | 218 10.88% 35.85% | 269 13.43% 49.28% | 269 13.43% 62.71% | 262 13.08% 75.79% | 248 12.38% 88.17% | 237 11.83% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 2003
-system.ruby.L1Cache_Controller.OI.Writeback_Nack | 18 15.79% 15.79% | 12 10.53% 26.32% | 19 16.67% 42.98% | 18 15.79% 58.77% | 13 11.40% 70.18% | 10 8.77% 78.95% | 10 8.77% 87.72% | 14 12.28% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 114
-system.ruby.L1Cache_Controller.MI.Load | 9 36.00% 36.00% | 1 4.00% 40.00% | 1 4.00% 44.00% | 1 4.00% 48.00% | 11 44.00% 92.00% | 0 0.00% 92.00% | 1 4.00% 96.00% | 1 4.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Load::total 25
-system.ruby.L1Cache_Controller.MI.Store | 10 71.43% 71.43% | 0 0.00% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 0 0.00% 78.57% | 2 14.29% 92.86% | 1 7.14% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Store::total 14
-system.ruby.L1Cache_Controller.MI.Fwd_GETX | 145 13.48% 13.48% | 134 12.45% 25.93% | 134 12.45% 38.38% | 136 12.64% 51.02% | 142 13.20% 64.22% | 123 11.43% 75.65% | 151 14.03% 89.68% | 111 10.32% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1076
-system.ruby.L1Cache_Controller.MI.Fwd_GETS | 247 12.34% 12.34% | 250 12.49% 24.84% | 220 10.99% 35.83% | 269 13.44% 49.28% | 269 13.44% 62.72% | 262 13.09% 75.81% | 249 12.44% 88.26% | 235 11.74% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 2001
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27623 12.44% 12.44% | 27836 12.54% 24.98% | 27863 12.55% 37.53% | 27840 12.54% 50.07% | 27638 12.45% 62.52% | 27766 12.51% 75.02% | 27666 12.46% 87.48% | 27786 12.52% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 222018
-system.ruby.L1Cache_Controller.II.Store | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.II.Store::total 1
-system.ruby.L1Cache_Controller.II.Writeback_Ack | 0 0.00% 0.00% | 2 28.57% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total 7
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 145 13.45% 13.45% | 135 12.52% 25.97% | 136 12.62% 38.59% | 136 12.62% 51.21% | 141 13.08% 64.29% | 123 11.41% 75.70% | 151 14.01% 89.70% | 111 10.30% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1078
-system.ruby.L1Cache_Controller.II.Writeback_Nack | 228 12.73% 12.73% | 220 12.28% 25.01% | 230 12.84% 37.86% | 215 12.00% 49.86% | 207 11.56% 61.42% | 253 14.13% 75.54% | 217 12.12% 87.66% | 221 12.34% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1791
-system.ruby.L2Cache_Controller.L1_GETS 505918 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 279265 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTO 147 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 260754 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 476678 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS 26071 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 222022 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 615806 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 394559 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 224021 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 221995 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 407986 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 225463 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 692184 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 393786 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 218821 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETS 3251 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX 1863 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391321 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS 3238 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETS 2251 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETX 1189 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTO 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 223094 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTS 1786 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTO 115 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTX 114 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1886 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 119 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS 2609 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX 1332 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 390668 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETX 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1779 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS 11 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L2_Replacement 105 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETS 19 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETX 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3291 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS 27 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement 2548 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1271 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 737 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_PUTS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 221899 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETS 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 21 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1591 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 115 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.Unblock 119 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 31 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 20 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 49 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4911 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 39 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1888 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.Unblock 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L1_PUTS 64 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.Unblock 27 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L2_Replacement 207 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_GETS 123 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_GETX 47 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_PUTS 12315 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3238 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETS 16878 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETX 8637 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391321 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETS 72 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETX 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.Unblock 3291 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L2_Replacement 23701 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETS 55 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETX 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.Unblock 1779 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L2_Replacement 9622 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_PUTS_only 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 36 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.Unblock 11 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 100 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETS 6543 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETX 3771 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1449 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_PUTS 29 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 222018 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.Unblock 1076 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_GETS 210 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_GETX 110 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28110 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_PUTS 313 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.Unblock 3251 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.Unblock 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 222 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 77 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 32390 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 148 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Unblock 2007 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1434 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 21 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOSX.Unblock 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 30 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 20 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETS 49192 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETX 27678 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_PUTS 7782 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 393784 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 393777 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.L1_GETS 22557 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.L1_GETX 11373 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 220151 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_GETS 194 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_GETX 129 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 29583 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 113 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data 1871 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETS 5723 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETX 2924 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTX 114 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 17056 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTS 123 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 222022 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 222014 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETS 25 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 737 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 75 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTS 24 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.Unblock 2609 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 30888 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETS 27 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETX 19 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1271 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L2_Replacement 12369 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 20 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.Unblock 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 83 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.Unblock 19 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L2_Replacement 75 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETS 747 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETX 366 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 221890 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 329 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSI.L1_PUTS 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 105 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu1]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu2]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl2.sequencer.slave[0]
-
-[system.cpu3]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl3.sequencer.slave[0]
-
-[system.cpu4]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl4.sequencer.slave[0]
-
-[system.cpu5]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl5.sequencer.slave[0]
-
-[system.cpu6]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl6.sequencer.slave[0]
-
-[system.cpu7]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl7.sequencer.slave[0]
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
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-write_buffer_size=64
-write_high_thresh_perc=85
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-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
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-access_backing_store=false
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-
-[system.ruby.clk_domain]
-type=SrcClockDomain
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-domain_id=-1
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-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
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-number_of_TBEs=256
-persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
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-reissue_wakeup_latency=10
-requestFromDir=system.ruby.dir_cntrl0.requestFromDir
-requestToDir=system.ruby.dir_cntrl0.requestToDir
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-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
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-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[31]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[30]
-
-[system.ruby.dir_cntrl0.persistentFromDir]
-type=MessageBuffer
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-ordered=true
-randomization=false
-master=system.ruby.network.slave[29]
-
-[system.ruby.dir_cntrl0.persistentToDir]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
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-slave=system.ruby.network.master[30]
-
-[system.ruby.dir_cntrl0.requestFromDir]
-type=MessageBuffer
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-ordered=false
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-master=system.ruby.network.slave[27]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
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-slave=system.ruby.network.master[28]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
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-master=system.ruby.network.slave[28]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
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-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
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-slave=system.ruby.network.master[29]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
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-N_tokens=9
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-no_mig_atomic=true
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-recycle_latency=10
-reissue_wakeup_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
-retry_threshold=1
-ruby_system=system.ruby
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-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
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-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
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-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
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-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
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-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
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-start_index_bit=6
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-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
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-size=256
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl0.persistentFromL1Cache]
-type=MessageBuffer
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-master=system.ruby.network.slave[2]
-
-[system.ruby.l1_cntrl0.persistentToL1Cache]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
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-slave=system.ruby.network.master[2]
-
-[system.ruby.l1_cntrl0.requestFromL1Cache]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.requestToL1Cache]
-type=MessageBuffer
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-ordered=false
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-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.responseFromL1Cache]
-type=MessageBuffer
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-ordered=false
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-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
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-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
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-slave=system.cpu0.port
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer
-L1Dcache=system.ruby.l1_cntrl1.L1Dcache
-L1Icache=system.ruby.l1_cntrl1.L1Icache
-N_tokens=9
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-persistentToL1Cache=system.ruby.l1_cntrl1.persistentToL1Cache
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-requestFromL1Cache=system.ruby.l1_cntrl1.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl1.requestToL1Cache
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-
-[system.ruby.l1_cntrl1.L1Dcache]
-type=RubyCache
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-
-[system.ruby.l1_cntrl1.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl1.L1Icache]
-type=RubyCache
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-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl1.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl1.mandatoryQueue]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl1.persistentFromL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl1.persistentToL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl1.requestFromL1Cache]
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-
-[system.ruby.l1_cntrl1.requestToL1Cache]
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-
-[system.ruby.l1_cntrl1.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl1.responseToL1Cache]
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-
-[system.ruby.l1_cntrl1.sequencer]
-type=RubySequencer
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-
-[system.ruby.l1_cntrl2]
-type=L1Cache_Controller
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-
-[system.ruby.l1_cntrl2.L1Dcache]
-type=RubyCache
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-
-[system.ruby.l1_cntrl2.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl2.L1Icache]
-type=RubyCache
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-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl2.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl2.mandatoryQueue]
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-
-[system.ruby.l1_cntrl2.persistentFromL1Cache]
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-
-[system.ruby.l1_cntrl2.persistentToL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl2.requestFromL1Cache]
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-
-[system.ruby.l1_cntrl2.requestToL1Cache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl2.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl2.responseToL1Cache]
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-
-[system.ruby.l1_cntrl2.sequencer]
-type=RubySequencer
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-
-[system.ruby.l1_cntrl3]
-type=L1Cache_Controller
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-
-[system.ruby.l1_cntrl3.L1Dcache]
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-
-[system.ruby.l1_cntrl3.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl3.L1Icache]
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-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl3.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl3.mandatoryQueue]
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-
-[system.ruby.l1_cntrl3.persistentFromL1Cache]
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-
-[system.ruby.l1_cntrl3.persistentToL1Cache]
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-
-[system.ruby.l1_cntrl3.requestFromL1Cache]
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-
-[system.ruby.l1_cntrl3.requestToL1Cache]
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-
-[system.ruby.l1_cntrl3.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl3.responseToL1Cache]
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-
-[system.ruby.l1_cntrl3.sequencer]
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-
-[system.ruby.l1_cntrl4]
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-
-[system.ruby.l1_cntrl4.L1Dcache]
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-
-[system.ruby.l1_cntrl4.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl4.L1Icache]
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-
-[system.ruby.l1_cntrl4.L1Icache.replacement_policy]
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-
-[system.ruby.l1_cntrl4.mandatoryQueue]
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-
-[system.ruby.l1_cntrl4.persistentFromL1Cache]
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-
-[system.ruby.l1_cntrl4.persistentToL1Cache]
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-
-[system.ruby.l1_cntrl4.requestFromL1Cache]
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-
-[system.ruby.l1_cntrl4.requestToL1Cache]
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-
-[system.ruby.l1_cntrl4.responseFromL1Cache]
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-
-[system.ruby.l1_cntrl4.responseToL1Cache]
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-
-[system.ruby.l1_cntrl4.sequencer]
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-
-[system.ruby.l1_cntrl5]
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-
-[system.ruby.l1_cntrl5.L1Dcache]
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-
-[system.ruby.l1_cntrl5.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl5.L1Icache]
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-
-[system.ruby.l1_cntrl5.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl5.mandatoryQueue]
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-[system.ruby.l1_cntrl5.persistentFromL1Cache]
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-
-[system.ruby.l1_cntrl5.persistentToL1Cache]
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-
-[system.ruby.l1_cntrl5.requestFromL1Cache]
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-[system.ruby.l1_cntrl5.requestToL1Cache]
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-[system.ruby.l1_cntrl5.responseFromL1Cache]
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-[system.ruby.l1_cntrl5.responseToL1Cache]
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-
-[system.ruby.l1_cntrl5.sequencer]
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-[system.ruby.l1_cntrl6]
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-[system.ruby.l1_cntrl6.L1Dcache]
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-
-[system.ruby.l1_cntrl6.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl6.L1Icache]
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-
-[system.ruby.l1_cntrl6.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl6.mandatoryQueue]
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-[system.ruby.l1_cntrl6.persistentFromL1Cache]
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-[system.ruby.l1_cntrl6.persistentToL1Cache]
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-[system.ruby.l1_cntrl6.requestFromL1Cache]
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-[system.ruby.l1_cntrl6.requestToL1Cache]
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-[system.ruby.l1_cntrl6.responseFromL1Cache]
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-[system.ruby.l1_cntrl6.responseToL1Cache]
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-[system.ruby.l1_cntrl6.sequencer]
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-[system.ruby.l1_cntrl7]
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-
-[system.ruby.l1_cntrl7.L1Dcache]
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-
-[system.ruby.l1_cntrl7.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl7.L1Icache]
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-
-[system.ruby.l1_cntrl7.L1Icache.replacement_policy]
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-
-[system.ruby.l1_cntrl7.mandatoryQueue]
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-
-[system.ruby.l1_cntrl7.persistentFromL1Cache]
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-
-[system.ruby.l1_cntrl7.persistentToL1Cache]
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-[system.ruby.l1_cntrl7.requestFromL1Cache]
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-[system.ruby.l1_cntrl7.requestToL1Cache]
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-[system.ruby.l1_cntrl7.responseFromL1Cache]
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-[system.ruby.l1_cntrl7.responseToL1Cache]
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-[system.ruby.l1_cntrl7.sequencer]
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-
-[system.ruby.l2_cntrl0]
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-GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache
-L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
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-[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache]
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-[system.ruby.l2_cntrl0.GlobalRequestToL2Cache]
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-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
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-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
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-[system.ruby.l2_cntrl0.L2cache]
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-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
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-[system.ruby.l2_cntrl0.persistentToL2Cache]
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-[system.ruby.l2_cntrl0.responseFromL2Cache]
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-[system.ruby.l2_cntrl0.responseToL2Cache]
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-[system.ruby.memctrl_clk_domain]
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-[system.ruby.network]
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-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9
-netifs=
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-slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.persistentFromL1Cache.master system.ruby.l1_cntrl1.requestFromL1Cache.master system.ruby.l1_cntrl1.responseFromL1Cache.master system.ruby.l1_cntrl1.persistentFromL1Cache.master system.ruby.l1_cntrl2.requestFromL1Cache.master system.ruby.l1_cntrl2.responseFromL1Cache.master system.ruby.l1_cntrl2.persistentFromL1Cache.master system.ruby.l1_cntrl3.requestFromL1Cache.master system.ruby.l1_cntrl3.responseFromL1Cache.master system.ruby.l1_cntrl3.persistentFromL1Cache.master system.ruby.l1_cntrl4.requestFromL1Cache.master system.ruby.l1_cntrl4.responseFromL1Cache.master system.ruby.l1_cntrl4.persistentFromL1Cache.master system.ruby.l1_cntrl5.requestFromL1Cache.master system.ruby.l1_cntrl5.responseFromL1Cache.master system.ruby.l1_cntrl5.persistentFromL1Cache.master system.ruby.l1_cntrl6.requestFromL1Cache.master system.ruby.l1_cntrl6.responseFromL1Cache.master system.ruby.l1_cntrl6.persistentFromL1Cache.master system.ruby.l1_cntrl7.requestFromL1Cache.master system.ruby.l1_cntrl7.responseFromL1Cache.master system.ruby.l1_cntrl7.persistentFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.requestFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.persistentFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master
-
-[system.ruby.network.ext_links0]
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-[system.ruby.network.ext_links1]
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-[system.ruby.network.ext_links2]
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-[system.ruby.network.ext_links3]
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-[system.ruby.network.ext_links4]
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-[system.ruby.network.ext_links5]
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-[system.ruby.network.ext_links6]
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-[system.ruby.network.ext_links7]
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-[system.ruby.network.ext_links8]
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-[system.ruby.network.ext_links9]
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-[system.ruby.network.int_link_buffers000]
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-[system.ruby.network.int_link_buffers001]
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers062]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers063]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers064]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers065]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers066]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers067]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers068]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers069]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers070]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers071]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers072]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers073]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers074]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers075]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers076]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers077]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers078]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers079]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers080]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers081]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers082]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers083]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers084]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers085]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers086]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers087]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers088]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers089]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers090]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers091]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers092]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers093]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers094]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers095]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers096]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers097]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers098]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers099]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers100]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers101]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers102]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers103]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers104]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers105]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers106]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers107]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers108]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers109]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers110]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers111]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers112]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers113]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers114]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers115]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers116]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers117]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers118]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers10.port_buffers119]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-system.cpu6: completed 10000 read, 5414 write accesses @600125
-system.cpu3: completed 10000 read, 5553 write accesses @601190
-system.cpu5: completed 10000 read, 5522 write accesses @610184
-system.cpu2: completed 10000 read, 5553 write accesses @610543
-system.cpu1: completed 10000 read, 5553 write accesses @610637
-system.cpu7: completed 10000 read, 5548 write accesses @613961
-system.cpu4: completed 10000 read, 5672 write accesses @625096
-system.cpu0: completed 10000 read, 5578 write accesses @625819
-system.cpu3: completed 20000 read, 11222 write accesses @1210787
-system.cpu2: completed 20000 read, 11113 write accesses @1216356
-system.cpu6: completed 20000 read, 11010 write accesses @1217399
-system.cpu7: completed 20000 read, 10915 write accesses @1224868
-system.cpu1: completed 20000 read, 11109 write accesses @1227113
-system.cpu5: completed 20000 read, 11172 write accesses @1228690
-system.cpu0: completed 20000 read, 11076 write accesses @1241151
-system.cpu4: completed 20000 read, 11317 write accesses @1252011
-system.cpu3: completed 30000 read, 16793 write accesses @1808510
-system.cpu2: completed 30000 read, 16719 write accesses @1811663
-system.cpu6: completed 30000 read, 16607 write accesses @1829544
-system.cpu1: completed 30000 read, 16700 write accesses @1832567
-system.cpu7: completed 30000 read, 16359 write accesses @1837933
-system.cpu5: completed 30000 read, 16722 write accesses @1842350
-system.cpu0: completed 30000 read, 16567 write accesses @1855038
-system.cpu4: completed 30000 read, 16806 write accesses @1868367
-system.cpu2: completed 40000 read, 22363 write accesses @2439233
-system.cpu3: completed 40000 read, 22637 write accesses @2443609
-system.cpu6: completed 40000 read, 22031 write accesses @2444868
-system.cpu1: completed 40000 read, 22136 write accesses @2454083
-system.cpu7: completed 40000 read, 22019 write accesses @2462426
-system.cpu0: completed 40000 read, 22102 write accesses @2464718
-system.cpu5: completed 40000 read, 22391 write accesses @2467086
-system.cpu4: completed 40000 read, 22274 write accesses @2476956
-system.cpu2: completed 50000 read, 27787 write accesses @3042124
-system.cpu6: completed 50000 read, 27603 write accesses @3052498
-system.cpu3: completed 50000 read, 28345 write accesses @3055004
-system.cpu1: completed 50000 read, 27635 write accesses @3062785
-system.cpu7: completed 50000 read, 27487 write accesses @3068425
-system.cpu0: completed 50000 read, 27611 write accesses @3068440
-system.cpu5: completed 50000 read, 27987 write accesses @3072420
-system.cpu4: completed 50000 read, 27913 write accesses @3101440
-system.cpu2: completed 60000 read, 33280 write accesses @3652049
-system.cpu3: completed 60000 read, 33864 write accesses @3668867
-system.cpu0: completed 60000 read, 33089 write accesses @3675395
-system.cpu7: completed 60000 read, 33087 write accesses @3676487
-system.cpu1: completed 60000 read, 33182 write accesses @3678705
-system.cpu6: completed 60000 read, 33377 write accesses @3680817
-system.cpu5: completed 60000 read, 33479 write accesses @3694370
-system.cpu4: completed 60000 read, 33302 write accesses @3701614
-system.cpu2: completed 70000 read, 38766 write accesses @4250473
-system.cpu0: completed 70000 read, 38578 write accesses @4284716
-system.cpu3: completed 70000 read, 39510 write accesses @4292337
-system.cpu1: completed 70000 read, 38741 write accesses @4292636
-system.cpu6: completed 70000 read, 39114 write accesses @4297860
-system.cpu7: completed 70000 read, 38662 write accesses @4300070
-system.cpu5: completed 70000 read, 38961 write accesses @4315101
-system.cpu4: completed 70000 read, 38876 write accesses @4320121
-system.cpu2: completed 80000 read, 44272 write accesses @4868351
-system.cpu3: completed 80000 read, 45140 write accesses @4896693
-system.cpu6: completed 80000 read, 44453 write accesses @4900088
-system.cpu0: completed 80000 read, 44159 write accesses @4900273
-system.cpu1: completed 80000 read, 44332 write accesses @4908589
-system.cpu7: completed 80000 read, 44332 write accesses @4918776
-system.cpu5: completed 80000 read, 44375 write accesses @4922197
-system.cpu4: completed 80000 read, 44529 write accesses @4935812
-system.cpu2: completed 90000 read, 49875 write accesses @5488123
-system.cpu3: completed 90000 read, 50614 write accesses @5502669
-system.cpu0: completed 90000 read, 49682 write accesses @5505213
-system.cpu6: completed 90000 read, 50248 write accesses @5520798
-system.cpu1: completed 90000 read, 49915 write accesses @5525318
-system.cpu7: completed 90000 read, 49900 write accesses @5530195
-system.cpu5: completed 90000 read, 50114 write accesses @5537728
-system.cpu4: completed 90000 read, 50125 write accesses @5550036
-system.cpu2: completed 100000 read, 55518 write accesses @6099346
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 14:12:23
-gem5 started Jan 21 2016 14:12:59
-gem5 executing on zizzer, pid 55396
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 6099346 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.006099 # Number of seconds simulated
-sim_ticks 6099346 # Number of ticks simulated
-final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 91228 # Simulator tick rate (ticks/s)
-host_mem_usage 473028 # Number of bytes of host memory used
-host_seconds 66.86 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39765376 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 19455168 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 19455168 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 621334 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 621334 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 303987 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 303987 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 6519613086 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 6519613086 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 3189713782 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 3189713782 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 9709326869 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 9709326869 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 621353 # Number of read requests accepted
-system.mem_ctrls.writeReqs 303987 # Number of write requests accepted
-system.mem_ctrls.readBursts 621353 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 303987 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 39135936 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 630016 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 19233536 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39766592 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 19455168 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 9844 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 3445 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 76431 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 76127 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 76543 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 76671 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 76481 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 76370 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 76529 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 76347 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 37966 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 37270 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 37672 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 37851 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 37319 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 37564 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 37461 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 37421 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 6099263 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 621353 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 303987 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 9205 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 12803 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 17020 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 20322 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 24896 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 30274 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 35013 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 37548 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 36271 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 32061 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 28288 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 26271 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 25434 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 24827 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 24316 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 23513 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 22261 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 21004 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 20162 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 19561 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 19244 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 18852 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 18407 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 17373 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 15506 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 12631 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 9097 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 5499 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 2677 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 929 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 214 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 30 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 32 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 89 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 308 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 808 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 1648 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 2932 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 4835 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 7227 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 10026 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 13120 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 16528 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 20274 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 17895 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 19060 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 20080 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 20633 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 21139 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 21648 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 12617 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 11019 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 9715 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 8816 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 7624 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 6699 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 5864 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 5356 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 4652 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 4249 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 3709 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 3432 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 3063 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 2763 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 2448 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 2048 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 1790 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 1460 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 1286 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 1101 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 924 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 776 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 451 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 197 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 92 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 50 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 17 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 3 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 253833 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 229.950243 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 184.650902 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 156.806564 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 46155 18.18% 18.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 104846 41.31% 59.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 56523 22.27% 81.76% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 26583 10.47% 92.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 12002 4.73% 96.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 4847 1.91% 98.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1822 0.72% 99.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 638 0.25% 99.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 417 0.16% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 253833 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 18189 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 33.618066 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 30.320455 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 11.847126 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7 973 5.35% 5.35% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15 91 0.50% 5.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23 51 0.28% 6.13% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31 5842 32.12% 38.25% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39 8693 47.79% 86.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47 1435 7.89% 93.93% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55 149 0.82% 94.75% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63 362 1.99% 96.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71 347 1.91% 98.65% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79 138 0.76% 99.41% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87 42 0.23% 99.64% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95 22 0.12% 99.76% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-103 20 0.11% 99.87% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::104-111 15 0.08% 99.95% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-119 8 0.04% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::152-159 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 18189 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 18189 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.522294 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.453355 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.687354 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 15819 86.97% 86.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 514 2.83% 89.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 386 2.12% 91.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 307 1.69% 93.61% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 291 1.60% 95.21% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 250 1.37% 96.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 208 1.14% 97.72% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 134 0.74% 98.46% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 105 0.58% 99.04% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 62 0.34% 99.38% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 47 0.26% 99.64% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 24 0.13% 99.77% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 18 0.10% 99.87% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 10 0.05% 99.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 5 0.03% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31 4 0.02% 99.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32 3 0.02% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::36 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 18189 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 65720985 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 77339466 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3057495 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 107.47 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 126.47 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 6416.42 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 3153.38 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 6519.81 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 3189.71 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 74.76 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 50.13 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 24.64 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 15.58 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 32.06 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 364001 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 294185 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 59.53 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 97.88 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 6.59 # Average gap between requests
-system.mem_ctrls.pageHitRate 72.17 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1918206360 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1065670200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7628499840 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 3114474624 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 398202480 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 4155129684 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 13188000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 18293371188 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 3000.521294 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 21 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 203580 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 5893144 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 398202480 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 131750712 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3542439600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 4072392792 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.968488 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5893118 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 203580 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99731 # number of read accesses completed
-system.cpu0.num_writes 55103 # number of write accesses completed
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 99468 # number of read accesses completed
-system.cpu1.num_writes 55228 # number of write accesses completed
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 100000 # number of read accesses completed
-system.cpu2.num_writes 55518 # number of write accesses completed
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 99696 # number of read accesses completed
-system.cpu3.num_writes 55953 # number of write accesses completed
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 98851 # number of read accesses completed
-system.cpu4.num_writes 55227 # number of write accesses completed
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 98859 # number of read accesses completed
-system.cpu5.num_writes 55313 # number of write accesses completed
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 99329 # number of read accesses completed
-system.cpu6.num_writes 55461 # number of write accesses completed
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 99244 # number of read accesses completed
-system.cpu7.num_writes 55110 # number of write accesses completed
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 626716
-system.ruby.outstanding_req_hist_seqr::mean 15.998460
-system.ruby.outstanding_req_hist_seqr::gmean 15.997196
-system.ruby.outstanding_req_hist_seqr::stdev 0.125834
-system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 626591 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 626716
-system.ruby.latency_hist_seqr::bucket_size 512
-system.ruby.latency_hist_seqr::max_bucket 5119
-system.ruby.latency_hist_seqr::samples 626588
-system.ruby.latency_hist_seqr::mean 1245.772554
-system.ruby.latency_hist_seqr::gmean 1012.769806
-system.ruby.latency_hist_seqr::stdev 668.694211
-system.ruby.latency_hist_seqr | 107920 17.22% 17.22% | 148908 23.76% 40.99% | 141299 22.55% 63.54% | 142667 22.77% 86.31% | 76272 12.17% 98.48% | 9413 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 626588
-system.ruby.hit_latency_hist_seqr::bucket_size 512
-system.ruby.hit_latency_hist_seqr::max_bucket 5119
-system.ruby.hit_latency_hist_seqr::samples 2961
-system.ruby.hit_latency_hist_seqr::mean 1105.733874
-system.ruby.hit_latency_hist_seqr::gmean 581.668757
-system.ruby.hit_latency_hist_seqr::stdev 707.726656
-system.ruby.hit_latency_hist_seqr | 739 24.96% 24.96% | 664 22.42% 47.38% | 645 21.78% 69.17% | 594 20.06% 89.23% | 287 9.69% 98.92% | 32 1.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 2961
-system.ruby.miss_latency_hist_seqr::bucket_size 512
-system.ruby.miss_latency_hist_seqr::max_bucket 5119
-system.ruby.miss_latency_hist_seqr::samples 623627
-system.ruby.miss_latency_hist_seqr::mean 1246.437462
-system.ruby.miss_latency_hist_seqr::gmean 1015.439930
-system.ruby.miss_latency_hist_seqr::stdev 668.434071
-system.ruby.miss_latency_hist_seqr | 107181 17.19% 17.19% | 148244 23.77% 40.96% | 140654 22.55% 63.51% | 142073 22.78% 86.29% | 75985 12.18% 98.48% | 9381 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 623627
-system.ruby.L1Cache.incomplete_times_seqr 2150
-system.ruby.Directory.incomplete_times_seqr 621474
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 20 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 78435 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78455 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 26 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 78293 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78319 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.fully_busy_cycles 8 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 21 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 78389 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78410 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.fully_busy_cycles 6 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 78553 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78573 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.fully_busy_cycles 6 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl4.L1Dcache.demand_hits 24 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses 78168 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78192 # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl5.L1Dcache.demand_hits 31 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses 78418 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78449 # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.fully_busy_cycles 8 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl6.L1Dcache.demand_hits 32 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses 78003 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78035 # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl7.L1Dcache.demand_hits 24 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses 78156 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78180 # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
-system.ruby.l2_cntrl0.L2cache.demand_hits 1651 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 624764 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 626415 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers00.percent_links_utilized 11.233413
-system.ruby.network.routers00.msg_count.Request_Control::1 78435
-system.ruby.network.routers00.msg_count.Response_Data::4 81785
-system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 210
-system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 180
-system.ruby.network.routers00.msg_count.Response_Control::4 122
-system.ruby.network.routers00.msg_count.Writeback_Data::4 107529
-system.ruby.network.routers00.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers00.msg_count.Persistent_Control::3 328351
-system.ruby.network.routers00.msg_bytes.Request_Control::1 627480
-system.ruby.network.routers00.msg_bytes.Response_Data::4 5888520
-system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 15120
-system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 12960
-system.ruby.network.routers00.msg_bytes.Response_Control::4 976
-system.ruby.network.routers00.msg_bytes.Writeback_Data::4 7742088
-system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2626808
-system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers01.percent_links_utilized 11.216772
-system.ruby.network.routers01.msg_count.Request_Control::1 78293
-system.ruby.network.routers01.msg_count.Response_Data::4 81463
-system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 217
-system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 171
-system.ruby.network.routers01.msg_count.Response_Control::4 101
-system.ruby.network.routers01.msg_count.Writeback_Data::4 107414
-system.ruby.network.routers01.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers01.msg_count.Persistent_Control::3 328405
-system.ruby.network.routers01.msg_bytes.Request_Control::1 626344
-system.ruby.network.routers01.msg_bytes.Response_Data::4 5865336
-system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 15624
-system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 12312
-system.ruby.network.routers01.msg_bytes.Response_Control::4 808
-system.ruby.network.routers01.msg_bytes.Writeback_Data::4 7733808
-system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2627240
-system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers02.percent_links_utilized 11.235213
-system.ruby.network.routers02.msg_count.Request_Control::1 78389
-system.ruby.network.routers02.msg_count.Response_Data::4 81630
-system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 212
-system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 166
-system.ruby.network.routers02.msg_count.Response_Control::4 134
-system.ruby.network.routers02.msg_count.Writeback_Data::4 107712
-system.ruby.network.routers02.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers02.msg_count.Persistent_Control::3 328681
-system.ruby.network.routers02.msg_bytes.Request_Control::1 627112
-system.ruby.network.routers02.msg_bytes.Response_Data::4 5877360
-system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 15264
-system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 11952
-system.ruby.network.routers02.msg_bytes.Response_Control::4 1072
-system.ruby.network.routers02.msg_bytes.Writeback_Data::4 7755264
-system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2629448
-system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers03.percent_links_utilized 11.269241
-system.ruby.network.routers03.msg_count.Request_Control::1 78553
-system.ruby.network.routers03.msg_count.Response_Data::4 82027
-system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 206
-system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 173
-system.ruby.network.routers03.msg_count.Response_Control::4 127
-system.ruby.network.routers03.msg_count.Writeback_Data::4 108198
-system.ruby.network.routers03.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers03.msg_count.Persistent_Control::3 328869
-system.ruby.network.routers03.msg_bytes.Request_Control::1 628424
-system.ruby.network.routers03.msg_bytes.Response_Data::4 5905944
-system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 14832
-system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 12456
-system.ruby.network.routers03.msg_bytes.Response_Control::4 1016
-system.ruby.network.routers03.msg_bytes.Writeback_Data::4 7790256
-system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2630952
-system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers04.percent_links_utilized 11.220096
-system.ruby.network.routers04.msg_count.Request_Control::1 78168
-system.ruby.network.routers04.msg_count.Response_Data::4 81565
-system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 202
-system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 179
-system.ruby.network.routers04.msg_count.Response_Control::4 149
-system.ruby.network.routers04.msg_count.Writeback_Data::4 107413
-system.ruby.network.routers04.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers04.msg_count.Persistent_Control::3 328447
-system.ruby.network.routers04.msg_bytes.Request_Control::1 625344
-system.ruby.network.routers04.msg_bytes.Response_Data::4 5872680
-system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 14544
-system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 12888
-system.ruby.network.routers04.msg_bytes.Response_Control::4 1192
-system.ruby.network.routers04.msg_bytes.Writeback_Data::4 7733736
-system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2627576
-system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers05.percent_links_utilized 11.228085
-system.ruby.network.routers05.msg_count.Request_Control::1 78418
-system.ruby.network.routers05.msg_count.Response_Data::4 81763
-system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 205
-system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 183
-system.ruby.network.routers05.msg_count.Response_Control::4 151
-system.ruby.network.routers05.msg_count.Writeback_Data::4 107403
-system.ruby.network.routers05.msg_count.Writeback_Control::4 2
-system.ruby.network.routers05.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers05.msg_count.Persistent_Control::3 328387
-system.ruby.network.routers05.msg_bytes.Request_Control::1 627344
-system.ruby.network.routers05.msg_bytes.Response_Data::4 5886936
-system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 14760
-system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 13176
-system.ruby.network.routers05.msg_bytes.Response_Control::4 1208
-system.ruby.network.routers05.msg_bytes.Writeback_Data::4 7733016
-system.ruby.network.routers05.msg_bytes.Writeback_Control::4 16
-system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2627096
-system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers06.percent_links_utilized 11.201853
-system.ruby.network.routers06.msg_count.Request_Control::1 78003
-system.ruby.network.routers06.msg_count.Response_Data::4 81441
-system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 248
-system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 180
-system.ruby.network.routers06.msg_count.Response_Control::4 133
-system.ruby.network.routers06.msg_count.Writeback_Data::4 107026
-system.ruby.network.routers06.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers06.msg_count.Persistent_Control::3 328353
-system.ruby.network.routers06.msg_bytes.Request_Control::1 624024
-system.ruby.network.routers06.msg_bytes.Response_Data::4 5863752
-system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 17856
-system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 12960
-system.ruby.network.routers06.msg_bytes.Response_Control::4 1064
-system.ruby.network.routers06.msg_bytes.Writeback_Data::4 7705872
-system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2626824
-system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers07.percent_links_utilized 11.201172
-system.ruby.network.routers07.msg_count.Request_Control::1 78156
-system.ruby.network.routers07.msg_count.Response_Data::4 81436
-system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 242
-system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 192
-system.ruby.network.routers07.msg_count.Response_Control::4 146
-system.ruby.network.routers07.msg_count.Writeback_Data::4 107013
-system.ruby.network.routers07.msg_count.Broadcast_Control::1 626415
-system.ruby.network.routers07.msg_count.Persistent_Control::3 328129
-system.ruby.network.routers07.msg_bytes.Request_Control::1 625248
-system.ruby.network.routers07.msg_bytes.Response_Data::4 5863392
-system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 17424
-system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 13824
-system.ruby.network.routers07.msg_bytes.Response_Control::4 1168
-system.ruby.network.routers07.msg_bytes.Writeback_Data::4 7704936
-system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5011320
-system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2625032
-system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers08.percent_links_utilized 42.049426
-system.ruby.network.routers08.msg_count.Request_Control::1 626415
-system.ruby.network.routers08.msg_count.Request_Control::2 624764
-system.ruby.network.routers08.msg_count.Response_Data::4 15075
-system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1651
-system.ruby.network.routers08.msg_count.Response_Control::4 1042
-system.ruby.network.routers08.msg_count.Writeback_Data::4 916236
-system.ruby.network.routers08.msg_count.Writeback_Control::4 318123
-system.ruby.network.routers08.msg_count.Persistent_Control::3 291958
-system.ruby.network.routers08.msg_bytes.Request_Control::1 5011320
-system.ruby.network.routers08.msg_bytes.Request_Control::2 4998112
-system.ruby.network.routers08.msg_bytes.Response_Data::4 1085400
-system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 118872
-system.ruby.network.routers08.msg_bytes.Response_Control::4 8336
-system.ruby.network.routers08.msg_bytes.Writeback_Data::4 65968992
-system.ruby.network.routers08.msg_bytes.Writeback_Control::4 2544984
-system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2335664
-system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers09.percent_links_utilized 39.472142
-system.ruby.network.routers09.msg_count.Request_Control::2 624764
-system.ruby.network.routers09.msg_count.Response_Data::4 635954
-system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 91
-system.ruby.network.routers09.msg_count.Response_Control::4 9
-system.ruby.network.routers09.msg_count.Writeback_Data::4 296768
-system.ruby.network.routers09.msg_count.Writeback_Control::4 318125
-system.ruby.network.routers09.msg_count.Persistent_Control::3 291958
-system.ruby.network.routers09.msg_bytes.Request_Control::2 4998112
-system.ruby.network.routers09.msg_bytes.Response_Data::4 45788688
-system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 6552
-system.ruby.network.routers09.msg_bytes.Response_Control::4 72
-system.ruby.network.routers09.msg_bytes.Writeback_Data::4 21367296
-system.ruby.network.routers09.msg_bytes.Writeback_Control::4 2545000
-system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2335664
-system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers10.percent_links_utilized 19.510945
-system.ruby.network.routers10.msg_count.Request_Control::1 626415
-system.ruby.network.routers10.msg_count.Request_Control::2 624764
-system.ruby.network.routers10.msg_count.Response_Data::4 652070
-system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1742
-system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 712
-system.ruby.network.routers10.msg_count.Response_Control::4 1057
-system.ruby.network.routers10.msg_count.Writeback_Data::4 1036356
-system.ruby.network.routers10.msg_count.Writeback_Control::4 318125
-system.ruby.network.routers10.msg_count.Broadcast_Control::1 4384905
-system.ruby.network.routers10.msg_count.Persistent_Control::3 2627622
-system.ruby.network.routers10.msg_bytes.Request_Control::1 5011320
-system.ruby.network.routers10.msg_bytes.Request_Control::2 4998112
-system.ruby.network.routers10.msg_bytes.Response_Data::4 46949040
-system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 125424
-system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 51264
-system.ruby.network.routers10.msg_bytes.Response_Control::4 8456
-system.ruby.network.routers10.msg_bytes.Writeback_Data::4 74617632
-system.ruby.network.routers10.msg_bytes.Writeback_Control::4 2545000
-system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35079240
-system.ruby.network.routers10.msg_bytes.Persistent_Control::3 21020976
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control 3753537
-system.ruby.network.msg_count.Response_Data 1956209
-system.ruby.network.msg_count.ResponseL2hit_Data 5226
-system.ruby.network.msg_count.ResponseLocal_Data 2136
-system.ruby.network.msg_count.Response_Control 3171
-system.ruby.network.msg_count.Writeback_Data 3109068
-system.ruby.network.msg_count.Writeback_Control 954375
-system.ruby.network.msg_count.Broadcast_Control 9396225
-system.ruby.network.msg_count.Persistent_Control 5839160
-system.ruby.network.msg_byte.Request_Control 30028296
-system.ruby.network.msg_byte.Response_Data 140847048
-system.ruby.network.msg_byte.ResponseL2hit_Data 376272
-system.ruby.network.msg_byte.ResponseLocal_Data 153792
-system.ruby.network.msg_byte.Response_Control 25368
-system.ruby.network.msg_byte.Writeback_Data 223852896
-system.ruby.network.msg_byte.Writeback_Control 7635000
-system.ruby.network.msg_byte.Broadcast_Control 75169800
-system.ruby.network.msg_byte.Persistent_Control 46713280
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers00.throttle0.link_utilization 13.880578
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-system.ruby.ST.miss_latency_hist_seqr | 38270 17.22% 17.22% | 52638 23.68% 40.90% | 50107 22.54% 63.44% | 50539 22.74% 86.17% | 27418 12.33% 98.51% | 3278 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Directory.miss_mach_latency_hist_seqr | 106791 17.18% 17.18% | 147794 23.78% 40.96% | 140129 22.55% 63.51% | 141588 22.78% 86.29% | 75730 12.19% 98.48% | 9336 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 621477
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 3
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 3
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 3
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 88
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 87.863425
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev 6
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 3
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 132
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 132 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 132
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 1339
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 1280.535474
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1006.733527
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::stdev 680.945391
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 229 17.10% 17.10% | 276 20.61% 37.71% | 333 24.87% 62.58% | 304 22.70% 85.29% | 164 12.25% 97.54% | 33 2.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 1339
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 1760
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 1173.405114
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 910.831654
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 657.956416
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 347 19.72% 19.72% | 427 24.26% 43.98% | 425 24.15% 68.12% | 371 21.08% 89.20% | 172 9.77% 98.98% | 18 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 1760
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 399993
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1245.478163
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 1014.921384
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 667.876777
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 68682 17.17% 17.17% | 95330 23.83% 41.00% | 90214 22.55% 63.56% | 91230 22.81% 86.37% | 48403 12.10% 98.47% | 6070 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 399993
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 66
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 66 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 66
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 811
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1208.461159
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 942.129361
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 665.132497
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 161 19.85% 19.85% | 174 21.45% 41.31% | 192 23.67% 64.98% | 181 22.32% 87.30% | 91 11.22% 98.52% | 12 1.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 811
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 1003
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 1205.071785
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 930.438584
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 678.666440
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 194 19.34% 19.34% | 237 23.63% 42.97% | 220 21.93% 64.91% | 223 22.23% 87.14% | 115 11.47% 98.60% | 14 1.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 1003
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 221484
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1248.102838
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 1016.708923
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 669.367212
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 38109 17.21% 17.21% | 52464 23.69% 40.89% | 49915 22.54% 63.43% | 50358 22.74% 86.17% | 27327 12.34% 98.51% | 3266 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 221484
-system.ruby.Directory_Controller.GETX 240452 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 432599 0.00% 0.00%
-system.ruby.Directory_Controller.Lockdown 146609 0.00% 0.00%
-system.ruby.Directory_Controller.Unlockdown 145349 0.00% 0.00%
-system.ruby.Directory_Controller.Data_Owner 469 0.00% 0.00%
-system.ruby.Directory_Controller.Data_All_Tokens 307348 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_Owner 430 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens 316863 0.00% 0.00%
-system.ruby.Directory_Controller.Tokens 180 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens 746 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 621329 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 303987 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 220258 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETS 397725 0.00% 0.00%
-system.ruby.Directory_Controller.O.Lockdown 2797 0.00% 0.00%
-system.ruby.Directory_Controller.O.Data_All_Tokens 150 0.00% 0.00%
-system.ruby.Directory_Controller.O.Tokens 17 0.00% 0.00%
-system.ruby.Directory_Controller.O.Ack_All_Tokens 732 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETX 1901 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETS 3320 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Lockdown 44050 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_Owner 467 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens 303520 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner 430 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 316439 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Tokens 157 0.00% 0.00%
-system.ruby.Directory_Controller.L.GETX 558 0.00% 0.00%
-system.ruby.Directory_Controller.L.GETS 1002 0.00% 0.00%
-system.ruby.Directory_Controller.L.Lockdown 1116 0.00% 0.00%
-system.ruby.Directory_Controller.L.Unlockdown 145316 0.00% 0.00%
-system.ruby.Directory_Controller.L.Data_Owner 2 0.00% 0.00%
-system.ruby.Directory_Controller.L.Data_All_Tokens 3652 0.00% 0.00%
-system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 424 0.00% 0.00%
-system.ruby.Directory_Controller.L.Tokens 3 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.GETX 61 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.GETS 128 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Lockdown 149 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Data_All_Tokens 26 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Tokens 3 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Ack_All_Tokens 1 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Memory_Data 33 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack 303838 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.GETX 543 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.GETS 896 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.Lockdown 7 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.Unlockdown 33 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Data 3337 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Ack 149 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.GETX 1538 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.GETS 2627 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Lockdown 129 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data 98356 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.GETX 15593 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.GETS 26901 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown 98361 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 13 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 519603 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50667 12.57% 12.57% | 50484 12.52% 25.08% | 50375 12.49% 37.58% | 50486 12.52% 50.10% | 50381 12.49% 62.59% | 50187 12.45% 75.04% | 50077 12.42% 87.46% | 50582 12.54% 100.00%
-system.ruby.L1Cache_Controller.Load::total 403239
-system.ruby.L1Cache_Controller.Store | 27788 12.44% 12.44% | 27835 12.46% 24.90% | 28035 12.55% 37.45% | 28087 12.57% 50.03% | 27811 12.45% 62.48% | 28262 12.65% 75.13% | 27958 12.52% 87.64% | 27598 12.36% 100.00%
-system.ruby.L1Cache_Controller.Store::total 223374
-system.ruby.L1Cache_Controller.L1_Replacement | 1482309 12.54% 12.54% | 1478152 12.50% 25.04% | 1477165 12.50% 37.54% | 1480092 12.52% 50.06% | 1475170 12.48% 62.54% | 1480320 12.52% 75.06% | 1470800 12.44% 87.50% | 1477330 12.50% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 11821338
-system.ruby.L1Cache_Controller.Data_Shared | 182 12.24% 12.24% | 184 12.37% 24.61% | 174 11.70% 36.31% | 192 12.91% 49.23% | 172 11.57% 60.79% | 175 11.77% 72.56% | 199 13.38% 85.94% | 209 14.06% 100.00%
-system.ruby.L1Cache_Controller.Data_Shared::total 1487
-system.ruby.L1Cache_Controller.Data_Owner | 102 14.35% 14.35% | 88 12.38% 26.72% | 96 13.50% 40.23% | 87 12.24% 52.46% | 88 12.38% 64.84% | 87 12.24% 77.07% | 68 9.56% 86.64% | 95 13.36% 100.00%
-system.ruby.L1Cache_Controller.Data_Owner::total 711
-system.ruby.L1Cache_Controller.Data_All_Tokens | 94528 12.51% 12.51% | 94324 12.49% 25.00% | 94557 12.52% 37.51% | 94990 12.57% 50.09% | 94377 12.49% 62.58% | 94479 12.51% 75.09% | 94128 12.46% 87.55% | 94089 12.45% 100.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens::total 755472
-system.ruby.L1Cache_Controller.Ack | 3 21.43% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 2 14.29% 57.14% | 0 0.00% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 14
-system.ruby.L1Cache_Controller.Transient_Local_GETX | 195530 12.51% 12.51% | 195478 12.51% 25.01% | 195278 12.49% 37.51% | 195229 12.49% 50.00% | 195505 12.51% 62.50% | 195060 12.48% 74.98% | 195357 12.50% 87.48% | 195719 12.52% 100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1563156
-system.ruby.L1Cache_Controller.Transient_Local_GETS | 352449 12.49% 12.49% | 352643 12.50% 24.99% | 352748 12.50% 37.49% | 352633 12.50% 49.99% | 352741 12.50% 62.49% | 352937 12.51% 74.99% | 353055 12.51% 87.51% | 352539 12.49% 100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2821745
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 4
-system.ruby.L1Cache_Controller.Persistent_GETX | 45490 12.51% 12.51% | 45476 12.51% 25.02% | 45348 12.47% 37.50% | 45359 12.48% 49.97% | 45403 12.49% 62.46% | 45382 12.48% 74.94% | 45473 12.51% 87.45% | 45618 12.55% 100.00%
-system.ruby.L1Cache_Controller.Persistent_GETX::total 363549
-system.ruby.L1Cache_Controller.Persistent_GETS | 82793 12.49% 12.49% | 82775 12.49% 24.98% | 82793 12.49% 37.48% | 82699 12.48% 49.96% | 82884 12.51% 62.46% | 82958 12.52% 74.98% | 82904 12.51% 87.49% | 82886 12.51% 100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS::total 662692
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 2
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 163675 12.50% 12.50% | 163707 12.50% 25.00% | 163816 12.51% 37.51% | 163900 12.52% 50.03% | 163671 12.50% 62.53% | 163618 12.50% 75.02% | 163580 12.49% 87.52% | 163454 12.48% 100.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 1309421
-system.ruby.L1Cache_Controller.Request_Timeout | 113982 12.40% 12.40% | 114218 12.43% 24.83% | 115677 12.58% 37.41% | 116297 12.65% 50.06% | 115021 12.51% 62.58% | 115438 12.56% 75.13% | 114863 12.50% 87.63% | 113699 12.37% 100.00%
-system.ruby.L1Cache_Controller.Request_Timeout::total 919195
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 10 4.93% 4.93% | 17 8.37% 13.30% | 26 12.81% 26.11% | 26 12.81% 38.92% | 26 12.81% 51.72% | 30 14.78% 66.50% | 34 16.75% 83.25% | 34 16.75% 100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 203
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 26 8.12% 8.12% | 19 5.94% 14.06% | 35 10.94% 25.00% | 33 10.31% 35.31% | 51 15.94% 51.25% | 51 15.94% 67.19% | 51 15.94% 83.12% | 54 16.88% 100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 320
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78180 12.53% 12.53% | 78041 12.50% 25.03% | 78121 12.52% 37.54% | 78269 12.54% 50.08% | 77894 12.48% 62.56% | 78131 12.52% 75.08% | 77705 12.45% 87.53% | 77837 12.47% 100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 624178
-system.ruby.L1Cache_Controller.NP.Load | 50581 12.57% 12.57% | 50392 12.52% 25.09% | 50283 12.49% 37.58% | 50410 12.53% 50.11% | 50271 12.49% 62.60% | 50089 12.45% 75.04% | 49958 12.41% 87.46% | 50481 12.54% 100.00%
-system.ruby.L1Cache_Controller.NP.Load::total 402465
-system.ruby.L1Cache_Controller.NP.Store | 27727 12.44% 12.44% | 27793 12.47% 24.90% | 27984 12.55% 37.45% | 28032 12.57% 50.02% | 27756 12.45% 62.47% | 28215 12.65% 75.13% | 27910 12.52% 87.64% | 27550 12.36% 100.00%
-system.ruby.L1Cache_Controller.NP.Store::total 222967
-system.ruby.L1Cache_Controller.NP.Data_Shared | 31 14.03% 14.03% | 28 12.67% 26.70% | 28 12.67% 39.37% | 23 10.41% 49.77% | 29 13.12% 62.90% | 25 11.31% 74.21% | 26 11.76% 85.97% | 31 14.03% 100.00%
-system.ruby.L1Cache_Controller.NP.Data_Shared::total 221
-system.ruby.L1Cache_Controller.NP.Data_Owner | 37 13.41% 13.41% | 30 10.87% 24.28% | 36 13.04% 37.32% | 33 11.96% 49.28% | 35 12.68% 61.96% | 31 11.23% 73.19% | 30 10.87% 84.06% | 44 15.94% 100.00%
-system.ruby.L1Cache_Controller.NP.Data_Owner::total 276
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 16213 12.44% 12.44% | 16160 12.40% 24.84% | 16306 12.51% 37.36% | 16601 12.74% 50.09% | 16361 12.56% 62.65% | 16214 12.44% 75.09% | 16316 12.52% 87.61% | 16143 12.39% 100.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 130314
-system.ruby.L1Cache_Controller.NP.Ack | 2 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 1 12.50% 62.50% | 0 0.00% 62.50% | 3 37.50% 100.00%
-system.ruby.L1Cache_Controller.NP.Ack::total 8
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194864 12.51% 12.51% | 194884 12.51% 25.01% | 194599 12.49% 37.50% | 194606 12.49% 49.99% | 194888 12.51% 62.50% | 194419 12.48% 74.98% | 194754 12.50% 87.48% | 195093 12.52% 100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1558107
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 351252 12.49% 12.49% | 351488 12.50% 24.99% | 351609 12.50% 37.49% | 351524 12.50% 49.99% | 351577 12.50% 62.49% | 351765 12.51% 75.00% | 351871 12.51% 87.51% | 351335 12.49% 100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2812421
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 142654 12.51% 12.51% | 142579 12.50% 25.00% | 142548 12.50% 37.50% | 142694 12.51% 50.01% | 142513 12.49% 62.50% | 142552 12.50% 75.00% | 142576 12.50% 87.50% | 142609 12.50% 100.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 1140725
-system.ruby.L1Cache_Controller.I.L1_Replacement | 115 11.11% 11.11% | 99 9.57% 20.68% | 132 12.75% 33.43% | 120 11.59% 45.02% | 149 14.40% 59.42% | 150 14.49% 73.91% | 130 12.56% 86.47% | 140 13.53% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 1035
-system.ruby.L1Cache_Controller.I.Data_All_Tokens | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 1
-system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
-system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 4
-system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock::total 3
-system.ruby.L1Cache_Controller.S.L1_Replacement | 199 11.94% 11.94% | 196 11.76% 23.70% | 190 11.40% 35.09% | 210 12.60% 47.69% | 197 11.82% 59.51% | 200 12.00% 71.51% | 237 14.22% 85.72% | 238 14.28% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 1667
-system.ruby.L1Cache_Controller.S.Data_Shared | 0 0.00% 0.00% | 1 8.33% 8.33% | 2 16.67% 25.00% | 1 8.33% 33.33% | 2 16.67% 50.00% | 3 25.00% 75.00% | 2 16.67% 91.67% | 1 8.33% 100.00%
-system.ruby.L1Cache_Controller.S.Data_Shared::total 12
-system.ruby.L1Cache_Controller.S.Data_Owner | 1 25.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Data_Owner::total 4
-system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 10.00% 10.00% | 3 30.00% 40.00% | 1 10.00% 50.00% | 2 20.00% 70.00% | 0 0.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00%
-system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 10
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 1
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 4
-system.ruby.L1Cache_Controller.S.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETX::total 1
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 2
-system.ruby.L1Cache_Controller.O.L1_Replacement | 96 14.29% 14.29% | 87 12.95% 27.23% | 81 12.05% 39.29% | 78 11.61% 50.89% | 85 12.65% 63.54% | 77 11.46% 75.00% | 78 11.61% 86.61% | 90 13.39% 100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total 672
-system.ruby.L1Cache_Controller.O.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Data_Shared::total 1
-system.ruby.L1Cache_Controller.O.Data_All_Tokens | 3 37.50% 37.50% | 2 25.00% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00%
-system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 8
-system.ruby.L1Cache_Controller.O.Ack | 1 25.00% 25.00% | 1 25.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Ack::total 4
-system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 5
-system.ruby.L1Cache_Controller.O.Persistent_GETX | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Persistent_GETX::total 1
-system.ruby.L1Cache_Controller.O.Persistent_GETS | 1 14.29% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Persistent_GETS::total 7
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 29 17.90% 17.90% | 21 12.96% 30.86% | 23 14.20% 45.06% | 16 9.88% 54.94% | 16 9.88% 64.81% | 31 19.14% 83.95% | 9 5.56% 89.51% | 17 10.49% 100.00%
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 162
-system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 2 6.45% 6.45% | 7 22.58% 29.03% | 1 3.23% 32.26% | 4 12.90% 45.16% | 4 12.90% 58.06% | 5 16.13% 74.19% | 8 25.81% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 31
-system.ruby.L1Cache_Controller.M.Store | 2 14.29% 14.29% | 1 7.14% 21.43% | 1 7.14% 28.57% | 3 21.43% 50.00% | 1 7.14% 57.14% | 4 28.57% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 14
-system.ruby.L1Cache_Controller.M.L1_Replacement | 50307 12.57% 12.57% | 50130 12.52% 25.09% | 50031 12.50% 37.59% | 50119 12.52% 50.11% | 50010 12.49% 62.60% | 49833 12.45% 75.05% | 49674 12.41% 87.46% | 50184 12.54% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 400288
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 25 14.29% 14.29% | 18 10.29% 24.57% | 22 12.57% 37.14% | 21 12.00% 49.14% | 26 14.86% 64.00% | 17 9.71% 73.71% | 24 13.71% 87.43% | 22 12.57% 100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 175
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 35 13.83% 13.83% | 33 13.04% 26.88% | 23 9.09% 35.97% | 26 10.28% 46.25% | 33 13.04% 59.29% | 23 9.09% 68.38% | 40 15.81% 84.19% | 40 15.81% 100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 253
-system.ruby.L1Cache_Controller.M.Persistent_GETX | 14 12.61% 12.61% | 11 9.91% 22.52% | 13 11.71% 34.23% | 16 14.41% 48.65% | 22 19.82% 68.47% | 13 11.71% 80.18% | 15 13.51% 93.69% | 7 6.31% 100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETX::total 111
-system.ruby.L1Cache_Controller.M.Persistent_GETS | 36 16.36% 16.36% | 32 14.55% 30.91% | 20 9.09% 40.00% | 24 10.91% 50.91% | 27 12.27% 63.18% | 26 11.82% 75.00% | 31 14.09% 89.09% | 24 10.91% 100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETS::total 220
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 1544 12.49% 12.49% | 1604 12.98% 25.48% | 1578 12.77% 38.25% | 1508 12.20% 50.45% | 1549 12.54% 62.98% | 1497 12.11% 75.10% | 1552 12.56% 87.66% | 1525 12.34% 100.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 12357
-system.ruby.L1Cache_Controller.MM.Load | 1 6.25% 6.25% | 2 12.50% 18.75% | 2 12.50% 31.25% | 2 12.50% 43.75% | 3 18.75% 62.50% | 3 18.75% 81.25% | 2 12.50% 93.75% | 1 6.25% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 16
-system.ruby.L1Cache_Controller.MM.Store | 1 11.11% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 4 44.44% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 9
-system.ruby.L1Cache_Controller.MM.L1_Replacement | 27714 12.44% 12.44% | 27777 12.47% 24.92% | 27951 12.55% 37.46% | 28022 12.58% 50.05% | 27723 12.45% 62.49% | 28154 12.64% 75.14% | 27879 12.52% 87.65% | 27500 12.35% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222720
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 18 16.98% 16.98% | 12 11.32% 28.30% | 14 13.21% 41.51% | 14 13.21% 54.72% | 8 7.55% 62.26% | 17 16.04% 78.30% | 9 8.49% 86.79% | 14 13.21% 100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 106
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 14 8.09% 8.09% | 20 11.56% 19.65% | 27 15.61% 35.26% | 14 8.09% 43.35% | 24 13.87% 57.23% | 29 16.76% 73.99% | 19 10.98% 84.97% | 26 15.03% 100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 173
-system.ruby.L1Cache_Controller.MM.Persistent_GETX | 8 14.55% 14.55% | 5 9.09% 23.64% | 6 10.91% 34.55% | 6 10.91% 45.45% | 8 14.55% 60.00% | 5 9.09% 69.09% | 7 12.73% 81.82% | 10 18.18% 100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 55
-system.ruby.L1Cache_Controller.MM.Persistent_GETS | 14 14.89% 14.89% | 8 8.51% 23.40% | 15 15.96% 39.36% | 10 10.64% 50.00% | 13 13.83% 63.83% | 15 15.96% 79.79% | 7 7.45% 87.23% | 12 12.77% 100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 94
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 814 11.97% 11.97% | 872 12.82% 24.78% | 871 12.80% 37.59% | 802 11.79% 49.38% | 885 13.01% 62.38% | 911 13.39% 75.78% | 828 12.17% 87.95% | 820 12.05% 100.00%
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 6803
-system.ruby.L1Cache_Controller.M_W.Load | 5 9.09% 9.09% | 12 21.82% 30.91% | 4 7.27% 38.18% | 5 9.09% 47.27% | 8 14.55% 61.82% | 6 10.91% 72.73% | 11 20.00% 92.73% | 4 7.27% 100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total 55
-system.ruby.L1Cache_Controller.M_W.Store | 5 16.67% 16.67% | 3 10.00% 26.67% | 2 6.67% 33.33% | 2 6.67% 40.00% | 5 16.67% 56.67% | 4 13.33% 70.00% | 3 10.00% 80.00% | 6 20.00% 100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total 30
-system.ruby.L1Cache_Controller.M_W.L1_Replacement | 368001 12.55% 12.55% | 367387 12.53% 25.08% | 364960 12.45% 37.53% | 365705 12.47% 50.01% | 366083 12.49% 62.50% | 366138 12.49% 74.99% | 365181 12.46% 87.44% | 368148 12.56% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2931603
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 49 11.01% 11.01% | 37 8.31% 19.33% | 60 13.48% 32.81% | 64 14.38% 47.19% | 69 15.51% 62.70% | 53 11.91% 74.61% | 54 12.13% 86.74% | 59 13.26% 100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 445
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 119 13.46% 13.46% | 114 12.90% 26.36% | 91 10.29% 36.65% | 100 11.31% 47.96% | 111 12.56% 60.52% | 129 14.59% 75.11% | 105 11.88% 86.99% | 115 13.01% 100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 884
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 7 6.09% 6.09% | 13 11.30% 17.39% | 15 13.04% 30.43% | 18 15.65% 46.09% | 16 13.91% 60.00% | 19 16.52% 76.52% | 10 8.70% 85.22% | 17 14.78% 100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 115
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 14 7.41% 7.41% | 11 5.82% 13.23% | 26 13.76% 26.98% | 20 10.58% 37.57% | 25 13.23% 50.79% | 26 13.76% 64.55% | 33 17.46% 82.01% | 34 17.99% 100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 189
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 1068 12.52% 12.52% | 1087 12.75% 25.27% | 1113 13.05% 38.32% | 1079 12.65% 50.97% | 1065 12.49% 63.46% | 1029 12.07% 75.53% | 1063 12.46% 87.99% | 1024 12.01% 100.00%
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 8528
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 7 5.56% 5.56% | 13 10.32% 15.87% | 17 13.49% 29.37% | 19 15.08% 44.44% | 16 12.70% 57.14% | 20 15.87% 73.02% | 15 11.90% 84.92% | 19 15.08% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 126
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 14 6.76% 6.76% | 13 6.28% 13.04% | 26 12.56% 25.60% | 23 11.11% 36.71% | 29 14.01% 50.72% | 27 13.04% 63.77% | 36 17.39% 81.16% | 39 18.84% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 207
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50414 12.57% 12.57% | 50220 12.52% 25.09% | 50109 12.49% 37.59% | 50206 12.52% 50.11% | 50119 12.50% 62.60% | 49914 12.45% 75.05% | 49786 12.41% 87.46% | 50275 12.54% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 401043
-system.ruby.L1Cache_Controller.MM_W.Load | 4 13.33% 13.33% | 5 16.67% 30.00% | 3 10.00% 40.00% | 4 13.33% 53.33% | 1 3.33% 56.67% | 4 13.33% 70.00% | 7 23.33% 93.33% | 2 6.67% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 30
-system.ruby.L1Cache_Controller.MM_W.Store | 2 15.38% 15.38% | 1 7.69% 23.08% | 1 7.69% 30.77% | 1 7.69% 38.46% | 2 15.38% 53.85% | 2 15.38% 69.23% | 1 7.69% 76.92% | 3 23.08% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total 13
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 203874 12.47% 12.47% | 204301 12.50% 24.97% | 203682 12.46% 37.43% | 204611 12.52% 49.95% | 202828 12.41% 62.35% | 206627 12.64% 74.99% | 204717 12.52% 87.52% | 204080 12.48% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1634720
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 40 13.56% 13.56% | 39 13.22% 26.78% | 34 11.53% 38.31% | 40 13.56% 51.86% | 38 12.88% 64.75% | 49 16.61% 81.36% | 33 11.19% 92.54% | 22 7.46% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 295
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 63 13.04% 13.04% | 54 11.18% 24.22% | 66 13.66% 37.89% | 58 12.01% 49.90% | 56 11.59% 61.49% | 54 11.18% 72.67% | 59 12.22% 84.89% | 73 15.11% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 483
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 3 4.17% 4.17% | 4 5.56% 9.72% | 9 12.50% 22.22% | 7 9.72% 31.94% | 10 13.89% 45.83% | 9 12.50% 58.33% | 17 23.61% 81.94% | 13 18.06% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 72
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 9 8.26% 8.26% | 6 5.50% 13.76% | 9 8.26% 22.02% | 10 9.17% 31.19% | 22 20.18% 51.38% | 23 21.10% 72.48% | 15 13.76% 86.24% | 15 13.76% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 109
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 604 12.79% 12.79% | 622 13.18% 25.97% | 622 13.18% 39.14% | 599 12.69% 51.83% | 595 12.60% 64.44% | 603 12.77% 77.21% | 525 11.12% 88.33% | 551 11.67% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 4721
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 3 3.90% 3.90% | 4 5.19% 9.09% | 9 11.69% 20.78% | 7 9.09% 29.87% | 10 12.99% 42.86% | 10 12.99% 55.84% | 19 24.68% 80.52% | 15 19.48% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 77
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 12 10.62% 10.62% | 6 5.31% 15.93% | 9 7.96% 23.89% | 10 8.85% 32.74% | 22 19.47% 52.21% | 24 21.24% 73.45% | 15 13.27% 86.73% | 15 13.27% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 113
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 27766 12.44% 12.44% | 27821 12.47% 24.91% | 28012 12.55% 37.47% | 28063 12.58% 50.04% | 27775 12.45% 62.49% | 28217 12.65% 75.14% | 27919 12.51% 87.65% | 27562 12.35% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223135
-system.ruby.L1Cache_Controller.IM.L1_Replacement | 293829 12.43% 12.43% | 294288 12.45% 24.89% | 297278 12.58% 37.47% | 297532 12.59% 50.06% | 292259 12.37% 62.42% | 298219 12.62% 75.04% | 295523 12.51% 87.55% | 294226 12.45% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2363154
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 27773 12.44% 12.44% | 27827 12.46% 24.90% | 28028 12.55% 37.45% | 28078 12.58% 50.03% | 27803 12.45% 62.48% | 28244 12.65% 75.13% | 27946 12.52% 87.65% | 27585 12.35% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223284
-system.ruby.L1Cache_Controller.IM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 2
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 89 12.34% 12.34% | 84 11.65% 23.99% | 108 14.98% 38.97% | 75 10.40% 49.38% | 73 10.12% 59.50% | 92 12.76% 72.26% | 104 14.42% 86.69% | 96 13.31% 100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 721
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 180 13.16% 13.16% | 148 10.82% 23.98% | 194 14.18% 38.16% | 147 10.75% 48.90% | 178 13.01% 61.92% | 183 13.38% 75.29% | 165 12.06% 87.35% | 173 12.65% 100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1368
-system.ruby.L1Cache_Controller.IM.Persistent_GETX | 15 7.58% 7.58% | 23 11.62% 19.19% | 28 14.14% 33.33% | 23 11.62% 44.95% | 23 11.62% 56.57% | 26 13.13% 69.70% | 33 16.67% 86.36% | 27 13.64% 100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 198
-system.ruby.L1Cache_Controller.IM.Persistent_GETS | 42 12.10% 12.10% | 31 8.93% 21.04% | 40 11.53% 32.56% | 47 13.54% 46.11% | 42 12.10% 58.21% | 45 12.97% 71.18% | 55 15.85% 87.03% | 45 12.97% 100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 347
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 5813 12.38% 12.38% | 5806 12.36% 24.74% | 5927 12.62% 37.37% | 5944 12.66% 50.02% | 5905 12.58% 62.60% | 5925 12.62% 75.22% | 5900 12.56% 87.78% | 5737 12.22% 100.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 46957
-system.ruby.L1Cache_Controller.IM.Request_Timeout | 40928 12.51% 12.51% | 40339 12.33% 24.84% | 40691 12.44% 37.28% | 41426 12.66% 49.94% | 40569 12.40% 62.34% | 42216 12.90% 75.24% | 40851 12.49% 87.73% | 40139 12.27% 100.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout::total 327159
-system.ruby.L1Cache_Controller.IS.L1_Replacement | 535929 12.62% 12.62% | 531889 12.53% 25.15% | 530564 12.50% 37.64% | 531367 12.51% 50.16% | 533202 12.56% 62.72% | 528282 12.44% 75.16% | 524494 12.35% 87.51% | 530355 12.49% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4246082
-system.ruby.L1Cache_Controller.IS.Data_Shared | 151 12.09% 12.09% | 154 12.33% 24.42% | 144 11.53% 35.95% | 165 13.21% 49.16% | 141 11.29% 60.45% | 147 11.77% 72.22% | 170 13.61% 85.83% | 177 14.17% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared::total 1249
-system.ruby.L1Cache_Controller.IS.Data_Owner | 64 14.85% 14.85% | 57 13.23% 28.07% | 59 13.69% 41.76% | 54 12.53% 54.29% | 52 12.06% 66.36% | 56 12.99% 79.35% | 38 8.82% 88.17% | 51 11.83% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Owner::total 431
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50440 12.57% 12.57% | 50246 12.52% 25.09% | 50151 12.49% 37.58% | 50247 12.52% 50.10% | 50165 12.50% 62.60% | 49962 12.45% 75.05% | 49832 12.42% 87.46% | 50330 12.54% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 401373
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 201 14.57% 14.57% | 147 10.65% 25.22% | 201 14.57% 39.78% | 171 12.39% 52.17% | 172 12.46% 64.64% | 184 13.33% 77.97% | 144 10.43% 88.41% | 160 11.59% 100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1380
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 334 13.51% 13.51% | 299 12.09% 25.60% | 274 11.08% 36.68% | 294 11.89% 48.56% | 317 12.82% 61.38% | 292 11.81% 73.19% | 336 13.59% 86.78% | 327 13.22% 100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2473
-system.ruby.L1Cache_Controller.IS.Persistent_GETX | 46 11.86% 11.86% | 49 12.63% 24.48% | 53 13.66% 38.14% | 48 12.37% 50.52% | 51 13.14% 63.66% | 47 12.11% 75.77% | 41 10.57% 86.34% | 53 13.66% 100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 388
-system.ruby.L1Cache_Controller.IS.Persistent_GETS | 68 10.09% 10.09% | 78 11.57% 21.66% | 70 10.39% 32.05% | 99 14.69% 46.74% | 89 13.20% 59.94% | 91 13.50% 73.44% | 94 13.95% 87.39% | 85 12.61% 100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 674
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 10744 12.55% 12.55% | 10736 12.54% 25.09% | 10707 12.51% 37.60% | 10817 12.64% 50.23% | 10654 12.44% 62.68% | 10612 12.40% 75.07% | 10635 12.42% 87.49% | 10706 12.51% 100.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 85611
-system.ruby.L1Cache_Controller.IS.Request_Timeout | 72575 12.35% 12.35% | 73377 12.49% 24.85% | 74350 12.66% 37.50% | 74310 12.65% 50.15% | 73874 12.58% 62.73% | 72578 12.36% 75.08% | 73347 12.49% 87.57% | 73021 12.43% 100.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout::total 587432
-system.ruby.L1Cache_Controller.I_L.Load | 76 11.84% 11.84% | 71 11.06% 22.90% | 76 11.84% 34.74% | 64 9.97% 44.70% | 94 14.64% 59.35% | 81 12.62% 71.96% | 94 14.64% 86.60% | 86 13.40% 100.00%
-system.ruby.L1Cache_Controller.I_L.Load::total 642
-system.ruby.L1Cache_Controller.I_L.Store | 51 14.96% 14.96% | 37 10.85% 25.81% | 46 13.49% 39.30% | 47 13.78% 53.08% | 47 13.78% 66.86% | 33 9.68% 76.54% | 41 12.02% 88.56% | 39 11.44% 100.00%
-system.ruby.L1Cache_Controller.I_L.Store::total 341
-system.ruby.L1Cache_Controller.I_L.L1_Replacement | 393 10.96% 10.96% | 357 9.95% 20.91% | 349 9.73% 30.64% | 428 11.93% 42.57% | 589 16.42% 58.99% | 509 14.19% 73.18% | 506 14.11% 87.29% | 456 12.71% 100.00%
-system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 3587
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 94 21.71% 21.71% | 82 18.94% 40.65% | 67 15.47% 56.12% | 57 13.16% 69.28% | 43 9.93% 79.21% | 51 11.78% 90.99% | 22 5.08% 96.07% | 17 3.93% 100.00%
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 433
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 243 12.64% 12.64% | 257 13.36% 26.00% | 240 12.48% 38.48% | 235 12.22% 50.70% | 231 12.01% 62.71% | 229 11.91% 74.62% | 235 12.22% 86.84% | 253 13.16% 100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 1923
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 450 12.27% 12.27% | 482 13.14% 25.41% | 464 12.65% 38.06% | 463 12.62% 50.68% | 444 12.10% 62.79% | 459 12.51% 75.30% | 459 12.51% 87.81% | 447 12.19% 100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 3668
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 45396 12.52% 12.52% | 45363 12.51% 25.04% | 45210 12.47% 37.51% | 45228 12.48% 49.99% | 45261 12.49% 62.48% | 45241 12.48% 74.96% | 45319 12.50% 87.46% | 45459 12.54% 100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 362477
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 82609 12.50% 12.50% | 82595 12.50% 25.00% | 82589 12.50% 37.50% | 82459 12.48% 49.98% | 82626 12.50% 62.48% | 82687 12.51% 75.00% | 82597 12.50% 87.50% | 82607 12.50% 100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 660769
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 59 10.15% 10.15% | 49 8.43% 18.59% | 69 11.88% 30.46% | 70 12.05% 42.51% | 91 15.66% 58.18% | 87 14.97% 73.15% | 78 13.43% 86.57% | 78 13.43% 100.00%
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 581
-system.ruby.L1Cache_Controller.S_L.L1_Replacement | 142 14.42% 14.42% | 139 14.11% 28.53% | 85 8.63% 37.16% | 113 11.47% 48.63% | 125 12.69% 61.32% | 129 13.10% 74.42% | 149 15.13% 89.54% | 103 10.46% 100.00%
-system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 985
-system.ruby.L1Cache_Controller.S_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S_L.Transient_Local_GETS::total 1
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 2 2.47% 2.47% | 7 8.64% 11.11% | 7 8.64% 19.75% | 13 16.05% 35.80% | 11 13.58% 49.38% | 17 20.99% 70.37% | 24 29.63% 100.00%
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 81
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 51 11.70% 11.70% | 46 10.55% 22.25% | 49 11.24% 33.49% | 48 11.01% 44.50% | 57 13.07% 57.57% | 54 12.39% 69.95% | 68 15.60% 85.55% | 63 14.45% 100.00%
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 436
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 565 10.94% 10.94% | 424 8.21% 19.15% | 773 14.97% 34.12% | 681 13.19% 47.31% | 662 12.82% 60.13% | 600 11.62% 71.75% | 945 18.30% 90.05% | 514 9.95% 100.00%
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 5164
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 3 21.43% 21.43% | 1 7.14% 28.57% | 1 7.14% 35.71% | 0 0.00% 35.71% | 0 0.00% 35.71% | 3 21.43% 57.14% | 4 28.57% 85.71% | 2 14.29% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 14
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total 2
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 16.67% 16.67% | 0 0.00% 16.67% | 5 83.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 6
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 2 4.08% 4.08% | 6 12.24% 16.33% | 3 6.12% 22.45% | 6 12.24% 34.69% | 6 12.24% 46.94% | 14 28.57% 75.51% | 12 24.49% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 49
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 1.43% 1.43% | 6 8.57% 10.00% | 7 10.00% 20.00% | 11 15.71% 35.71% | 10 14.29% 50.00% | 21 30.00% 80.00% | 14 20.00% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 70
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 105 12.04% 12.04% | 90 10.32% 22.36% | 113 12.96% 35.32% | 117 13.42% 48.74% | 112 12.84% 61.58% | 101 11.58% 73.17% | 125 14.33% 87.50% | 109 12.50% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 872
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 157 10.06% 10.06% | 120 7.69% 17.75% | 259 16.59% 34.34% | 210 13.45% 47.79% | 169 10.83% 58.62% | 143 9.16% 67.78% | 356 22.81% 90.58% | 147 9.42% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 1561
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 1145 11.85% 11.85% | 1078 11.16% 23.01% | 1089 11.27% 34.28% | 1106 11.45% 45.73% | 1258 13.02% 58.75% | 1402 14.51% 73.26% | 1287 13.32% 86.59% | 1296 13.41% 100.00%
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 9661
-system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 4
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 3 8.57% 8.57% | 3 8.57% 17.14% | 4 11.43% 28.57% | 5 14.29% 42.86% | 3 8.57% 51.43% | 8 22.86% 74.29% | 9 25.71% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 35
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 1
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 6
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 5 6.10% 6.10% | 8 9.76% 15.85% | 10 12.20% 28.05% | 6 7.32% 35.37% | 16 19.51% 54.88% | 17 20.73% 75.61% | 20 24.39% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 82
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 10 7.58% 7.58% | 9 6.82% 14.39% | 15 11.36% 25.76% | 15 11.36% 37.12% | 23 17.42% 54.55% | 34 25.76% 80.30% | 26 19.70% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 132
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 190 11.41% 11.41% | 194 11.65% 23.06% | 196 11.77% 34.83% | 205 12.31% 47.15% | 229 13.75% 60.90% | 216 12.97% 73.87% | 220 13.21% 87.09% | 215 12.91% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 1665
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 322 10.58% 10.58% | 382 12.55% 23.14% | 377 12.39% 35.52% | 351 11.53% 47.06% | 409 13.44% 60.50% | 501 16.46% 76.96% | 309 10.15% 87.12% | 392 12.88% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 3043
-system.ruby.L2Cache_Controller.L1_GETS 403097 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS_Last_Token 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 223308 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_INV 1037 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 510458 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Shared_Data 1095 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens 623664 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Owned 588 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX 51938 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS 94665 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 145349 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 401663 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 222518 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_INV 556 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 896 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 509229 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Owned 341 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 131369 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS 114 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETX 61 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_INV 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L2_Replacement 14121 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 358 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Owned 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Persistent_GETX 23 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Persistent_GETS 39 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 829 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 84 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Persistent_GETS 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L1_GETS 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L2_Replacement 773 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 572 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETS 29 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1028 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 591 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 493571 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETX 5438 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETS 9607 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETS 270 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETX 138 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L1_INV 479 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L2_Replacement 1163 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 175 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 113421 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Owned 241 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX 46476 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS 84985 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 13945 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_L.L2_Replacement 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_L.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 35 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu1]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu2]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl2.sequencer.slave[0]
-
-[system.cpu3]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl3.sequencer.slave[0]
-
-[system.cpu4]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl4.sequencer.slave[0]
-
-[system.cpu5]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl5.sequencer.slave[0]
-
-[system.cpu6]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl6.sequencer.slave[0]
-
-[system.cpu7]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl7.sequencer.slave[0]
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:268435455
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=8
-number_of_virtual_networks=6
-phys_mem=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter requestToDir responseFromDir responseFromMemory responseToDir triggerQueue unblockToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-directory=system.ruby.dir_cntrl0.directory
-dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
-dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-from_memory_controller_latency=2
-full_bit_dir_enabled=false
-number_of_TBEs=256
-probeFilter=system.ruby.dir_cntrl0.probeFilter
-probe_filter_enabled=false
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-triggerQueue=system.ruby.dir_cntrl0.triggerQueue
-unblockToDir=system.ruby.dir_cntrl0.unblockToDir
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[19]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[26]
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[24]
-
-[system.ruby.dir_cntrl0.probeFilter]
-type=RubyCache
-children=replacement_policy
-assoc=4
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.dir_cntrl0.probeFilter.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=1024
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.dir_cntrl0.probeFilter.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=4
-block_size=64
-eventq_index=0
-size=1024
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[18]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[25]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[17]
-
-[system.ruby.dir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.dir_cntrl0.unblockToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[16]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-L2cache=system.ruby.l1_cntrl0.L2cache
-buffer_size=0
-cache_response_latency=10
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl0.forwardToCache
-issue_latency=2
-l2_cache_hit_latency=10
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-no_mig_atomic=true
-number_of_TBEs=256
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl0.requestFromCache
-responseFromCache=system.ruby.l1_cntrl0.responseFromCache
-responseToCache=system.ruby.l1_cntrl0.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl0.triggerQueue
-unblockFromCache=system.ruby.l1_cntrl0.unblockFromCache
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l1_cntrl0.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.requestFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.responseFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.cpu0.port
-
-[system.ruby.l1_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.unblockFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache
-L1Dcache=system.ruby.l1_cntrl1.L1Dcache
-L1Icache=system.ruby.l1_cntrl1.L1Icache
-L2cache=system.ruby.l1_cntrl1.L2cache
-buffer_size=0
-cache_response_latency=10
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl1.forwardToCache
-issue_latency=2
-l2_cache_hit_latency=10
-mandatoryQueue=system.ruby.l1_cntrl1.mandatoryQueue
-no_mig_atomic=true
-number_of_TBEs=256
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl1.requestFromCache
-responseFromCache=system.ruby.l1_cntrl1.responseFromCache
-responseToCache=system.ruby.l1_cntrl1.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl1.triggerQueue
-unblockFromCache=system.ruby.l1_cntrl1.unblockFromCache
-version=1
-
-[system.ruby.l1_cntrl1.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl1.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl1.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl1.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl1.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl1.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l1_cntrl1.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.l1_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl1.requestFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.l1_cntrl1.responseFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.l1_cntrl1.responseToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.l1_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl1.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl1.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-slave=system.cpu1.port
-
-[system.ruby.l1_cntrl1.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
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-
-[system.ruby.l1_cntrl1.unblockFromCache]
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-
-[system.ruby.l1_cntrl2]
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-[system.ruby.l1_cntrl2.L1Dcache]
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-
-[system.ruby.l1_cntrl2.L1Dcache.replacement_policy]
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-
-[system.ruby.l1_cntrl2.L1Icache]
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-
-[system.ruby.l1_cntrl2.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl2.L2cache]
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-
-[system.ruby.l1_cntrl2.L2cache.replacement_policy]
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-
-[system.ruby.l1_cntrl2.forwardToCache]
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-[system.ruby.l1_cntrl2.mandatoryQueue]
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-[system.ruby.l1_cntrl2.requestFromCache]
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-
-[system.ruby.l1_cntrl2.responseFromCache]
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-
-[system.ruby.l1_cntrl2.responseToCache]
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-
-[system.ruby.l1_cntrl2.sequencer]
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-
-[system.ruby.l1_cntrl2.triggerQueue]
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-[system.ruby.l1_cntrl2.unblockFromCache]
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-
-[system.ruby.l1_cntrl3]
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-
-[system.ruby.l1_cntrl3.L1Dcache]
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-
-[system.ruby.l1_cntrl3.L1Dcache.replacement_policy]
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-[system.ruby.l1_cntrl3.L1Icache]
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-
-[system.ruby.l1_cntrl3.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl3.L2cache]
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-
-[system.ruby.l1_cntrl3.L2cache.replacement_policy]
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-
-[system.ruby.l1_cntrl3.forwardToCache]
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-[system.ruby.l1_cntrl3.mandatoryQueue]
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-[system.ruby.l1_cntrl3.requestFromCache]
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-[system.ruby.l1_cntrl3.responseFromCache]
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-[system.ruby.l1_cntrl3.responseToCache]
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-[system.ruby.l1_cntrl3.sequencer]
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-[system.ruby.l1_cntrl3.triggerQueue]
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-[system.ruby.l1_cntrl3.unblockFromCache]
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-[system.ruby.l1_cntrl4]
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-[system.ruby.l1_cntrl4.L1Dcache]
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-[system.ruby.l1_cntrl4.L1Dcache.replacement_policy]
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-[system.ruby.l1_cntrl4.L1Icache]
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-[system.ruby.l1_cntrl4.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl4.L2cache]
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-[system.ruby.l1_cntrl4.L2cache.replacement_policy]
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-[system.ruby.l1_cntrl4.forwardToCache]
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-[system.ruby.l1_cntrl4.mandatoryQueue]
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-[system.ruby.l1_cntrl4.requestFromCache]
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-[system.ruby.l1_cntrl4.responseFromCache]
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-[system.ruby.l1_cntrl4.responseToCache]
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-[system.ruby.l1_cntrl4.sequencer]
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-[system.ruby.l1_cntrl4.triggerQueue]
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-[system.ruby.l1_cntrl4.unblockFromCache]
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-[system.ruby.l1_cntrl5]
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-[system.ruby.l1_cntrl5.L1Dcache]
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-
-[system.ruby.l1_cntrl5.L1Dcache.replacement_policy]
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-[system.ruby.l1_cntrl5.L1Icache]
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-
-[system.ruby.l1_cntrl5.L1Icache.replacement_policy]
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-[system.ruby.l1_cntrl5.L2cache]
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-
-[system.ruby.l1_cntrl5.L2cache.replacement_policy]
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-[system.ruby.l1_cntrl5.forwardToCache]
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-[system.ruby.l1_cntrl5.mandatoryQueue]
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-[system.ruby.l1_cntrl5.requestFromCache]
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-[system.ruby.l1_cntrl5.responseFromCache]
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-[system.ruby.l1_cntrl5.responseToCache]
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-[system.ruby.l1_cntrl5.sequencer]
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-[system.ruby.l1_cntrl5.triggerQueue]
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-[system.ruby.l1_cntrl5.unblockFromCache]
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-[system.ruby.l1_cntrl6]
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-[system.ruby.l1_cntrl6.L1Dcache]
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-replacement_policy=system.ruby.l1_cntrl6.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl6.L1Icache]
-type=RubyCache
-children=replacement_policy
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-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl6.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl6.L2cache]
-type=RubyCache
-children=replacement_policy
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-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl6.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l1_cntrl6.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[12]
-
-[system.ruby.l1_cntrl6.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl6.requestFromCache]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[18]
-
-[system.ruby.l1_cntrl6.responseFromCache]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[19]
-
-[system.ruby.l1_cntrl6.responseToCache]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.ruby.l1_cntrl6.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
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-deadlock_threshold=1000000
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-icache=system.ruby.l1_cntrl6.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
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-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
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-version=6
-slave=system.cpu6.port
-
-[system.ruby.l1_cntrl6.triggerQueue]
-type=MessageBuffer
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-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl6.unblockFromCache]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[20]
-
-[system.ruby.l1_cntrl7]
-type=L1Cache_Controller
-children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache
-L1Dcache=system.ruby.l1_cntrl7.L1Dcache
-L1Icache=system.ruby.l1_cntrl7.L1Icache
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-buffer_size=0
-cache_response_latency=10
-clk_domain=system.cpu_clk_domain
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-forwardToCache=system.ruby.l1_cntrl7.forwardToCache
-issue_latency=2
-l2_cache_hit_latency=10
-mandatoryQueue=system.ruby.l1_cntrl7.mandatoryQueue
-no_mig_atomic=true
-number_of_TBEs=256
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl7.requestFromCache
-responseFromCache=system.ruby.l1_cntrl7.responseFromCache
-responseToCache=system.ruby.l1_cntrl7.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl7.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl7.triggerQueue
-unblockFromCache=system.ruby.l1_cntrl7.unblockFromCache
-version=7
-
-[system.ruby.l1_cntrl7.L1Dcache]
-type=RubyCache
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-replacement_policy=system.ruby.l1_cntrl7.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
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-
-[system.ruby.l1_cntrl7.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-size=256
-
-[system.ruby.l1_cntrl7.L1Icache]
-type=RubyCache
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-replacement_policy=system.ruby.l1_cntrl7.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
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-start_index_bit=6
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-tagArrayBanks=1
-
-[system.ruby.l1_cntrl7.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl7.L2cache]
-type=RubyCache
-children=replacement_policy
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-dataArrayBanks=1
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-replacement_policy=system.ruby.l1_cntrl7.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl7.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l1_cntrl7.forwardToCache]
-type=MessageBuffer
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-ordered=false
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-slave=system.ruby.network.master[14]
-
-[system.ruby.l1_cntrl7.mandatoryQueue]
-type=MessageBuffer
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-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl7.requestFromCache]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl7.responseFromCache]
-type=MessageBuffer
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-ordered=false
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-master=system.ruby.network.slave[22]
-
-[system.ruby.l1_cntrl7.responseToCache]
-type=MessageBuffer
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-slave=system.ruby.network.master[15]
-
-[system.ruby.l1_cntrl7.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
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-
-[system.ruby.l1_cntrl7.triggerQueue]
-type=MessageBuffer
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-
-[system.ruby.l1_cntrl7.unblockFromCache]
-type=MessageBuffer
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-
-[system.ruby.memctrl_clk_domain]
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-
-[system.ruby.network]
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-adaptive_routing=false
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-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8
-netifs=
-number_of_virtual_networks=6
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5 system.ruby.network.routers6 system.ruby.network.routers7 system.ruby.network.routers8 system.ruby.network.routers9
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.l1_cntrl1.forwardToCache.slave system.ruby.l1_cntrl1.responseToCache.slave system.ruby.l1_cntrl2.forwardToCache.slave system.ruby.l1_cntrl2.responseToCache.slave system.ruby.l1_cntrl3.forwardToCache.slave system.ruby.l1_cntrl3.responseToCache.slave system.ruby.l1_cntrl4.forwardToCache.slave system.ruby.l1_cntrl4.responseToCache.slave system.ruby.l1_cntrl5.forwardToCache.slave system.ruby.l1_cntrl5.responseToCache.slave system.ruby.l1_cntrl6.forwardToCache.slave system.ruby.l1_cntrl6.responseToCache.slave system.ruby.l1_cntrl7.forwardToCache.slave system.ruby.l1_cntrl7.responseToCache.slave system.ruby.dir_cntrl0.unblockToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl0.unblockFromCache.master system.ruby.l1_cntrl1.requestFromCache.master system.ruby.l1_cntrl1.responseFromCache.master system.ruby.l1_cntrl1.unblockFromCache.master system.ruby.l1_cntrl2.requestFromCache.master system.ruby.l1_cntrl2.responseFromCache.master system.ruby.l1_cntrl2.unblockFromCache.master system.ruby.l1_cntrl3.requestFromCache.master system.ruby.l1_cntrl3.responseFromCache.master system.ruby.l1_cntrl3.unblockFromCache.master system.ruby.l1_cntrl4.requestFromCache.master system.ruby.l1_cntrl4.responseFromCache.master system.ruby.l1_cntrl4.unblockFromCache.master system.ruby.l1_cntrl5.requestFromCache.master system.ruby.l1_cntrl5.responseFromCache.master system.ruby.l1_cntrl5.unblockFromCache.master system.ruby.l1_cntrl6.requestFromCache.master system.ruby.l1_cntrl6.responseFromCache.master system.ruby.l1_cntrl6.unblockFromCache.master system.ruby.l1_cntrl7.requestFromCache.master system.ruby.l1_cntrl7.responseFromCache.master system.ruby.l1_cntrl7.unblockFromCache.master system.ruby.dir_cntrl0.forwardFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl1
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl2
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.ext_links3]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl3
-int_node=system.ruby.network.routers3
-latency=1
-link_id=3
-weight=1
-
-[system.ruby.network.ext_links4]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl4
-int_node=system.ruby.network.routers4
-latency=1
-link_id=4
-weight=1
-
-[system.ruby.network.ext_links5]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl5
-int_node=system.ruby.network.routers5
-latency=1
-link_id=5
-weight=1
-
-[system.ruby.network.ext_links6]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl6
-int_node=system.ruby.network.routers6
-latency=1
-link_id=6
-weight=1
-
-[system.ruby.network.ext_links7]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl7
-int_node=system.ruby.network.routers7
-latency=1
-link_id=7
-weight=1
-
-[system.ruby.network.ext_links8]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers8
-latency=1
-link_id=8
-weight=1
-
-[system.ruby.network.int_link_buffers000]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers001]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers002]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers003]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers004]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers005]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers006]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers007]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers008]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers009]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers082]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers083]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers084]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers085]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers086]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers087]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers088]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers089]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers090]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers091]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers092]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers093]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers094]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers095]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers096]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers097]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers098]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers099]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers100]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers101]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers102]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers103]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers104]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers105]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers106]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers107]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-system.cpu6: completed 10000 read, 5442 write accesses @464151
-system.cpu5: completed 10000 read, 5565 write accesses @467904
-system.cpu1: completed 10000 read, 5530 write accesses @472727
-system.cpu4: completed 10000 read, 5671 write accesses @474893
-system.cpu2: completed 10000 read, 5702 write accesses @475545
-system.cpu3: completed 10000 read, 5626 write accesses @475848
-system.cpu7: completed 10000 read, 5688 write accesses @476316
-system.cpu0: completed 10000 read, 5652 write accesses @477657
-system.cpu6: completed 20000 read, 11069 write accesses @933991
-system.cpu4: completed 20000 read, 11035 write accesses @941133
-system.cpu1: completed 20000 read, 11144 write accesses @942887
-system.cpu5: completed 20000 read, 11075 write accesses @943473
-system.cpu7: completed 20000 read, 11122 write accesses @946462
-system.cpu2: completed 20000 read, 11251 write accesses @952011
-system.cpu3: completed 20000 read, 11149 write accesses @953947
-system.cpu0: completed 20000 read, 11405 write accesses @958457
-system.cpu4: completed 30000 read, 16671 write accesses @1411581
-system.cpu5: completed 30000 read, 16602 write accesses @1411822
-system.cpu7: completed 30000 read, 16713 write accesses @1419018
-system.cpu6: completed 30000 read, 16615 write accesses @1420265
-system.cpu3: completed 30000 read, 16709 write accesses @1421765
-system.cpu1: completed 30000 read, 16889 write accesses @1427949
-system.cpu2: completed 30000 read, 16908 write accesses @1434738
-system.cpu0: completed 30000 read, 17031 write accesses @1444971
-system.cpu5: completed 40000 read, 22172 write accesses @1880249
-system.cpu3: completed 40000 read, 22160 write accesses @1893274
-system.cpu6: completed 40000 read, 22289 write accesses @1896273
-system.cpu1: completed 40000 read, 22624 write accesses @1896553
-system.cpu4: completed 40000 read, 22359 write accesses @1896744
-system.cpu7: completed 40000 read, 22432 write accesses @1900299
-system.cpu2: completed 40000 read, 22368 write accesses @1910277
-system.cpu0: completed 40000 read, 22621 write accesses @1917733
-system.cpu5: completed 50000 read, 27506 write accesses @2349190
-system.cpu6: completed 50000 read, 27893 write accesses @2366731
-system.cpu7: completed 50000 read, 27846 write accesses @2369147
-system.cpu3: completed 50000 read, 27646 write accesses @2369997
-system.cpu1: completed 50000 read, 27990 write accesses @2371485
-system.cpu2: completed 50000 read, 27913 write accesses @2374199
-system.cpu4: completed 50000 read, 27983 write accesses @2375243
-system.cpu0: completed 50000 read, 28279 write accesses @2400165
-system.cpu5: completed 60000 read, 33080 write accesses @2828614
-system.cpu3: completed 60000 read, 33257 write accesses @2839097
-system.cpu1: completed 60000 read, 33556 write accesses @2841959
-system.cpu6: completed 60000 read, 33572 write accesses @2843628
-system.cpu7: completed 60000 read, 33379 write accesses @2844087
-system.cpu2: completed 60000 read, 33471 write accesses @2846336
-system.cpu4: completed 60000 read, 33614 write accesses @2862059
-system.cpu0: completed 60000 read, 33892 write accesses @2874908
-system.cpu5: completed 70000 read, 38668 write accesses @3302644
-system.cpu3: completed 70000 read, 38773 write accesses @3312258
-system.cpu7: completed 70000 read, 38856 write accesses @3313701
-system.cpu1: completed 70000 read, 39110 write accesses @3314841
-system.cpu6: completed 70000 read, 39295 write accesses @3319370
-system.cpu2: completed 70000 read, 39264 write accesses @3327548
-system.cpu4: completed 70000 read, 39102 write accesses @3335340
-system.cpu0: completed 70000 read, 39326 write accesses @3351991
-system.cpu5: completed 80000 read, 44247 write accesses @3772436
-system.cpu3: completed 80000 read, 44360 write accesses @3783174
-system.cpu1: completed 80000 read, 44568 write accesses @3784069
-system.cpu6: completed 80000 read, 44689 write accesses @3792375
-system.cpu2: completed 80000 read, 44751 write accesses @3797997
-system.cpu7: completed 80000 read, 44339 write accesses @3798680
-system.cpu4: completed 80000 read, 44675 write accesses @3804996
-system.cpu0: completed 80000 read, 44775 write accesses @3826542
-system.cpu5: completed 90000 read, 49884 write accesses @4250135
-system.cpu3: completed 90000 read, 49904 write accesses @4252427
-system.cpu6: completed 90000 read, 50171 write accesses @4263343
-system.cpu1: completed 90000 read, 50197 write accesses @4265783
-system.cpu4: completed 90000 read, 50286 write accesses @4279784
-system.cpu7: completed 90000 read, 50179 write accesses @4284358
-system.cpu2: completed 90000 read, 50246 write accesses @4285069
-system.cpu0: completed 90000 read, 50200 write accesses @4290832
-system.cpu3: completed 100000 read, 55486 write accesses @4722948
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 13:56:08
-gem5 started Jan 21 2016 13:56:42
-gem5 executing on zizzer, pid 39366
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 4722948 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.004723 # Number of seconds simulated
-sim_ticks 4722948 # Number of ticks simulated
-final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 61998 # Simulator tick rate (ticks/s)
-host_mem_usage 471708 # Number of bytes of host memory used
-host_seconds 76.18 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 38973248 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14131456 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 14131456 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 608957 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 608957 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 220804 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 220804 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 8251890133 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 8251890133 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 2992083758 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 2992083758 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 11243973891 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 11243973891 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 608977 # Number of read requests accepted
-system.mem_ctrls.writeReqs 220804 # Number of write requests accepted
-system.mem_ctrls.readBursts 608977 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 220804 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 37976000 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 997824 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 13939200 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 38974528 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 14131456 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 15591 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 2959 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 74105 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 73980 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 74679 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 74154 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 74161 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 73974 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 74309 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 74013 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 27203 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 26999 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 27374 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 27330 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 26957 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 27414 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 27321 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 27202 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 424 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 4722934 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 608977 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 220804 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 169 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 460 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 895 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 1451 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 2111 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 3075 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 4290 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 5411 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 7051 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 8881 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 11531 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 15691 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 22424 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 32193 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 44982 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 58729 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 70091 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 72682 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 65307 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 51432 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 36131 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 23722 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 15901 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 11796 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 9263 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 7114 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 4981 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 3028 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 1644 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 696 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 224 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 30 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 3 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 4 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 3 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 8 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 8 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 16 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 31 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 48 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 74 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 110 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 195 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 279 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 528 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 678 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 1538 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 3259 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 5632 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 8230 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 10381 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 12285 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 13587 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 14659 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 15020 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 15616 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 16200 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 16964 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 16340 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 15807 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 15724 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 16997 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 10061 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 3449 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 1011 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 658 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 446 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 318 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 289 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 239 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 718 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 219845 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 236.140481 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 186.921535 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 170.771501 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 38344 17.44% 17.44% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 94183 42.84% 60.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 45510 20.70% 80.98% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 20713 9.42% 90.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 11139 5.07% 95.47% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 5659 2.57% 98.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2638 1.20% 99.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1011 0.46% 99.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 648 0.29% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 219845 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 13607 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 43.605791 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 31.669532 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 26.121939 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-15 3129 23.00% 23.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-31 1666 12.24% 35.24% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-47 2283 16.78% 52.02% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-63 2725 20.03% 72.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-79 2805 20.61% 92.66% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-95 914 6.72% 99.38% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-111 80 0.59% 99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-127 3 0.02% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::128-143 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::272-287 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 13607 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 13607 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.006467 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.005210 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.240875 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13590 99.88% 99.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 4 0.03% 99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 3 0.02% 99.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 2 0.01% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 13607 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 74869628 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 86143753 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 2966875 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 126.17 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 145.17 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 8040.74 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 2951.38 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 8252.16 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 2992.08 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 85.88 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 62.82 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 23.06 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 19.71 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 50.33 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 379695 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 211632 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 63.99 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 97.15 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 5.69 # Average gap between requests
-system.mem_ctrls.pageHitRate 72.89 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1660380120 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 922433400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7398231360 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2256004224 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 308187360 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 3215945016 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 10178400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 15771359880 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 3342.354273 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 10 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 157560 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 4561082 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 308187360 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 101967984 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 2741691600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3151846944 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.967687 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 4561016 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 157560 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99221 # number of read accesses completed
-system.cpu0.num_writes 55233 # number of write accesses completed
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 99634 # number of read accesses completed
-system.cpu1.num_writes 55697 # number of write accesses completed
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 99089 # number of read accesses completed
-system.cpu2.num_writes 55519 # number of write accesses completed
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 100000 # number of read accesses completed
-system.cpu3.num_writes 55486 # number of write accesses completed
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 99397 # number of read accesses completed
-system.cpu4.num_writes 55450 # number of write accesses completed
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 99838 # number of read accesses completed
-system.cpu5.num_writes 55386 # number of write accesses completed
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 99890 # number of read accesses completed
-system.cpu6.num_writes 55532 # number of write accesses completed
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 99124 # number of read accesses completed
-system.cpu7.num_writes 55205 # number of write accesses completed
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 630039
-system.ruby.outstanding_req_hist_seqr::mean 15.998449
-system.ruby.outstanding_req_hist_seqr::gmean 15.997191
-system.ruby.outstanding_req_hist_seqr::stdev 0.125577
-system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 33 0.01% 0.02% | 629902 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 630039
-system.ruby.latency_hist_seqr::bucket_size 512
-system.ruby.latency_hist_seqr::max_bucket 5119
-system.ruby.latency_hist_seqr::samples 629911
-system.ruby.latency_hist_seqr::mean 959.551335
-system.ruby.latency_hist_seqr::gmean 653.122123
-system.ruby.latency_hist_seqr::stdev 680.118422
-system.ruby.latency_hist_seqr | 216304 34.34% 34.34% | 132336 21.01% 55.35% | 131857 20.93% 76.28% | 106965 16.98% 93.26% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 629911
-system.ruby.hit_latency_hist_seqr::bucket_size 128
-system.ruby.hit_latency_hist_seqr::max_bucket 1279
-system.ruby.hit_latency_hist_seqr::samples 662
-system.ruby.hit_latency_hist_seqr::mean 64.490937
-system.ruby.hit_latency_hist_seqr::gmean 13.604512
-system.ruby.hit_latency_hist_seqr::stdev 143.889590
-system.ruby.hit_latency_hist_seqr | 564 85.20% 85.20% | 45 6.80% 91.99% | 27 4.08% 96.07% | 10 1.51% 97.58% | 5 0.76% 98.34% | 4 0.60% 98.94% | 4 0.60% 99.55% | 2 0.30% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00%
-system.ruby.hit_latency_hist_seqr::total 662
-system.ruby.miss_latency_hist_seqr::bucket_size 512
-system.ruby.miss_latency_hist_seqr::max_bucket 5119
-system.ruby.miss_latency_hist_seqr::samples 629249
-system.ruby.miss_latency_hist_seqr::mean 960.492981
-system.ruby.miss_latency_hist_seqr::gmean 655.787621
-system.ruby.miss_latency_hist_seqr::stdev 679.839862
-system.ruby.miss_latency_hist_seqr | 215658 34.27% 34.27% | 132321 21.03% 55.30% | 131856 20.95% 76.26% | 106965 17.00% 93.25% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 629249
-system.ruby.L1Cache.incomplete_times_seqr 962
-system.ruby.Directory.incomplete_times_seqr 176578
-system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
-system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
-system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 10 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 78639 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78649 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits 70 # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses 78569 # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses 78639 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.fully_busy_cycles 19 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 13 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 78770 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78783 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L2cache.demand_hits 66 # Number of cache demand hits
-system.ruby.l1_cntrl1.L2cache.demand_misses 78704 # Number of cache demand misses
-system.ruby.l1_cntrl1.L2cache.demand_accesses 78770 # Number of cache demand accesses
-system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.fully_busy_cycles 15 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 78920 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78939 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L2cache.demand_hits 68 # Number of cache demand hits
-system.ruby.l1_cntrl2.L2cache.demand_misses 78852 # Number of cache demand misses
-system.ruby.l1_cntrl2.L2cache.demand_accesses 78920 # Number of cache demand accesses
-system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.fully_busy_cycles 16 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl3.L1Dcache.demand_hits 12 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 78627 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78639 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L2cache.demand_hits 62 # Number of cache demand hits
-system.ruby.l1_cntrl3.L2cache.demand_misses 78565 # Number of cache demand misses
-system.ruby.l1_cntrl3.L2cache.demand_accesses 78627 # Number of cache demand accesses
-system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.fully_busy_cycles 14 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl4.L1Dcache.demand_hits 19 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses 78575 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78594 # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl4.L2cache.demand_hits 52 # Number of cache demand hits
-system.ruby.l1_cntrl4.L2cache.demand_misses 78523 # Number of cache demand misses
-system.ruby.l1_cntrl4.L2cache.demand_accesses 78575 # Number of cache demand accesses
-system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.fully_busy_cycles 17 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses 78844 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78863 # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl5.L2cache.demand_hits 64 # Number of cache demand hits
-system.ruby.l1_cntrl5.L2cache.demand_misses 78780 # Number of cache demand misses
-system.ruby.l1_cntrl5.L2cache.demand_accesses 78844 # Number of cache demand accesses
-system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.fully_busy_cycles 18 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl6.L1Dcache.demand_hits 20 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses 78880 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78900 # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl6.L2cache.demand_hits 70 # Number of cache demand hits
-system.ruby.l1_cntrl6.L2cache.demand_misses 78810 # Number of cache demand misses
-system.ruby.l1_cntrl6.L2cache.demand_accesses 78880 # Number of cache demand accesses
-system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.fully_busy_cycles 21 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses 78558 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78572 # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl7.L2cache.demand_hits 84 # Number of cache demand hits
-system.ruby.l1_cntrl7.L2cache.demand_misses 78474 # Number of cache demand misses
-system.ruby.l1_cntrl7.L2cache.demand_accesses 78558 # Number of cache demand accesses
-system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.fully_busy_cycles 9 # cycles for which number of transistions == max transitions
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 15.732330
-system.ruby.network.routers0.msg_count.Request_Control::2 78569
-system.ruby.network.routers0.msg_count.Request_Control::3 120
-system.ruby.network.routers0.msg_count.Response_Data::4 81078
-system.ruby.network.routers0.msg_count.Response_Control::4 1094079
-system.ruby.network.routers0.msg_count.Writeback_Data::5 27411
-system.ruby.network.routers0.msg_count.Writeback_Control::2 73981
-system.ruby.network.routers0.msg_count.Writeback_Control::3 73979
-system.ruby.network.routers0.msg_count.Writeback_Control::5 46380
-system.ruby.network.routers0.msg_count.Broadcast_Control::3 549858
-system.ruby.network.routers0.msg_count.Unblock_Control::5 78752
-system.ruby.network.routers0.msg_bytes.Request_Control::2 628552
-system.ruby.network.routers0.msg_bytes.Request_Control::3 960
-system.ruby.network.routers0.msg_bytes.Response_Data::4 5837616
-system.ruby.network.routers0.msg_bytes.Response_Control::4 8752632
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5 1973592
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2 591848
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 591832
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5 371040
-system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4398864
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5 630016
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 15.771198
-system.ruby.network.routers1.msg_count.Request_Control::2 78704
-system.ruby.network.routers1.msg_count.Request_Control::3 125
-system.ruby.network.routers1.msg_count.Response_Data::4 81308
-system.ruby.network.routers1.msg_count.Response_Control::4 1095010
-system.ruby.network.routers1.msg_count.Writeback_Data::5 27816
-system.ruby.network.routers1.msg_count.Writeback_Control::2 74303
-system.ruby.network.routers1.msg_count.Writeback_Control::3 74303
-system.ruby.network.routers1.msg_count.Writeback_Control::5 46302
-system.ruby.network.routers1.msg_count.Broadcast_Control::3 549713
-system.ruby.network.routers1.msg_count.Unblock_Control::5 78886
-system.ruby.network.routers1.msg_bytes.Request_Control::2 629632
-system.ruby.network.routers1.msg_bytes.Request_Control::3 1000
-system.ruby.network.routers1.msg_bytes.Response_Data::4 5854176
-system.ruby.network.routers1.msg_bytes.Response_Control::4 8760080
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5 2002752
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2 594424
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 594424
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370416
-system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4397704
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5 631088
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 15.778059
-system.ruby.network.routers2.msg_count.Request_Control::2 78852
-system.ruby.network.routers2.msg_count.Request_Control::3 126
-system.ruby.network.routers2.msg_count.Response_Data::4 81411
-system.ruby.network.routers2.msg_count.Response_Control::4 1095892
-system.ruby.network.routers2.msg_count.Writeback_Data::5 27700
-system.ruby.network.routers2.msg_count.Writeback_Control::2 74392
-system.ruby.network.routers2.msg_count.Writeback_Control::3 74390
-system.ruby.network.routers2.msg_count.Writeback_Control::5 46510
-system.ruby.network.routers2.msg_count.Broadcast_Control::3 549569
-system.ruby.network.routers2.msg_count.Unblock_Control::5 79028
-system.ruby.network.routers2.msg_bytes.Request_Control::2 630816
-system.ruby.network.routers2.msg_bytes.Request_Control::3 1008
-system.ruby.network.routers2.msg_bytes.Response_Data::4 5861592
-system.ruby.network.routers2.msg_bytes.Response_Control::4 8767136
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5 1994400
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2 595136
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 595120
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5 372080
-system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4396552
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5 632224
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 15.737131
-system.ruby.network.routers3.msg_count.Request_Control::2 78565
-system.ruby.network.routers3.msg_count.Request_Control::3 100
-system.ruby.network.routers3.msg_count.Response_Data::4 81040
-system.ruby.network.routers3.msg_count.Response_Control::4 1094133
-system.ruby.network.routers3.msg_count.Writeback_Data::5 27552
-system.ruby.network.routers3.msg_count.Writeback_Control::2 74010
-system.ruby.network.routers3.msg_count.Writeback_Control::3 74010
-system.ruby.network.routers3.msg_count.Writeback_Control::5 46295
-system.ruby.network.routers3.msg_count.Broadcast_Control::3 549867
-system.ruby.network.routers3.msg_count.Unblock_Control::5 78725
-system.ruby.network.routers3.msg_bytes.Request_Control::2 628520
-system.ruby.network.routers3.msg_bytes.Request_Control::3 800
-system.ruby.network.routers3.msg_bytes.Response_Data::4 5834880
-system.ruby.network.routers3.msg_bytes.Response_Control::4 8753064
-system.ruby.network.routers3.msg_bytes.Writeback_Data::5 1983744
-system.ruby.network.routers3.msg_bytes.Writeback_Control::2 592080
-system.ruby.network.routers3.msg_bytes.Writeback_Control::3 592080
-system.ruby.network.routers3.msg_bytes.Writeback_Control::5 370360
-system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4398936
-system.ruby.network.routers3.msg_bytes.Unblock_Control::5 629800
-system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers4.percent_links_utilized 15.736924
-system.ruby.network.routers4.msg_count.Request_Control::2 78523
-system.ruby.network.routers4.msg_count.Request_Control::3 120
-system.ruby.network.routers4.msg_count.Response_Data::4 81065
-system.ruby.network.routers4.msg_count.Response_Control::4 1093829
-system.ruby.network.routers4.msg_count.Writeback_Data::5 27526
-system.ruby.network.routers4.msg_count.Writeback_Control::2 74103
-system.ruby.network.routers4.msg_count.Writeback_Control::3 74101
-system.ruby.network.routers4.msg_count.Writeback_Control::5 46392
-system.ruby.network.routers4.msg_count.Broadcast_Control::3 549899
-system.ruby.network.routers4.msg_count.Unblock_Control::5 78702
-system.ruby.network.routers4.msg_bytes.Request_Control::2 628184
-system.ruby.network.routers4.msg_bytes.Request_Control::3 960
-system.ruby.network.routers4.msg_bytes.Response_Data::4 5836680
-system.ruby.network.routers4.msg_bytes.Response_Control::4 8750632
-system.ruby.network.routers4.msg_bytes.Writeback_Data::5 1981872
-system.ruby.network.routers4.msg_bytes.Writeback_Control::2 592824
-system.ruby.network.routers4.msg_bytes.Writeback_Control::3 592808
-system.ruby.network.routers4.msg_bytes.Writeback_Control::5 371136
-system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4399192
-system.ruby.network.routers4.msg_bytes.Unblock_Control::5 629616
-system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers5.percent_links_utilized 15.767186
-system.ruby.network.routers5.msg_count.Request_Control::2 78780
-system.ruby.network.routers5.msg_count.Request_Control::3 112
-system.ruby.network.routers5.msg_count.Response_Data::4 81251
-system.ruby.network.routers5.msg_count.Response_Control::4 1095393
-system.ruby.network.routers5.msg_count.Writeback_Data::5 27709
-system.ruby.network.routers5.msg_count.Writeback_Control::2 74357
-system.ruby.network.routers5.msg_count.Writeback_Control::3 74354
-system.ruby.network.routers5.msg_count.Writeback_Control::5 46458
-system.ruby.network.routers5.msg_count.Broadcast_Control::3 549648
-system.ruby.network.routers5.msg_count.Unblock_Control::5 78962
-system.ruby.network.routers5.msg_bytes.Request_Control::2 630240
-system.ruby.network.routers5.msg_bytes.Request_Control::3 896
-system.ruby.network.routers5.msg_bytes.Response_Data::4 5850072
-system.ruby.network.routers5.msg_bytes.Response_Control::4 8763144
-system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1995048
-system.ruby.network.routers5.msg_bytes.Writeback_Control::2 594856
-system.ruby.network.routers5.msg_bytes.Writeback_Control::3 594832
-system.ruby.network.routers5.msg_bytes.Writeback_Control::5 371664
-system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4397184
-system.ruby.network.routers5.msg_bytes.Unblock_Control::5 631696
-system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers6.percent_links_utilized 15.767377
-system.ruby.network.routers6.msg_count.Request_Control::2 78810
-system.ruby.network.routers6.msg_count.Request_Control::3 118
-system.ruby.network.routers6.msg_count.Response_Data::4 81373
-system.ruby.network.routers6.msg_count.Response_Control::4 1095546
-system.ruby.network.routers6.msg_count.Writeback_Data::5 27545
-system.ruby.network.routers6.msg_count.Writeback_Control::2 74373
-system.ruby.network.routers6.msg_count.Writeback_Control::3 74372
-system.ruby.network.routers6.msg_count.Writeback_Control::5 46647
-system.ruby.network.routers6.msg_count.Broadcast_Control::3 549625
-system.ruby.network.routers6.msg_count.Unblock_Control::5 78987
-system.ruby.network.routers6.msg_bytes.Request_Control::2 630480
-system.ruby.network.routers6.msg_bytes.Request_Control::3 944
-system.ruby.network.routers6.msg_bytes.Response_Data::4 5858856
-system.ruby.network.routers6.msg_bytes.Response_Control::4 8764368
-system.ruby.network.routers6.msg_bytes.Writeback_Data::5 1983240
-system.ruby.network.routers6.msg_bytes.Writeback_Control::2 594984
-system.ruby.network.routers6.msg_bytes.Writeback_Control::3 594976
-system.ruby.network.routers6.msg_bytes.Writeback_Control::5 373176
-system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4397000
-system.ruby.network.routers6.msg_bytes.Unblock_Control::5 631896
-system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers7.percent_links_utilized 15.733208
-system.ruby.network.routers7.msg_count.Request_Control::2 78474
-system.ruby.network.routers7.msg_count.Request_Control::3 141
-system.ruby.network.routers7.msg_count.Response_Data::4 81016
-system.ruby.network.routers7.msg_count.Response_Control::4 1093666
-system.ruby.network.routers7.msg_count.Writeback_Data::5 27546
-system.ruby.network.routers7.msg_count.Writeback_Control::2 74028
-system.ruby.network.routers7.msg_count.Writeback_Control::3 74026
-system.ruby.network.routers7.msg_count.Writeback_Control::5 46294
-system.ruby.network.routers7.msg_count.Broadcast_Control::3 549942
-system.ruby.network.routers7.msg_count.Unblock_Control::5 78656
-system.ruby.network.routers7.msg_bytes.Request_Control::2 627792
-system.ruby.network.routers7.msg_bytes.Request_Control::3 1128
-system.ruby.network.routers7.msg_bytes.Response_Data::4 5833152
-system.ruby.network.routers7.msg_bytes.Response_Control::4 8749328
-system.ruby.network.routers7.msg_bytes.Writeback_Data::5 1983312
-system.ruby.network.routers7.msg_bytes.Writeback_Control::2 592224
-system.ruby.network.routers7.msg_bytes.Writeback_Control::3 592208
-system.ruby.network.routers7.msg_bytes.Writeback_Control::5 370352
-system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4399536
-system.ruby.network.routers7.msg_bytes.Unblock_Control::5 629248
-system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers8.percent_links_utilized 57.778553
-system.ruby.network.routers8.msg_count.Request_Control::2 629277
-system.ruby.network.routers8.msg_count.Request_Control::3 962
-system.ruby.network.routers8.msg_count.Response_Data::4 608952
-system.ruby.network.routers8.msg_count.Writeback_Data::5 220804
-system.ruby.network.routers8.msg_count.Writeback_Control::2 593547
-system.ruby.network.routers8.msg_count.Writeback_Control::3 593536
-system.ruby.network.routers8.msg_count.Writeback_Control::5 371278
-system.ruby.network.routers8.msg_count.Broadcast_Control::3 628303
-system.ruby.network.routers8.msg_count.Unblock_Control::5 630697
-system.ruby.network.routers8.msg_bytes.Request_Control::2 5034216
-system.ruby.network.routers8.msg_bytes.Request_Control::3 7696
-system.ruby.network.routers8.msg_bytes.Response_Data::4 43844544
-system.ruby.network.routers8.msg_bytes.Writeback_Data::5 15897888
-system.ruby.network.routers8.msg_bytes.Writeback_Control::2 4748376
-system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4748288
-system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2970224
-system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 5026424
-system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5045576
-system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers9.percent_links_utilized 22.639639
-system.ruby.network.routers9.msg_count.Request_Control::2 629277
-system.ruby.network.routers9.msg_count.Request_Control::3 962
-system.ruby.network.routers9.msg_count.Response_Data::4 629247
-system.ruby.network.routers9.msg_count.Response_Control::4 4378774
-system.ruby.network.routers9.msg_count.Writeback_Data::5 220805
-system.ruby.network.routers9.msg_count.Writeback_Control::2 593547
-system.ruby.network.routers9.msg_count.Writeback_Control::3 593535
-system.ruby.network.routers9.msg_count.Writeback_Control::5 371278
-system.ruby.network.routers9.msg_count.Broadcast_Control::3 4398121
-system.ruby.network.routers9.msg_count.Unblock_Control::5 630697
-system.ruby.network.routers9.msg_bytes.Request_Control::2 5034216
-system.ruby.network.routers9.msg_bytes.Request_Control::3 7696
-system.ruby.network.routers9.msg_bytes.Response_Data::4 45305784
-system.ruby.network.routers9.msg_bytes.Response_Control::4 35030192
-system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15897960
-system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4748376
-system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4748280
-system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2970224
-system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35184968
-system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5045576
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control 1890717
-system.ruby.network.msg_count.Response_Data 1887741
-system.ruby.network.msg_count.Response_Control 13136322
-system.ruby.network.msg_count.Writeback_Data 662414
-system.ruby.network.msg_count.Writeback_Control 4675081
-system.ruby.network.msg_count.Broadcast_Control 9424545
-system.ruby.network.msg_count.Unblock_Control 1892092
-system.ruby.network.msg_byte.Request_Control 15125736
-system.ruby.network.msg_byte.Response_Data 135917352
-system.ruby.network.msg_byte.Response_Control 105090576
-system.ruby.network.msg_byte.Writeback_Data 47693808
-system.ruby.network.msg_byte.Writeback_Control 37400648
-system.ruby.network.msg_byte.Broadcast_Control 75396360
-system.ruby.network.msg_byte.Unblock_Control 15136736
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 19.878030
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 120
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78565
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 546616
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 73979
-system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 549858
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 960
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5656680
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4372928
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 591832
-system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4398864
-system.ruby.network.routers0.throttle1.link_utilization 11.586630
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 78569
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 2513
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::4 547463
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 27411
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 73981
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 46380
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 78752
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 628552
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 180936
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4 4379704
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 1973592
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 591848
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 371040
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 630016
-system.ruby.network.routers1.throttle0.link_utilization 19.905269
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::3 125
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78701
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::4 547781
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 74303
-system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3 549713
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3 1000
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5666472
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4 4382248
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 594424
-system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3 4397704
-system.ruby.network.routers1.throttle1.link_utilization 11.637128
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 78704
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 2607
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 547229
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5 27816
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 74303
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5 46302
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5 78886
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 629632
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 187704
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 4377832
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5 2002752
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 594424
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5 370416
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5 631088
-system.ruby.network.routers2.throttle0.link_utilization 19.929068
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::3 126
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78848
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::4 548762
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 74390
-system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3 549569
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3 1008
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5677056
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4 4390096
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 595120
-system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3 4396552
-system.ruby.network.routers2.throttle1.link_utilization 11.627049
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 78852
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 2563
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::4 547130
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 27700
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 74392
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46510
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 79028
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 630816
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 184536
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4377040
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 1994400
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 595136
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 372080
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 632224
-system.ruby.network.routers3.throttle0.link_utilization 19.878284
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 100
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78563
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 546645
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 74010
-system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 549867
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 800
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5656536
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4373160
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 592080
-system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4398936
-system.ruby.network.routers3.throttle1.link_utilization 11.595978
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 78565
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2477
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 547488
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27552
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 74010
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46295
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78725
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 628520
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 178344
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4379904
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1983744
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 592080
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 370360
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 629800
-system.ruby.network.routers4.throttle0.link_utilization 19.872641
-system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 120
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78519
-system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 546358
-system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 74101
-system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 549899
-system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 960
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5653368
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4370864
-system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 592808
-system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4399192
-system.ruby.network.routers4.throttle1.link_utilization 11.601208
-system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78523
-system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2546
-system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 547471
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27526
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 74103
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 46392
-system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 78702
-system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 628184
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 183312
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4379768
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 1981872
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 592824
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 371136
-system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 629616
-system.ruby.network.routers5.throttle0.link_utilization 19.915506
-system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 112
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78775
-system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 548109
-system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 74354
-system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 549648
-system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 896
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5671800
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4384872
-system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 594832
-system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4397184
-system.ruby.network.routers5.throttle1.link_utilization 11.618866
-system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78780
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2476
-system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 547284
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27709
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 74357
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 46458
-system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78962
-system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 630240
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 178272
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4378272
-system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1995048
-system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 594856
-system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 371664
-system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 631696
-system.ruby.network.routers6.throttle0.link_utilization 19.921255
-system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 118
-system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78806
-system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 548372
-system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 74372
-system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 549625
-system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 944
-system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5674032
-system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4386976
-system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 594976
-system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4397000
-system.ruby.network.routers6.throttle1.link_utilization 11.613499
-system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78810
-system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2567
-system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 547174
-system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27545
-system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 74373
-system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 46647
-system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 78987
-system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 630480
-system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 184824
-system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4377392
-system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 1983240
-system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 594984
-system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 373176
-system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 631896
-system.ruby.network.routers7.throttle0.link_utilization 19.865453
-system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 141
-system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78470
-system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 546131
-system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 74026
-system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 549942
-system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 1128
-system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5649840
-system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4369048
-system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 592208
-system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4399536
-system.ruby.network.routers7.throttle1.link_utilization 11.600964
-system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78474
-system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2546
-system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 547535
-system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27546
-system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 74028
-system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 46294
-system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 78656
-system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 627792
-system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 183312
-system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4380280
-system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1983312
-system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 592224
-system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 370352
-system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 629248
-system.ruby.network.routers8.throttle0.link_utilization 44.591164
-system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 629277
-system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 220804
-system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 593547
-system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 371278
-system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 630697
-system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5034216
-system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15897888
-system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4748376
-system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2970224
-system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5045576
-system.ruby.network.routers8.throttle1.link_utilization 70.965941
-system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 962
-system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 608952
-system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 593536
-system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 628303
-system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 7696
-system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43844544
-system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4748288
-system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 5026424
-system.ruby.network.routers9.throttle0.link_utilization 19.878030
-system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 120
-system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78565
-system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 546616
-system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 73979
-system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 549858
-system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 960
-system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5656680
-system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4372928
-system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 591832
-system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4398864
-system.ruby.network.routers9.throttle1.link_utilization 19.905269
-system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 125
-system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78701
-system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 547781
-system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 74303
-system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 549713
-system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 1000
-system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5666472
-system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4382248
-system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 594424
-system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4397704
-system.ruby.network.routers9.throttle2.link_utilization 19.929068
-system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 126
-system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78848
-system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 548762
-system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 74390
-system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 549569
-system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 1008
-system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5677056
-system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4390096
-system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 595120
-system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4396552
-system.ruby.network.routers9.throttle3.link_utilization 19.878326
-system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 100
-system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78563
-system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 546645
-system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 74010
-system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 549867
-system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 800
-system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5656536
-system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4373160
-system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 592080
-system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4398936
-system.ruby.network.routers9.throttle4.link_utilization 19.872641
-system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 120
-system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78519
-system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 546358
-system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74101
-system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 549899
-system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 960
-system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5653368
-system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4370864
-system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 592808
-system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4399192
-system.ruby.network.routers9.throttle5.link_utilization 19.915506
-system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 112
-system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78775
-system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 548109
-system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 74354
-system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 549648
-system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 896
-system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5671800
-system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4384872
-system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 594832
-system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4397184
-system.ruby.network.routers9.throttle6.link_utilization 19.921255
-system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 118
-system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78806
-system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 548372
-system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74372
-system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 549625
-system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 944
-system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5674032
-system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4386976
-system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 594976
-system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4397000
-system.ruby.network.routers9.throttle7.link_utilization 19.865453
-system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 141
-system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78470
-system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 546131
-system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74026
-system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 549942
-system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 1128
-system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5649840
-system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4369048
-system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 592208
-system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4399536
-system.ruby.network.routers9.throttle8.link_utilization 44.591207
-system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 629277
-system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 220805
-system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 593547
-system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 371278
-system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 630697
-system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5034216
-system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15897960
-system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4748376
-system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2970224
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-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 25.295189
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 180.313043
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 147 84.00% 84.00% | 11 6.29% 90.29% | 7 4.00% 94.29% | 2 1.14% 95.43% | 0 0.00% 95.43% | 3 1.71% 97.14% | 3 1.71% 98.86% | 2 1.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 175
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 213572
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 960.926385
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 657.193585
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 679.626872
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 73147 34.25% 34.25% | 45007 21.07% 55.32% | 44740 20.95% 76.27% | 36252 16.97% 93.25% | 13143 6.15% 99.40% | 1260 0.59% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 213572
-system.ruby.Directory_Controller.GETX 227359 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 412013 0.00% 0.00%
-system.ruby.Directory_Controller.PUT 607708 0.00% 0.00%
-system.ruby.Directory_Controller.Unblock 1451 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockS 26373 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockM 602873 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Clean 8050 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Dirty 1352 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean 363228 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 219452 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 608953 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 220804 0.00% 0.00%
-system.ruby.Directory_Controller.All_Unblocks 962 0.00% 0.00%
-system.ruby.Directory_Controller.NX.GETX 83 0.00% 0.00%
-system.ruby.Directory_Controller.NX.GETS 74 0.00% 0.00%
-system.ruby.Directory_Controller.NX.PUT 10821 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETX 7117 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETS 12062 0.00% 0.00%
-system.ruby.Directory_Controller.NO.PUT 582725 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 9321 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETS 16807 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETX 206891 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETS 375959 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.GETX 569 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.GETS 962 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.PUT 13941 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.UnblockS 8535 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM 601412 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_X.GETX 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_X.PUT 20 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_X.UnblockS 31 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_X.UnblockM 538 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S.PUT 29 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S.UnblockS 39 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S.UnblockM 923 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S_W.GETX 4 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S_W.GETS 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S_W.PUT 112 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S_W.UnblockS 962 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 962 0.00% 0.00%
-system.ruby.Directory_Controller.O_B.GETX 10 0.00% 0.00%
-system.ruby.Directory_Controller.O_B.GETS 32 0.00% 0.00%
-system.ruby.Directory_Controller.O_B.UnblockS 16806 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.GETX 1902 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.GETS 3515 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data 592146 0.00% 0.00%
-system.ruby.Directory_Controller.O_B_W.GETX 49 0.00% 0.00%
-system.ruby.Directory_Controller.O_B_W.GETS 101 0.00% 0.00%
-system.ruby.Directory_Controller.O_B_W.Memory_Data 16807 0.00% 0.00%
-system.ruby.Directory_Controller.WB.GETX 1378 0.00% 0.00%
-system.ruby.Directory_Controller.WB.GETS 2421 0.00% 0.00%
-system.ruby.Directory_Controller.WB.PUT 60 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Unblock 1451 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Clean 8050 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Dirty 1352 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 363228 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 219452 0.00% 0.00%
-system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1352 0.00% 0.00%
-system.ruby.Directory_Controller.WB_E_W.GETX 34 0.00% 0.00%
-system.ruby.Directory_Controller.WB_E_W.GETS 79 0.00% 0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack 219452 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50971 12.54% 12.54% | 50665 12.46% 25.00% | 50845 12.50% 37.50% | 50743 12.48% 49.98% | 50754 12.48% 62.46% | 50895 12.52% 74.98% | 51016 12.55% 87.52% | 50730 12.48% 100.00%
-system.ruby.L1Cache_Controller.Load::total 406619
-system.ruby.L1Cache_Controller.Store | 27735 12.39% 12.39% | 28186 12.59% 24.99% | 28157 12.58% 37.57% | 27944 12.49% 50.05% | 27882 12.46% 62.51% | 28029 12.52% 75.03% | 27949 12.49% 87.52% | 27925 12.48% 100.00%
-system.ruby.L1Cache_Controller.Store::total 223807
-system.ruby.L1Cache_Controller.L2_Replacement | 77360 12.48% 12.48% | 77497 12.51% 24.99% | 77632 12.53% 37.52% | 77372 12.49% 50.01% | 77315 12.48% 62.48% | 77607 12.52% 75.01% | 77589 12.52% 87.53% | 77281 12.47% 100.00%
-system.ruby.L1Cache_Controller.L2_Replacement::total 619653
-system.ruby.L1Cache_Controller.L1_to_L2 | 1262689 12.50% 12.50% | 1264010 12.51% 25.01% | 1265832 12.53% 37.54% | 1258023 12.45% 50.00% | 1260220 12.48% 62.47% | 1264438 12.52% 74.99% | 1265548 12.53% 87.52% | 1260958 12.48% 100.00%
-system.ruby.L1Cache_Controller.L1_to_L2::total 10101718
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 73 13.20% 13.20% | 67 12.12% 25.32% | 70 12.66% 37.97% | 65 11.75% 49.73% | 55 9.95% 59.67% | 67 12.12% 71.79% | 71 12.84% 84.63% | 85 15.37% 100.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 553
-system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 73 13.20% 13.20% | 67 12.12% 25.32% | 70 12.66% 37.97% | 65 11.75% 49.73% | 55 9.95% 59.67% | 67 12.12% 71.79% | 71 12.84% 84.63% | 85 15.37% 100.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 553
-system.ruby.L1Cache_Controller.Other_GETX | 195724 12.52% 12.52% | 195274 12.49% 25.00% | 195314 12.49% 37.49% | 195506 12.50% 49.99% | 195571 12.51% 62.50% | 195421 12.50% 74.99% | 195515 12.50% 87.50% | 195545 12.50% 100.00%
-system.ruby.L1Cache_Controller.Other_GETX::total 1563870
-system.ruby.L1Cache_Controller.Other_GETS | 354134 12.49% 12.49% | 354439 12.51% 25.00% | 354255 12.50% 37.50% | 354361 12.50% 50.00% | 354328 12.50% 62.50% | 354227 12.50% 75.00% | 354110 12.49% 87.50% | 354397 12.50% 100.00%
-system.ruby.L1Cache_Controller.Other_GETS::total 2834251
-system.ruby.L1Cache_Controller.Merged_GETS | 120 12.47% 12.47% | 125 12.99% 25.47% | 126 13.10% 38.57% | 100 10.40% 48.96% | 120 12.47% 61.43% | 112 11.64% 73.08% | 118 12.27% 85.34% | 141 14.66% 100.00%
-system.ruby.L1Cache_Controller.Merged_GETS::total 962
-system.ruby.L1Cache_Controller.Ack | 546565 12.48% 12.48% | 547738 12.51% 24.99% | 548718 12.53% 37.53% | 546605 12.48% 50.01% | 546312 12.48% 62.49% | 548045 12.52% 75.00% | 548316 12.52% 87.53% | 546087 12.47% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 4378386
-system.ruby.L1Cache_Controller.Shared_Ack | 51 13.14% 13.14% | 43 11.08% 24.23% | 44 11.34% 35.57% | 40 10.31% 45.88% | 46 11.86% 57.73% | 64 16.49% 74.23% | 56 14.43% 88.66% | 44 11.34% 100.00%
-system.ruby.L1Cache_Controller.Shared_Ack::total 388
-system.ruby.L1Cache_Controller.Data | 3541 12.82% 12.82% | 3379 12.23% 25.05% | 3493 12.65% 37.70% | 3551 12.86% 50.55% | 3408 12.34% 62.89% | 3461 12.53% 75.42% | 3404 12.32% 87.75% | 3385 12.25% 100.00%
-system.ruby.L1Cache_Controller.Data::total 27622
-system.ruby.L1Cache_Controller.Shared_Data | 1202 12.56% 12.56% | 1159 12.11% 24.68% | 1180 12.33% 37.01% | 1226 12.81% 49.83% | 1192 12.46% 62.29% | 1221 12.76% 75.05% | 1195 12.49% 87.54% | 1192 12.46% 100.00%
-system.ruby.L1Cache_Controller.Shared_Data::total 9567
-system.ruby.L1Cache_Controller.Exclusive_Data | 73822 12.47% 12.47% | 74163 12.53% 25.00% | 74175 12.53% 37.52% | 73785 12.46% 49.99% | 73919 12.49% 62.47% | 74093 12.51% 74.99% | 74207 12.53% 87.52% | 73893 12.48% 100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total 592057
-system.ruby.L1Cache_Controller.Writeback_Ack | 73979 12.46% 12.46% | 74303 12.52% 24.98% | 74390 12.53% 37.52% | 74010 12.47% 49.99% | 74101 12.48% 62.47% | 74354 12.53% 75.00% | 74372 12.53% 87.53% | 74026 12.47% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 593535
-system.ruby.L1Cache_Controller.All_acks | 1249 12.60% 12.60% | 1194 12.04% 24.64% | 1213 12.23% 36.87% | 1266 12.77% 49.64% | 1237 12.47% 62.11% | 1277 12.88% 74.99% | 1248 12.59% 87.58% | 1232 12.42% 100.00%
-system.ruby.L1Cache_Controller.All_acks::total 9916
-system.ruby.L1Cache_Controller.All_acks_no_sharers | 77316 12.48% 12.48% | 77507 12.51% 25.00% | 77635 12.54% 37.53% | 77297 12.48% 50.01% | 77282 12.48% 62.49% | 77499 12.51% 75.01% | 77559 12.52% 87.53% | 77238 12.47% 100.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers::total 619333
-system.ruby.L1Cache_Controller.I.Load | 50883 12.54% 12.54% | 50568 12.46% 25.00% | 50755 12.51% 37.50% | 50661 12.48% 49.98% | 50684 12.49% 62.47% | 50791 12.51% 74.99% | 50914 12.54% 87.53% | 50609 12.47% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 405865
-system.ruby.L1Cache_Controller.I.Store | 27682 12.39% 12.39% | 28135 12.59% 24.99% | 28094 12.58% 37.56% | 27901 12.49% 50.05% | 27835 12.46% 62.51% | 27986 12.53% 75.04% | 27895 12.49% 87.53% | 27863 12.47% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 223391
-system.ruby.L1Cache_Controller.I.Other_GETX | 194570 12.51% 12.51% | 194171 12.49% 25.00% | 194237 12.49% 37.49% | 194432 12.50% 49.99% | 194464 12.51% 62.50% | 194330 12.50% 75.00% | 194397 12.50% 87.50% | 194438 12.50% 100.00%
-system.ruby.L1Cache_Controller.I.Other_GETX::total 1555039
-system.ruby.L1Cache_Controller.I.Other_GETS | 352245 12.49% 12.49% | 352525 12.50% 25.00% | 352324 12.50% 37.50% | 352485 12.50% 50.00% | 352423 12.50% 62.50% | 352389 12.50% 75.00% | 352205 12.49% 87.49% | 352535 12.51% 100.00%
-system.ruby.L1Cache_Controller.I.Other_GETS::total 2819131
-system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 3
-system.ruby.L1Cache_Controller.S.Store | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 4
-system.ruby.L1Cache_Controller.S.L2_Replacement | 3379 12.94% 12.94% | 3194 12.23% 25.18% | 3240 12.41% 37.59% | 3362 12.88% 50.47% | 3212 12.30% 62.77% | 3250 12.45% 75.22% | 3216 12.32% 87.54% | 3253 12.46% 100.00%
-system.ruby.L1Cache_Controller.S.L2_Replacement::total 26106
-system.ruby.L1Cache_Controller.S.L1_to_L2 | 3414 12.95% 12.95% | 3228 12.24% 25.19% | 3282 12.45% 37.64% | 3389 12.85% 50.49% | 3250 12.33% 62.82% | 3282 12.45% 75.27% | 3240 12.29% 87.56% | 3280 12.44% 100.00%
-system.ruby.L1Cache_Controller.S.L1_to_L2::total 26365
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 8 25.00% 25.00% | 3 9.38% 34.38% | 3 9.38% 43.75% | 3 9.38% 53.12% | 5 15.62% 68.75% | 5 15.62% 84.38% | 1 3.12% 87.50% | 4 12.50% 100.00%
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 32
-system.ruby.L1Cache_Controller.S.Other_GETX | 29 11.79% 11.79% | 34 13.82% 25.61% | 38 15.45% 41.06% | 26 10.57% 51.63% | 34 13.82% 65.45% | 31 12.60% 78.05% | 28 11.38% 89.43% | 26 10.57% 100.00%
-system.ruby.L1Cache_Controller.S.Other_GETX::total 246
-system.ruby.L1Cache_Controller.S.Other_GETS | 61 15.72% 15.72% | 40 10.31% 26.03% | 51 13.14% 39.18% | 45 11.60% 50.77% | 54 13.92% 64.69% | 49 12.63% 77.32% | 38 9.79% 87.11% | 50 12.89% 100.00%
-system.ruby.L1Cache_Controller.S.Other_GETS::total 388
-system.ruby.L1Cache_Controller.O.L2_Replacement | 837 12.41% 12.41% | 884 13.10% 25.51% | 862 12.78% 38.29% | 816 12.10% 50.39% | 866 12.84% 63.22% | 809 11.99% 75.21% | 832 12.33% 87.55% | 840 12.45% 100.00%
-system.ruby.L1Cache_Controller.O.L2_Replacement::total 6746
-system.ruby.L1Cache_Controller.O.L1_to_L2 | 69 12.97% 12.97% | 78 14.66% 27.63% | 53 9.96% 37.59% | 54 10.15% 47.74% | 78 14.66% 62.41% | 61 11.47% 73.87% | 61 11.47% 85.34% | 78 14.66% 100.00%
-system.ruby.L1Cache_Controller.O.L1_to_L2::total 532
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 2 20.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00%
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 10
-system.ruby.L1Cache_Controller.O.Other_GETX | 7 15.91% 15.91% | 5 11.36% 27.27% | 7 15.91% 43.18% | 5 11.36% 54.55% | 4 9.09% 63.64% | 7 15.91% 79.55% | 3 6.82% 86.36% | 6 13.64% 100.00%
-system.ruby.L1Cache_Controller.O.Other_GETX::total 44
-system.ruby.L1Cache_Controller.O.Other_GETS | 2 5.00% 5.00% | 6 15.00% 20.00% | 5 12.50% 32.50% | 6 15.00% 47.50% | 5 12.50% 60.00% | 3 7.50% 67.50% | 7 17.50% 85.00% | 6 15.00% 100.00%
-system.ruby.L1Cache_Controller.O.Other_GETS::total 40
-system.ruby.L1Cache_Controller.O.Merged_GETS | 3 17.65% 17.65% | 0 0.00% 17.65% | 4 23.53% 41.18% | 3 17.65% 58.82% | 2 11.76% 70.59% | 3 17.65% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
-system.ruby.L1Cache_Controller.O.Merged_GETS::total 17
-system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 3 13.04% 13.04% | 2 8.70% 21.74% | 1 4.35% 26.09% | 8 34.78% 60.87% | 2 8.70% 69.57% | 4 17.39% 86.96% | 3 13.04% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 23
-system.ruby.L1Cache_Controller.M.Store | 2 15.38% 15.38% | 1 7.69% 23.08% | 1 7.69% 30.77% | 0 0.00% 30.77% | 2 15.38% 46.15% | 3 23.08% 69.23% | 2 15.38% 84.62% | 2 15.38% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 13
-system.ruby.L1Cache_Controller.M.L2_Replacement | 46198 12.51% 12.51% | 46006 12.46% 24.97% | 46208 12.51% 37.49% | 46008 12.46% 49.95% | 46151 12.50% 62.44% | 46263 12.53% 74.97% | 46379 12.56% 87.53% | 46030 12.47% 100.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement::total 369243
-system.ruby.L1Cache_Controller.M.L1_to_L2 | 47396 12.51% 12.51% | 47252 12.47% 24.98% | 47404 12.51% 37.49% | 47224 12.46% 49.95% | 47339 12.49% 62.44% | 47445 12.52% 74.96% | 47605 12.56% 87.53% | 47263 12.47% 100.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2::total 378928
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 35 10.61% 10.61% | 38 11.52% 22.12% | 40 12.12% 34.24% | 44 13.33% 47.58% | 31 9.39% 56.97% | 38 11.52% 68.48% | 48 14.55% 83.03% | 56 16.97% 100.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 330
-system.ruby.L1Cache_Controller.M.Other_GETX | 454 12.65% 12.65% | 458 12.76% 25.40% | 407 11.34% 36.74% | 451 12.56% 49.30% | 431 12.01% 61.31% | 444 12.37% 73.68% | 464 12.92% 86.60% | 481 13.40% 100.00%
-system.ruby.L1Cache_Controller.M.Other_GETX::total 3590
-system.ruby.L1Cache_Controller.M.Other_GETS | 746 12.47% 12.47% | 778 13.00% 25.47% | 761 12.72% 38.19% | 742 12.40% 50.59% | 769 12.85% 63.45% | 723 12.08% 75.53% | 736 12.30% 87.83% | 728 12.17% 100.00%
-system.ruby.L1Cache_Controller.M.Other_GETS::total 5983
-system.ruby.L1Cache_Controller.M.Merged_GETS | 54 10.87% 10.87% | 71 14.29% 25.15% | 74 14.89% 40.04% | 51 10.26% 50.30% | 56 11.27% 61.57% | 59 11.87% 73.44% | 64 12.88% 86.32% | 68 13.68% 100.00%
-system.ruby.L1Cache_Controller.M.Merged_GETS::total 497
-system.ruby.L1Cache_Controller.MM.Load | 1 4.76% 4.76% | 2 9.52% 14.29% | 5 23.81% 38.10% | 2 9.52% 47.62% | 4 19.05% 66.67% | 1 4.76% 71.43% | 3 14.29% 85.71% | 3 14.29% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 21
-system.ruby.L1Cache_Controller.MM.Store | 2 22.22% 22.22% | 1 11.11% 33.33% | 2 22.22% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 9
-system.ruby.L1Cache_Controller.MM.L2_Replacement | 26946 12.39% 12.39% | 27413 12.60% 24.99% | 27322 12.56% 37.54% | 27186 12.50% 50.04% | 27086 12.45% 62.49% | 27285 12.54% 75.03% | 27162 12.48% 87.52% | 27158 12.48% 100.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217558
-system.ruby.L1Cache_Controller.MM.L1_to_L2 | 27649 12.39% 12.39% | 28125 12.60% 24.98% | 28083 12.58% 37.56% | 27887 12.49% 50.06% | 27807 12.46% 62.51% | 27967 12.53% 75.04% | 27876 12.49% 87.53% | 27839 12.47% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223233
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 28 15.47% 15.47% | 25 13.81% 29.28% | 26 14.36% 43.65% | 16 8.84% 52.49% | 18 9.94% 62.43% | 23 12.71% 75.14% | 21 11.60% 86.74% | 24 13.26% 100.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 181
-system.ruby.L1Cache_Controller.MM.Other_GETX | 281 13.30% 13.30% | 260 12.31% 25.62% | 282 13.35% 38.97% | 254 12.03% 50.99% | 275 13.02% 64.02% | 260 12.31% 76.33% | 264 12.50% 88.83% | 236 11.17% 100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETX::total 2112
-system.ruby.L1Cache_Controller.MM.Other_GETS | 424 12.01% 12.01% | 438 12.40% 24.41% | 473 13.40% 37.81% | 444 12.57% 50.38% | 450 12.74% 63.13% | 418 11.84% 74.96% | 452 12.80% 87.77% | 432 12.23% 100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETS::total 3531
-system.ruby.L1Cache_Controller.MM.Merged_GETS | 45 14.33% 14.33% | 40 12.74% 27.07% | 34 10.83% 37.90% | 29 9.24% 47.13% | 45 14.33% 61.46% | 35 11.15% 72.61% | 36 11.46% 84.08% | 50 15.92% 100.00%
-system.ruby.L1Cache_Controller.MM.Merged_GETS::total 314
-system.ruby.L1Cache_Controller.SR.Load | 5 27.78% 27.78% | 2 11.11% 38.89% | 1 5.56% 44.44% | 1 5.56% 50.00% | 2 11.11% 61.11% | 3 16.67% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00%
-system.ruby.L1Cache_Controller.SR.Load::total 18
-system.ruby.L1Cache_Controller.SR.Store | 3 21.43% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 2 14.29% 57.14% | 3 21.43% 78.57% | 2 14.29% 92.86% | 0 0.00% 92.86% | 1 7.14% 100.00%
-system.ruby.L1Cache_Controller.SR.Store::total 14
-system.ruby.L1Cache_Controller.SR.L1_to_L2 | 1 14.29% 14.29% | 0 0.00% 14.29% | 3 42.86% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SR.L1_to_L2::total 7
-system.ruby.L1Cache_Controller.OR.Load | 2 28.57% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00%
-system.ruby.L1Cache_Controller.OR.Load::total 7
-system.ruby.L1Cache_Controller.OR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OR.Store::total 3
-system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OR.L1_to_L2::total 2
-system.ruby.L1Cache_Controller.MR.Load | 25 11.16% 11.16% | 20 8.93% 20.09% | 25 11.16% 31.25% | 32 14.29% 45.54% | 16 7.14% 52.68% | 31 13.84% 66.52% | 32 14.29% 80.80% | 43 19.20% 100.00%
-system.ruby.L1Cache_Controller.MR.Load::total 224
-system.ruby.L1Cache_Controller.MR.Store | 10 9.43% 9.43% | 18 16.98% 26.42% | 15 14.15% 40.57% | 12 11.32% 51.89% | 15 14.15% 66.04% | 7 6.60% 72.64% | 16 15.09% 87.74% | 13 12.26% 100.00%
-system.ruby.L1Cache_Controller.MR.Store::total 106
-system.ruby.L1Cache_Controller.MR.L1_to_L2 | 11 50.00% 50.00% | 0 0.00% 50.00% | 2 9.09% 59.09% | 3 13.64% 72.73% | 0 0.00% 72.73% | 1 4.55% 77.27% | 5 22.73% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2::total 22
-system.ruby.L1Cache_Controller.MMR.Load | 16 14.29% 14.29% | 20 17.86% 32.14% | 17 15.18% 47.32% | 8 7.14% 54.46% | 13 11.61% 66.07% | 12 10.71% 76.79% | 14 12.50% 89.29% | 12 10.71% 100.00%
-system.ruby.L1Cache_Controller.MMR.Load::total 112
-system.ruby.L1Cache_Controller.MMR.Store | 12 17.39% 17.39% | 5 7.25% 24.64% | 9 13.04% 37.68% | 8 11.59% 49.28% | 5 7.25% 56.52% | 11 15.94% 72.46% | 7 10.14% 82.61% | 12 17.39% 100.00%
-system.ruby.L1Cache_Controller.MMR.Store::total 69
-system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 0 0.00% 0.00% | 1 16.67% 16.67% | 0 0.00% 16.67% | 2 33.33% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 6
-system.ruby.L1Cache_Controller.IM.L1_to_L2 | 302923 12.45% 12.45% | 307239 12.63% 25.09% | 307083 12.63% 37.71% | 302980 12.46% 50.17% | 301277 12.39% 62.56% | 306307 12.59% 75.15% | 302955 12.46% 87.61% | 301458 12.39% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2432222
-system.ruby.L1Cache_Controller.IM.Other_GETX | 70 14.40% 14.40% | 57 11.73% 26.13% | 62 12.76% 38.89% | 59 12.14% 51.03% | 62 12.76% 63.79% | 50 10.29% 74.07% | 67 13.79% 87.86% | 59 12.14% 100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETX::total 486
-system.ruby.L1Cache_Controller.IM.Other_GETS | 132 14.54% 14.54% | 115 12.67% 27.20% | 112 12.33% 39.54% | 109 12.00% 51.54% | 117 12.89% 64.43% | 110 12.11% 76.54% | 115 12.67% 89.21% | 98 10.79% 100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETS::total 908
-system.ruby.L1Cache_Controller.IM.Ack | 134226 12.37% 12.37% | 136054 12.54% 24.91% | 136885 12.62% 37.53% | 135510 12.49% 50.02% | 135173 12.46% 62.47% | 136621 12.59% 75.06% | 135127 12.45% 87.52% | 135424 12.48% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 1085020
-system.ruby.L1Cache_Controller.IM.Data | 1327 12.29% 12.29% | 1308 12.11% 24.40% | 1387 12.84% 37.25% | 1384 12.82% 50.06% | 1346 12.47% 62.53% | 1397 12.94% 75.47% | 1355 12.55% 88.02% | 1294 11.98% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 10798
-system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26355 12.40% 12.40% | 26825 12.62% 25.02% | 26706 12.56% 37.58% | 26516 12.47% 50.05% | 26488 12.46% 62.51% | 26588 12.51% 75.02% | 26538 12.48% 87.50% | 26568 12.50% 100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 212584
-system.ruby.L1Cache_Controller.SM.L1_to_L2 | 40 32.79% 32.79% | 8 6.56% 39.34% | 11 9.02% 48.36% | 10 8.20% 56.56% | 10 8.20% 64.75% | 12 9.84% 74.59% | 0 0.00% 74.59% | 31 25.41% 100.00%
-system.ruby.L1Cache_Controller.SM.L1_to_L2::total 122
-system.ruby.L1Cache_Controller.SM.Ack | 9 11.84% 11.84% | 7 9.21% 21.05% | 11 14.47% 35.53% | 14 18.42% 53.95% | 21 27.63% 81.58% | 14 18.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 76
-system.ruby.L1Cache_Controller.SM.Data | 4 22.22% 22.22% | 1 5.56% 27.78% | 3 16.67% 44.44% | 2 11.11% 55.56% | 4 22.22% 77.78% | 2 11.11% 88.89% | 0 0.00% 88.89% | 2 11.11% 100.00%
-system.ruby.L1Cache_Controller.SM.Data::total 18
-system.ruby.L1Cache_Controller.OM.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OM.L1_to_L2::total 10
-system.ruby.L1Cache_Controller.OM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 33.33% 33.33% | 0 0.00% 33.33% | 7 33.33% 66.67% | 7 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total 21
-system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 3
-system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1405 11.94% 11.94% | 1364 11.59% 23.53% | 1489 12.65% 36.18% | 1604 13.63% 49.80% | 1332 11.32% 61.12% | 1603 13.62% 74.74% | 1519 12.91% 87.65% | 1454 12.35% 100.00%
-system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11770
-system.ruby.L1Cache_Controller.ISM.Ack | 2799 12.37% 12.37% | 2747 12.14% 24.51% | 2955 13.06% 37.57% | 2944 13.01% 50.58% | 2774 12.26% 62.84% | 2765 12.22% 75.05% | 2793 12.34% 87.40% | 2852 12.60% 100.00%
-system.ruby.L1Cache_Controller.ISM.Ack::total 22629
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1331 12.31% 12.31% | 1309 12.10% 24.41% | 1390 12.85% 37.26% | 1386 12.81% 50.07% | 1350 12.48% 62.56% | 1399 12.93% 75.49% | 1355 12.53% 88.02% | 1296 11.98% 100.00%
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10816
-system.ruby.L1Cache_Controller.M_W.Load | 2 8.70% 8.70% | 2 8.70% 17.39% | 1 4.35% 21.74% | 2 8.70% 30.43% | 1 4.35% 34.78% | 8 34.78% 69.57% | 3 13.04% 82.61% | 4 17.39% 100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total 23
-system.ruby.L1Cache_Controller.M_W.Store | 1 7.69% 7.69% | 2 15.38% 23.08% | 2 15.38% 38.46% | 1 7.69% 46.15% | 1 7.69% 53.85% | 2 15.38% 69.23% | 4 30.77% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total 13
-system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 201445 12.59% 12.59% | 199880 12.49% 25.07% | 199351 12.45% 37.53% | 199459 12.46% 49.99% | 199708 12.48% 62.47% | 199635 12.47% 74.94% | 200784 12.54% 87.48% | 200348 12.52% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 1600610
-system.ruby.L1Cache_Controller.M_W.Ack | 99436 12.49% 12.49% | 98487 12.37% 24.86% | 99684 12.52% 37.39% | 98522 12.38% 49.76% | 100457 12.62% 62.38% | 99804 12.54% 74.92% | 99953 12.56% 87.48% | 99670 12.52% 100.00%
-system.ruby.L1Cache_Controller.M_W.Ack::total 796013
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47466 12.51% 12.51% | 47336 12.47% 24.98% | 47467 12.51% 37.49% | 47268 12.46% 49.95% | 47430 12.50% 62.45% | 47503 12.52% 74.97% | 47665 12.56% 87.53% | 47325 12.47% 100.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 379460
-system.ruby.L1Cache_Controller.MM_W.Load | 2 16.67% 16.67% | 2 16.67% 33.33% | 1 8.33% 41.67% | 2 16.67% 58.33% | 2 16.67% 75.00% | 0 0.00% 75.00% | 3 25.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 12
-system.ruby.L1Cache_Controller.MM_W.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 25.00% 25.00% | 3 37.50% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total 8
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 110034 12.43% 12.43% | 112800 12.74% 25.18% | 110873 12.53% 37.70% | 109927 12.42% 50.12% | 110569 12.49% 62.61% | 109742 12.40% 75.01% | 110682 12.50% 87.52% | 110478 12.48% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 885105
-system.ruby.L1Cache_Controller.MM_W.Ack | 55850 12.44% 12.44% | 57296 12.76% 25.20% | 55937 12.46% 37.66% | 55962 12.46% 50.12% | 55976 12.47% 62.59% | 55627 12.39% 74.98% | 56487 12.58% 87.56% | 55876 12.44% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Ack::total 449011
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26356 12.40% 12.40% | 26827 12.62% 25.02% | 26708 12.56% 37.58% | 26517 12.47% 50.05% | 26489 12.46% 62.51% | 26590 12.51% 75.02% | 26542 12.48% 87.50% | 26568 12.50% 100.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 212597
-system.ruby.L1Cache_Controller.IS.L1_to_L2 | 556503 12.51% 12.51% | 552231 12.42% 24.93% | 556440 12.51% 37.44% | 553059 12.44% 49.88% | 556823 12.52% 62.40% | 556311 12.51% 74.91% | 558973 12.57% 87.48% | 556691 12.52% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4447031
-system.ruby.L1Cache_Controller.IS.Other_GETX | 125 13.90% 13.90% | 103 11.46% 25.36% | 99 11.01% 36.37% | 116 12.90% 49.28% | 118 13.13% 62.40% | 113 12.57% 74.97% | 112 12.46% 87.43% | 113 12.57% 100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETX::total 899
-system.ruby.L1Cache_Controller.IS.Other_GETS | 233 13.80% 13.80% | 185 10.96% 24.76% | 207 12.26% 37.03% | 218 12.91% 49.94% | 201 11.91% 61.85% | 212 12.56% 74.41% | 214 12.68% 87.09% | 218 12.91% 100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETS::total 1688
-system.ruby.L1Cache_Controller.IS.Ack | 246873 12.55% 12.55% | 245877 12.50% 25.05% | 246145 12.51% 37.56% | 246067 12.51% 50.07% | 244793 12.44% 62.51% | 245889 12.50% 75.01% | 246666 12.54% 87.55% | 244851 12.45% 100.00%
-system.ruby.L1Cache_Controller.IS.Ack::total 1967161
-system.ruby.L1Cache_Controller.IS.Shared_Ack | 43 15.09% 15.09% | 30 10.53% 25.61% | 29 10.18% 35.79% | 29 10.18% 45.96% | 31 10.88% 56.84% | 44 15.44% 72.28% | 42 14.74% 87.02% | 37 12.98% 100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Ack::total 285
-system.ruby.L1Cache_Controller.IS.Data | 2210 13.15% 13.15% | 2070 12.32% 25.47% | 2103 12.51% 37.98% | 2165 12.88% 50.86% | 2058 12.25% 63.11% | 2062 12.27% 75.38% | 2049 12.19% 87.57% | 2089 12.43% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 16806
-system.ruby.L1Cache_Controller.IS.Shared_Data | 1202 12.56% 12.56% | 1159 12.11% 24.68% | 1180 12.33% 37.01% | 1226 12.81% 49.83% | 1192 12.46% 62.29% | 1221 12.76% 75.05% | 1195 12.49% 87.54% | 1192 12.46% 100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Data::total 9567
-system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47467 12.51% 12.51% | 47338 12.47% 24.98% | 47469 12.51% 37.49% | 47269 12.46% 49.95% | 47431 12.50% 62.45% | 47505 12.52% 74.97% | 47669 12.56% 87.53% | 47325 12.47% 100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 379473
-system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SS.Load::total 1
-system.ruby.L1Cache_Controller.SS.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00%
-system.ruby.L1Cache_Controller.SS.Store::total 3
-system.ruby.L1Cache_Controller.SS.L1_to_L2 | 11768 12.31% 12.31% | 11790 12.33% 24.64% | 11742 12.28% 36.92% | 12395 12.96% 49.88% | 12008 12.56% 62.44% | 12055 12.61% 75.05% | 11824 12.37% 87.41% | 12035 12.59% 100.00%
-system.ruby.L1Cache_Controller.SS.L1_to_L2::total 95617
-system.ruby.L1Cache_Controller.SS.Ack | 7372 12.61% 12.61% | 7270 12.44% 25.05% | 7101 12.15% 37.20% | 7579 12.97% 50.16% | 7118 12.18% 62.34% | 7318 12.52% 74.86% | 7283 12.46% 87.32% | 7414 12.68% 100.00%
-system.ruby.L1Cache_Controller.SS.Ack::total 58455
-system.ruby.L1Cache_Controller.SS.Shared_Ack | 8 7.77% 7.77% | 13 12.62% 20.39% | 15 14.56% 34.95% | 11 10.68% 45.63% | 15 14.56% 60.19% | 20 19.42% 79.61% | 14 13.59% 93.20% | 7 6.80% 100.00%
-system.ruby.L1Cache_Controller.SS.Shared_Ack::total 103
-system.ruby.L1Cache_Controller.SS.All_acks | 1249 12.60% 12.60% | 1194 12.04% 24.64% | 1213 12.23% 36.87% | 1266 12.77% 49.64% | 1237 12.47% 62.11% | 1277 12.88% 74.99% | 1248 12.59% 87.58% | 1232 12.42% 100.00%
-system.ruby.L1Cache_Controller.SS.All_acks::total 9916
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2163 13.14% 13.14% | 2035 12.37% 25.51% | 2070 12.58% 38.09% | 2125 12.91% 51.00% | 2013 12.23% 63.23% | 2006 12.19% 75.42% | 1996 12.13% 87.55% | 2049 12.45% 100.00%
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16457
-system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Load::total 2
-system.ruby.L1Cache_Controller.OI.Store | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Store::total 4
-system.ruby.L1Cache_Controller.OI.Other_GETX | 2 10.53% 10.53% | 1 5.26% 15.79% | 1 5.26% 21.05% | 5 26.32% 47.37% | 3 15.79% 63.16% | 3 15.79% 78.95% | 1 5.26% 84.21% | 3 15.79% 100.00%
-system.ruby.L1Cache_Controller.OI.Other_GETX::total 19
-system.ruby.L1Cache_Controller.OI.Other_GETS | 1 5.56% 5.56% | 2 11.11% 16.67% | 2 11.11% 27.78% | 3 16.67% 44.44% | 3 16.67% 61.11% | 1 5.56% 66.67% | 4 22.22% 88.89% | 2 11.11% 100.00%
-system.ruby.L1Cache_Controller.OI.Other_GETS::total 18
-system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 18.18% 18.18% | 2 9.09% 27.27% | 2 9.09% 36.36% | 2 9.09% 45.45% | 2 9.09% 54.55% | 1 4.55% 59.09% | 6 27.27% 86.36% | 3 13.64% 100.00%
-system.ruby.L1Cache_Controller.OI.Merged_GETS::total 22
-system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1139 12.11% 12.11% | 1245 13.24% 25.36% | 1193 12.69% 38.05% | 1135 12.07% 50.12% | 1183 12.58% 62.70% | 1142 12.15% 74.85% | 1181 12.56% 87.41% | 1184 12.59% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9402
-system.ruby.L1Cache_Controller.MI.Load | 13 10.16% 10.16% | 19 14.84% 25.00% | 13 10.16% 35.16% | 15 11.72% 46.88% | 13 10.16% 57.03% | 21 16.41% 73.44% | 20 15.62% 89.06% | 14 10.94% 100.00%
-system.ruby.L1Cache_Controller.MI.Load::total 128
-system.ruby.L1Cache_Controller.MI.Store | 11 14.10% 14.10% | 11 14.10% 28.21% | 9 11.54% 39.74% | 6 7.69% 47.44% | 8 10.26% 57.69% | 8 10.26% 67.95% | 8 10.26% 78.21% | 17 21.79% 100.00%
-system.ruby.L1Cache_Controller.MI.Store::total 78
-system.ruby.L1Cache_Controller.MI.Other_GETX | 186 12.99% 12.99% | 184 12.85% 25.84% | 179 12.50% 38.34% | 158 11.03% 49.37% | 180 12.57% 61.94% | 183 12.78% 74.72% | 179 12.50% 87.22% | 183 12.78% 100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETX::total 1432
-system.ruby.L1Cache_Controller.MI.Other_GETS | 290 11.31% 11.31% | 350 13.65% 24.96% | 320 12.48% 37.44% | 309 12.05% 49.49% | 306 11.93% 61.43% | 322 12.56% 73.99% | 339 13.22% 87.21% | 328 12.79% 100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETS::total 2564
-system.ruby.L1Cache_Controller.MI.Merged_GETS | 14 12.50% 12.50% | 12 10.71% 23.21% | 12 10.71% 33.93% | 15 13.39% 47.32% | 15 13.39% 60.71% | 14 12.50% 73.21% | 11 9.82% 83.04% | 19 16.96% 100.00%
-system.ruby.L1Cache_Controller.MI.Merged_GETS::total 112
-system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72652 12.47% 12.47% | 72873 12.51% 24.98% | 73017 12.53% 37.51% | 72712 12.48% 49.99% | 72735 12.48% 62.47% | 73026 12.53% 75.00% | 73011 12.53% 87.53% | 72656 12.47% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 582682
-system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.II.Store::total 1
-system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.II.Other_GETX::total 3
-system.ruby.L1Cache_Controller.II.Writeback_Ack | 188 12.96% 12.96% | 185 12.75% 25.71% | 180 12.41% 38.11% | 163 11.23% 49.35% | 183 12.61% 61.96% | 186 12.82% 74.78% | 180 12.41% 87.18% | 186 12.82% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1451
-system.ruby.L1Cache_Controller.ST.Load | 2 22.22% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 0 0.00% 44.44% | 1 11.11% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00%
-system.ruby.L1Cache_Controller.ST.Load::total 9
-system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 1 20.00% 60.00% | 2 40.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.ST.Store::total 5
-system.ruby.L1Cache_Controller.ST.L1_to_L2 | 1 8.33% 8.33% | 0 0.00% 8.33% | 7 58.33% 66.67% | 1 8.33% 75.00% | 1 8.33% 83.33% | 2 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.ST.L1_to_L2::total 12
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 8 25.00% 25.00% | 3 9.38% 34.38% | 3 9.38% 43.75% | 3 9.38% 53.12% | 5 15.62% 68.75% | 5 15.62% 84.38% | 1 3.12% 87.50% | 4 12.50% 100.00%
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 32
-system.ruby.L1Cache_Controller.OT.Load | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OT.Load::total 2
-system.ruby.L1Cache_Controller.OT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OT.Store::total 2
-system.ruby.L1Cache_Controller.OT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OT.L1_to_L2::total 6
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 2 20.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00%
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 10
-system.ruby.L1Cache_Controller.MT.Load | 12 10.00% 10.00% | 10 8.33% 18.33% | 16 13.33% 31.67% | 16 13.33% 45.00% | 5 4.17% 49.17% | 17 14.17% 63.33% | 17 14.17% 77.50% | 27 22.50% 100.00%
-system.ruby.L1Cache_Controller.MT.Load::total 120
-system.ruby.L1Cache_Controller.MT.Store | 2 3.92% 3.92% | 7 13.73% 17.65% | 13 25.49% 43.14% | 4 7.84% 50.98% | 6 11.76% 62.75% | 3 5.88% 68.63% | 10 19.61% 88.24% | 6 11.76% 100.00%
-system.ruby.L1Cache_Controller.MT.Store::total 51
-system.ruby.L1Cache_Controller.MT.L1_to_L2 | 18 23.68% 23.68% | 11 14.47% 38.16% | 7 9.21% 47.37% | 9 11.84% 59.21% | 13 17.11% 76.32% | 6 7.89% 84.21% | 10 13.16% 97.37% | 2 2.63% 100.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2::total 76
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 35 10.61% 10.61% | 38 11.52% 22.12% | 40 12.12% 34.24% | 44 13.33% 47.58% | 31 9.39% 56.97% | 38 11.52% 68.48% | 48 14.55% 83.03% | 56 16.97% 100.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 330
-system.ruby.L1Cache_Controller.MMT.Load | 7 14.29% 14.29% | 12 24.49% 38.78% | 4 8.16% 46.94% | 2 4.08% 51.02% | 4 8.16% 59.18% | 6 12.24% 71.43% | 5 10.20% 81.63% | 9 18.37% 100.00%
-system.ruby.L1Cache_Controller.MMT.Load::total 49
-system.ruby.L1Cache_Controller.MMT.Store | 9 27.27% 27.27% | 3 9.09% 36.36% | 5 15.15% 51.52% | 2 6.06% 57.58% | 2 6.06% 63.64% | 4 12.12% 75.76% | 3 9.09% 84.85% | 5 15.15% 100.00%
-system.ruby.L1Cache_Controller.MMT.Store::total 33
-system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 12 28.57% 28.57% | 3 7.14% 35.71% | 2 4.76% 40.48% | 2 4.76% 45.24% | 4 9.52% 54.76% | 4 9.52% 64.29% | 14 33.33% 97.62% | 1 2.38% 100.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 42
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 28 15.47% 15.47% | 25 13.81% 29.28% | 26 14.36% 43.65% | 16 8.84% 52.49% | 18 9.94% 62.43% | 23 12.71% 75.14% | 21 11.60% 86.74% | 24 13.26% 100.00%
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 181
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu1]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu2]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl2.sequencer.slave[0]
-
-[system.cpu3]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl3.sequencer.slave[0]
-
-[system.cpu4]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl4.sequencer.slave[0]
-
-[system.cpu5]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl5.sequencer.slave[0]
-
-[system.cpu6]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl6.sequencer.slave[0]
-
-[system.cpu7]
-type=MemTest
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-interval=1
-max_loads=100000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=0
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=true
-system=system
-port=system.ruby.l1_cntrl7.sequencer.slave[0]
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:268435455
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=8
-number_of_virtual_networks=5
-phys_mem=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=12
-dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
-dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-number_of_TBEs=256
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[17]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[17]
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[18]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[16]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[16]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
-buffer_size=0
-cacheMemory=system.ruby.l1_cntrl0.cacheMemory
-cache_response_latency=12
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl0.forwardToCache
-issue_latency=2
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl0.requestFromCache
-responseFromCache=system.ruby.l1_cntrl0.responseFromCache
-responseToCache=system.ruby.l1_cntrl0.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l1_cntrl0.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.requestFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.responseFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.cpu_clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.cacheMemory
-dcache_hit_latency=1
-deadlock_threshold=1000000
-eventq_index=0
-icache=system.ruby.l1_cntrl0.cacheMemory
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.cpu0.port
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
-buffer_size=0
-cacheMemory=system.ruby.l1_cntrl1.cacheMemory
-cache_response_latency=12
-clk_domain=system.cpu_clk_domain
-cluster_id=0
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl1.forwardToCache
-issue_latency=2
-mandatoryQueue=system.ruby.l1_cntrl1.mandatoryQueue
-number_of_TBEs=256
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl1.requestFromCache
-responseFromCache=system.ruby.l1_cntrl1.responseFromCache
-responseToCache=system.ruby.l1_cntrl1.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-version=1
-
-[system.ruby.l1_cntrl1.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl1.cacheMemory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl1.forwardToCache]
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-[system.ruby.l1_cntrl1.mandatoryQueue]
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-
-[system.ruby.l1_cntrl1.requestFromCache]
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-
-[system.ruby.l1_cntrl1.responseFromCache]
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-[system.ruby.l1_cntrl1.responseToCache]
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-
-[system.ruby.l1_cntrl1.sequencer]
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-
-[system.ruby.l1_cntrl2]
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-
-[system.ruby.l1_cntrl2.cacheMemory]
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-
-[system.ruby.l1_cntrl2.cacheMemory.replacement_policy]
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-
-[system.ruby.l1_cntrl2.forwardToCache]
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-[system.ruby.l1_cntrl2.mandatoryQueue]
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-[system.ruby.l1_cntrl2.requestFromCache]
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-
-[system.ruby.l1_cntrl2.responseFromCache]
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-
-[system.ruby.l1_cntrl2.responseToCache]
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-
-[system.ruby.l1_cntrl2.sequencer]
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-
-[system.ruby.l1_cntrl3]
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-
-[system.ruby.l1_cntrl3.cacheMemory]
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-
-[system.ruby.l1_cntrl3.cacheMemory.replacement_policy]
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-
-[system.ruby.l1_cntrl3.forwardToCache]
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-
-[system.ruby.l1_cntrl3.mandatoryQueue]
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-[system.ruby.l1_cntrl3.requestFromCache]
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-
-[system.ruby.l1_cntrl3.responseFromCache]
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-
-[system.ruby.l1_cntrl3.responseToCache]
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-
-[system.ruby.l1_cntrl3.sequencer]
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-[system.ruby.l1_cntrl4]
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-
-[system.ruby.l1_cntrl4.cacheMemory]
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-
-[system.ruby.l1_cntrl4.cacheMemory.replacement_policy]
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-
-[system.ruby.l1_cntrl4.forwardToCache]
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-[system.ruby.l1_cntrl4.mandatoryQueue]
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-[system.ruby.l1_cntrl4.requestFromCache]
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-
-[system.ruby.l1_cntrl4.responseFromCache]
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-[system.ruby.l1_cntrl4.responseToCache]
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-[system.ruby.l1_cntrl4.sequencer]
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-[system.ruby.l1_cntrl5]
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-[system.ruby.l1_cntrl5.cacheMemory]
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-
-[system.ruby.l1_cntrl5.cacheMemory.replacement_policy]
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-[system.ruby.l1_cntrl5.forwardToCache]
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-[system.ruby.l1_cntrl5.mandatoryQueue]
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-[system.ruby.l1_cntrl5.responseFromCache]
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-[system.ruby.l1_cntrl5.responseToCache]
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-[system.ruby.l1_cntrl5.sequencer]
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-
-[system.ruby.l1_cntrl6]
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-
-[system.ruby.l1_cntrl6.cacheMemory]
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-
-[system.ruby.l1_cntrl6.cacheMemory.replacement_policy]
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-
-[system.ruby.l1_cntrl6.forwardToCache]
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-[system.ruby.l1_cntrl6.mandatoryQueue]
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-[system.ruby.l1_cntrl6.requestFromCache]
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-[system.ruby.l1_cntrl6.responseFromCache]
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-[system.ruby.l1_cntrl6.responseToCache]
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-[system.ruby.l1_cntrl6.sequencer]
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-
-[system.ruby.l1_cntrl7]
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-
-[system.ruby.l1_cntrl7.cacheMemory]
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-
-[system.ruby.l1_cntrl7.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.ruby.l1_cntrl7.forwardToCache]
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-
-[system.ruby.l1_cntrl7.mandatoryQueue]
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-
-[system.ruby.l1_cntrl7.requestFromCache]
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-
-[system.ruby.l1_cntrl7.responseFromCache]
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-
-[system.ruby.l1_cntrl7.responseToCache]
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-
-[system.ruby.l1_cntrl7.sequencer]
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-
-[system.ruby.memctrl_clk_domain]
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-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_link_buffers80 int_link_buffers81 int_link_buffers82 int_link_buffers83 int_link_buffers84 int_link_buffers85 int_link_buffers86 int_link_buffers87 int_link_buffers88 int_link_buffers89 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79 system.ruby.network.int_link_buffers80 system.ruby.network.int_link_buffers81 system.ruby.network.int_link_buffers82 system.ruby.network.int_link_buffers83 system.ruby.network.int_link_buffers84 system.ruby.network.int_link_buffers85 system.ruby.network.int_link_buffers86 system.ruby.network.int_link_buffers87 system.ruby.network.int_link_buffers88 system.ruby.network.int_link_buffers89
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8
-netifs=
-number_of_virtual_networks=5
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5 system.ruby.network.routers6 system.ruby.network.routers7 system.ruby.network.routers8 system.ruby.network.routers9
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.l1_cntrl1.forwardToCache.slave system.ruby.l1_cntrl1.responseToCache.slave system.ruby.l1_cntrl2.forwardToCache.slave system.ruby.l1_cntrl2.responseToCache.slave system.ruby.l1_cntrl3.forwardToCache.slave system.ruby.l1_cntrl3.responseToCache.slave system.ruby.l1_cntrl4.forwardToCache.slave system.ruby.l1_cntrl4.responseToCache.slave system.ruby.l1_cntrl5.forwardToCache.slave system.ruby.l1_cntrl5.responseToCache.slave system.ruby.l1_cntrl6.forwardToCache.slave system.ruby.l1_cntrl6.responseToCache.slave system.ruby.l1_cntrl7.forwardToCache.slave system.ruby.l1_cntrl7.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl1.requestFromCache.master system.ruby.l1_cntrl1.responseFromCache.master system.ruby.l1_cntrl2.requestFromCache.master system.ruby.l1_cntrl2.responseFromCache.master system.ruby.l1_cntrl3.requestFromCache.master system.ruby.l1_cntrl3.responseFromCache.master system.ruby.l1_cntrl4.requestFromCache.master system.ruby.l1_cntrl4.responseFromCache.master system.ruby.l1_cntrl5.requestFromCache.master system.ruby.l1_cntrl5.responseFromCache.master system.ruby.l1_cntrl6.requestFromCache.master system.ruby.l1_cntrl6.responseFromCache.master system.ruby.l1_cntrl7.requestFromCache.master system.ruby.l1_cntrl7.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl1
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl2
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.ext_links3]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl3
-int_node=system.ruby.network.routers3
-latency=1
-link_id=3
-weight=1
-
-[system.ruby.network.ext_links4]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl4
-int_node=system.ruby.network.routers4
-latency=1
-link_id=4
-weight=1
-
-[system.ruby.network.ext_links5]
-type=SimpleExtLink
-bandwidth_factor=16
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-int_node=system.ruby.network.routers5
-latency=1
-link_id=5
-weight=1
-
-[system.ruby.network.ext_links6]
-type=SimpleExtLink
-bandwidth_factor=16
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-int_node=system.ruby.network.routers6
-latency=1
-link_id=6
-weight=1
-
-[system.ruby.network.ext_links7]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
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-int_node=system.ruby.network.routers7
-latency=1
-link_id=7
-weight=1
-
-[system.ruby.network.ext_links8]
-type=SimpleExtLink
-bandwidth_factor=16
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-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers8
-latency=1
-link_id=8
-weight=1
-
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers25]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers36]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers37]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers38]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers39]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers40]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers41]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers42]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers43]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers44]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers45]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers46]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers47]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers48]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers49]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers50]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers51]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers52]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers53]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers54]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers55]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers56]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers57]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers58]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers59]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers60]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers61]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers62]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers63]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers64]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers65]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers66]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers67]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers68]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers69]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers70]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers71]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers72]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers73]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers74]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers75]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers76]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers77]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers78]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers79]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers80]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers81]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers82]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers83]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers84]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers85]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers86]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers87]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers88]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers9.port_buffers89]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-system.cpu0: completed 10000 read, 5571 write accesses @752421
-system.cpu5: completed 10000 read, 5518 write accesses @761420
-system.cpu4: completed 10000 read, 5515 write accesses @761995
-system.cpu1: completed 10000 read, 5545 write accesses @770340
-system.cpu7: completed 10000 read, 5536 write accesses @773657
-system.cpu3: completed 10000 read, 5634 write accesses @778030
-system.cpu6: completed 10000 read, 5641 write accesses @782742
-system.cpu2: completed 10000 read, 5665 write accesses @783711
-system.cpu4: completed 20000 read, 10969 write accesses @1519216
-system.cpu1: completed 20000 read, 11064 write accesses @1534419
-system.cpu0: completed 20000 read, 11217 write accesses @1534668
-system.cpu5: completed 20000 read, 11140 write accesses @1535434
-system.cpu3: completed 20000 read, 11134 write accesses @1543210
-system.cpu7: completed 20000 read, 11062 write accesses @1544582
-system.cpu2: completed 20000 read, 11296 write accesses @1546737
-system.cpu6: completed 20000 read, 11124 write accesses @1559617
-system.cpu4: completed 30000 read, 16555 write accesses @2275552
-system.cpu0: completed 30000 read, 16802 write accesses @2300818
-system.cpu1: completed 30000 read, 16697 write accesses @2303774
-system.cpu7: completed 30000 read, 16517 write accesses @2305690
-system.cpu3: completed 30000 read, 16547 write accesses @2312240
-system.cpu2: completed 30000 read, 16835 write accesses @2313552
-system.cpu5: completed 30000 read, 16782 write accesses @2322286
-system.cpu6: completed 30000 read, 16591 write accesses @2331245
-system.cpu4: completed 40000 read, 22197 write accesses @3047291
-system.cpu1: completed 40000 read, 22254 write accesses @3080372
-system.cpu5: completed 40000 read, 22355 write accesses @3084185
-system.cpu2: completed 40000 read, 22372 write accesses @3086032
-system.cpu3: completed 40000 read, 22166 write accesses @3086541
-system.cpu7: completed 40000 read, 22080 write accesses @3086779
-system.cpu0: completed 40000 read, 22498 write accesses @3087817
-system.cpu6: completed 40000 read, 22224 write accesses @3104629
-system.cpu4: completed 50000 read, 27651 write accesses @3808654
-system.cpu3: completed 50000 read, 27619 write accesses @3840689
-system.cpu2: completed 50000 read, 27948 write accesses @3842577
-system.cpu5: completed 50000 read, 27826 write accesses @3846119
-system.cpu1: completed 50000 read, 27919 write accesses @3856612
-system.cpu0: completed 50000 read, 27967 write accesses @3862756
-system.cpu7: completed 50000 read, 27662 write accesses @3864061
-system.cpu6: completed 50000 read, 27847 write accesses @3874888
-system.cpu4: completed 60000 read, 33289 write accesses @4579441
-system.cpu5: completed 60000 read, 33335 write accesses @4610406
-system.cpu2: completed 60000 read, 33617 write accesses @4620490
-system.cpu3: completed 60000 read, 33206 write accesses @4625510
-system.cpu0: completed 60000 read, 33552 write accesses @4626939
-system.cpu1: completed 60000 read, 33496 write accesses @4630810
-system.cpu7: completed 60000 read, 33243 write accesses @4635014
-system.cpu6: completed 60000 read, 33291 write accesses @4642013
-system.cpu4: completed 70000 read, 39076 write accesses @5364272
-system.cpu5: completed 70000 read, 38991 write accesses @5366681
-system.cpu2: completed 70000 read, 39149 write accesses @5384888
-system.cpu7: completed 70000 read, 38759 write accesses @5402266
-system.cpu0: completed 70000 read, 39059 write accesses @5403051
-system.cpu3: completed 70000 read, 38849 write accesses @5406812
-system.cpu1: completed 70000 read, 39130 write accesses @5408848
-system.cpu6: completed 70000 read, 38893 write accesses @5418265
-system.cpu5: completed 80000 read, 44444 write accesses @6131768
-system.cpu4: completed 80000 read, 44664 write accesses @6143607
-system.cpu2: completed 80000 read, 44926 write accesses @6155809
-system.cpu7: completed 80000 read, 44252 write accesses @6163509
-system.cpu0: completed 80000 read, 44649 write accesses @6169693
-system.cpu1: completed 80000 read, 44753 write accesses @6180727
-system.cpu3: completed 80000 read, 44403 write accesses @6182843
-system.cpu6: completed 80000 read, 44456 write accesses @6189312
-system.cpu5: completed 90000 read, 50182 write accesses @6910395
-system.cpu7: completed 90000 read, 49674 write accesses @6913652
-system.cpu2: completed 90000 read, 50514 write accesses @6919272
-system.cpu0: completed 90000 read, 50099 write accesses @6923145
-system.cpu4: completed 90000 read, 50279 write accesses @6924731
-system.cpu1: completed 90000 read, 50283 write accesses @6951674
-system.cpu3: completed 90000 read, 50165 write accesses @6956300
-system.cpu6: completed 90000 read, 50051 write accesses @6959913
-system.cpu5: completed 100000 read, 55705 write accesses @7678882
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:03
-gem5 executing on zizzer, pid 34009
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 7678882 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.007679 # Number of seconds simulated
-sim_ticks 7678882 # Number of ticks simulated
-final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 172641 # Simulator tick rate (ticks/s)
-host_mem_usage 467856 # Number of bytes of host memory used
-host_seconds 44.48 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39687936 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39686592 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 39686592 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 620124 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 620124 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 620103 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 620103 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 5168452387 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 5168452387 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 5168277361 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 5168277361 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 10336729748 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 10336729748 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 620135 # Number of read requests accepted
-system.mem_ctrls.writeReqs 620103 # Number of write requests accepted
-system.mem_ctrls.readBursts 620135 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 620103 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 38814144 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 874432 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 39178240 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39688640 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 39686592 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 13663 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 7899 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 76107 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 76000 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 75939 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 75805 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 75453 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 75733 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 75604 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 75830 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 76774 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 76710 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 76671 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 76539 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 76175 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 76456 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 76301 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 76534 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 1460 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 7678686 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 620135 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 620103 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 19 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 184 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 983 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 3255 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 7746 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 15554 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 26175 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 37685 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 47133 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 52357 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 54286 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 51593 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 44542 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 37610 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 32124 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 28105 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 25786 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 24080 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 22962 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 21687 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 19844 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 17181 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 13705 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 9888 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 6282 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 3447 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 1554 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 523 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 143 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 35 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 4 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 18 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 122 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 330 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 810 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 1760 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 3235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 5017 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 8822 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 11772 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 14646 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 17978 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 20446 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 22363 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 23166 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 24550 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 25656 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 26802 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 28849 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 30890 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 32798 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 34545 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 37340 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 41995 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 65965 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 58297 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 24690 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 18242 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 13049 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 8033 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 4660 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 2636 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 2690 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 246538 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 316.347760 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 240.406220 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 226.949392 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 34759 14.10% 14.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 76086 30.86% 44.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 46939 19.04% 64.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 34923 14.17% 78.17% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 24196 9.81% 87.98% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 14479 5.87% 93.85% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 7763 3.15% 97.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3969 1.61% 98.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 3424 1.39% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 246538 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 38260 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.850732 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 8.293167 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 11.882732 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-3 13623 35.61% 35.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::4-7 1256 3.28% 38.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-11 278 0.73% 39.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-15 163 0.43% 40.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-19 3078 8.04% 48.09% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-23 6049 15.81% 63.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-27 5774 15.09% 78.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::28-31 6360 16.62% 95.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-35 1623 4.24% 99.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-39 55 0.14% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 38260 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 38260 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 38260 100.00% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 38260 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 114599292 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 126122241 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3032355 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 188.96 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 207.96 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 5054.66 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 5102.08 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 5168.54 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 5168.28 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 79.35 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 39.49 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 39.86 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 18.26 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 53.74 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 369343 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 602743 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 60.90 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 98.45 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 6.19 # Average gap between requests
-system.mem_ctrls.pageHitRate 79.77 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1863396360 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1035220200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7566948480 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 6345547776 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 501440160 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 5232384540 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 16562400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 22561499916 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2938.732659 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 10 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 256360 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 7420933 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 501440160 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 165908304 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 4460811600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 5128160064 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.969052 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 7420896 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 256360 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99754 # number of read accesses completed
-system.cpu0.num_writes 55550 # number of write accesses completed
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 99722 # number of read accesses completed
-system.cpu1.num_writes 55422 # number of write accesses completed
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 99859 # number of read accesses completed
-system.cpu2.num_writes 56114 # number of write accesses completed
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 99399 # number of read accesses completed
-system.cpu3.num_writes 55238 # number of write accesses completed
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 99564 # number of read accesses completed
-system.cpu4.num_writes 55685 # number of write accesses completed
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 100000 # number of read accesses completed
-system.cpu5.num_writes 55705 # number of write accesses completed
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 99381 # number of read accesses completed
-system.cpu6.num_writes 55293 # number of write accesses completed
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 99930 # number of read accesses completed
-system.cpu7.num_writes 55169 # number of write accesses completed
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 32 # delay histogram for all message
-system.ruby.delayHist::max_bucket 319 # delay histogram for all message
-system.ruby.delayHist::samples 1260795 # delay histogram for all message
-system.ruby.delayHist::mean 2.261395 # delay histogram for all message
-system.ruby.delayHist::stdev 7.584807 # delay histogram for all message
-system.ruby.delayHist | 1243450 98.62% 98.62% | 11474 0.91% 99.53% | 5225 0.41% 99.95% | 542 0.04% 99.99% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 1260795 # delay histogram for all message
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 628584
-system.ruby.outstanding_req_hist_seqr::mean 15.998449
-system.ruby.outstanding_req_hist_seqr::gmean 15.997188
-system.ruby.outstanding_req_hist_seqr::stdev 0.125710
-system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 628449 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 628584
-system.ruby.latency_hist_seqr::bucket_size 512
-system.ruby.latency_hist_seqr::max_bucket 5119
-system.ruby.latency_hist_seqr::samples 628456
-system.ruby.latency_hist_seqr::mean 1563.811233
-system.ruby.latency_hist_seqr::gmean 1541.792365
-system.ruby.latency_hist_seqr::stdev 262.265559
-system.ruby.latency_hist_seqr | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 628456
-system.ruby.miss_latency_hist_seqr::bucket_size 512
-system.ruby.miss_latency_hist_seqr::max_bucket 5119
-system.ruby.miss_latency_hist_seqr::samples 628456
-system.ruby.miss_latency_hist_seqr::mean 1563.811233
-system.ruby.miss_latency_hist_seqr::gmean 1541.792365
-system.ruby.miss_latency_hist_seqr::stdev 262.265559
-system.ruby.miss_latency_hist_seqr | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 628456
-system.ruby.L1Cache.incomplete_times_seqr 8337
-system.ruby.Directory.incomplete_times_seqr 620116
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 78526 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78526 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.cacheMemory.demand_misses 78474 # Number of cache demand misses
-system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78474 # Number of cache demand accesses
-system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.cacheMemory.demand_misses 78844 # Number of cache demand misses
-system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78844 # Number of cache demand accesses
-system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.cacheMemory.demand_misses 78573 # Number of cache demand misses
-system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78573 # Number of cache demand accesses
-system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.cacheMemory.demand_misses 78575 # Number of cache demand misses
-system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78575 # Number of cache demand accesses
-system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.cacheMemory.demand_misses 78529 # Number of cache demand misses
-system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78529 # Number of cache demand accesses
-system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.cacheMemory.demand_misses 78440 # Number of cache demand misses
-system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78440 # Number of cache demand accesses
-system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.cacheMemory.demand_misses 78515 # Number of cache demand misses
-system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78515 # Number of cache demand accesses
-system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 5.128100
-system.ruby.network.routers0.msg_count.Control::2 78526
-system.ruby.network.routers0.msg_count.Data::2 77981
-system.ruby.network.routers0.msg_count.Response_Data::4 79531
-system.ruby.network.routers0.msg_count.Writeback_Control::3 78989
-system.ruby.network.routers0.msg_bytes.Control::2 628208
-system.ruby.network.routers0.msg_bytes.Data::2 5614632
-system.ruby.network.routers0.msg_bytes.Response_Data::4 5726232
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 631912
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 5.125007
-system.ruby.network.routers1.msg_count.Control::2 78474
-system.ruby.network.routers1.msg_count.Data::2 77933
-system.ruby.network.routers1.msg_count.Response_Data::4 79484
-system.ruby.network.routers1.msg_count.Writeback_Control::3 78946
-system.ruby.network.routers1.msg_bytes.Control::2 627792
-system.ruby.network.routers1.msg_bytes.Data::2 5611176
-system.ruby.network.routers1.msg_bytes.Response_Data::4 5722848
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 631568
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 5.149581
-system.ruby.network.routers2.msg_count.Control::2 78844
-system.ruby.network.routers2.msg_count.Data::2 78287
-system.ruby.network.routers2.msg_count.Response_Data::4 79885
-system.ruby.network.routers2.msg_count.Writeback_Control::3 79329
-system.ruby.network.routers2.msg_bytes.Control::2 630752
-system.ruby.network.routers2.msg_bytes.Data::2 5636664
-system.ruby.network.routers2.msg_bytes.Response_Data::4 5751720
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634632
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 5.132918
-system.ruby.network.routers3.msg_count.Control::2 78573
-system.ruby.network.routers3.msg_count.Data::2 78015
-system.ruby.network.routers3.msg_count.Response_Data::4 79645
-system.ruby.network.routers3.msg_count.Writeback_Control::3 79090
-system.ruby.network.routers3.msg_bytes.Control::2 628584
-system.ruby.network.routers3.msg_bytes.Data::2 5617080
-system.ruby.network.routers3.msg_bytes.Response_Data::4 5734440
-system.ruby.network.routers3.msg_bytes.Writeback_Control::3 632720
-system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers4.percent_links_utilized 5.131284
-system.ruby.network.routers4.msg_count.Control::2 78575
-system.ruby.network.routers4.msg_count.Data::2 78023
-system.ruby.network.routers4.msg_count.Response_Data::4 79587
-system.ruby.network.routers4.msg_count.Writeback_Control::3 79036
-system.ruby.network.routers4.msg_bytes.Control::2 628600
-system.ruby.network.routers4.msg_bytes.Data::2 5617656
-system.ruby.network.routers4.msg_bytes.Response_Data::4 5730264
-system.ruby.network.routers4.msg_bytes.Writeback_Control::3 632288
-system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers5.percent_links_utilized 5.129285
-system.ruby.network.routers5.msg_count.Control::2 78525
-system.ruby.network.routers5.msg_count.Data::2 77953
-system.ruby.network.routers5.msg_count.Response_Data::4 79596
-system.ruby.network.routers5.msg_count.Writeback_Control::3 79024
-system.ruby.network.routers5.msg_bytes.Control::2 628200
-system.ruby.network.routers5.msg_bytes.Data::2 5612616
-system.ruby.network.routers5.msg_bytes.Response_Data::4 5730912
-system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632192
-system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers6.percent_links_utilized 5.123636
-system.ruby.network.routers6.msg_count.Control::2 78440
-system.ruby.network.routers6.msg_count.Data::2 77859
-system.ruby.network.routers6.msg_count.Response_Data::4 79516
-system.ruby.network.routers6.msg_count.Writeback_Control::3 78937
-system.ruby.network.routers6.msg_bytes.Control::2 627520
-system.ruby.network.routers6.msg_bytes.Data::2 5605848
-system.ruby.network.routers6.msg_bytes.Response_Data::4 5725152
-system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631496
-system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers7.percent_links_utilized 5.127709
-system.ruby.network.routers7.msg_count.Control::2 78515
-system.ruby.network.routers7.msg_count.Data::2 77951
-system.ruby.network.routers7.msg_count.Response_Data::4 79549
-system.ruby.network.routers7.msg_count.Writeback_Control::3 78988
-system.ruby.network.routers7.msg_bytes.Control::2 628120
-system.ruby.network.routers7.msg_bytes.Data::2 5612472
-system.ruby.network.routers7.msg_bytes.Response_Data::4 5727528
-system.ruby.network.routers7.msg_bytes.Writeback_Control::3 631904
-system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers8.percent_links_utilized 40.558977
-system.ruby.network.routers8.msg_count.Control::2 628472
-system.ruby.network.routers8.msg_count.Data::2 624002
-system.ruby.network.routers8.msg_count.Response_Data::4 620120
-system.ruby.network.routers8.msg_count.Writeback_Control::3 632339
-system.ruby.network.routers8.msg_bytes.Control::2 5027776
-system.ruby.network.routers8.msg_bytes.Data::2 44928144
-system.ruby.network.routers8.msg_bytes.Response_Data::4 44648640
-system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5058712
-system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers9.percent_links_utilized 9.067388
-system.ruby.network.routers9.msg_count.Control::2 628472
-system.ruby.network.routers9.msg_count.Data::2 624002
-system.ruby.network.routers9.msg_count.Response_Data::4 628456
-system.ruby.network.routers9.msg_count.Writeback_Control::3 632339
-system.ruby.network.routers9.msg_bytes.Control::2 5027776
-system.ruby.network.routers9.msg_bytes.Data::2 44928144
-system.ruby.network.routers9.msg_bytes.Response_Data::4 45248832
-system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5058712
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 1885416
-system.ruby.network.msg_count.Data 1872006
-system.ruby.network.msg_count.Response_Data 1885369
-system.ruby.network.msg_count.Writeback_Control 1897017
-system.ruby.network.msg_byte.Control 15083328
-system.ruby.network.msg_byte.Data 134784432
-system.ruby.network.msg_byte.Response_Data 135746568
-system.ruby.network.msg_byte.Writeback_Control 15176136
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 5.115953
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78523
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78989
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5653656
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 631912
-system.ruby.network.routers0.throttle1.link_utilization 5.140247
-system.ruby.network.routers0.throttle1.msg_count.Control::2 78526
-system.ruby.network.routers0.throttle1.msg_count.Data::2 77981
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1008
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 628208
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5614632
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 72576
-system.ruby.network.routers1.throttle0.link_utilization 5.112626
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78471
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 78946
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5649912
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 631568
-system.ruby.network.routers1.throttle1.link_utilization 5.137388
-system.ruby.network.routers1.throttle1.msg_count.Control::2 78474
-system.ruby.network.routers1.throttle1.msg_count.Data::2 77933
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1013
-system.ruby.network.routers1.throttle1.msg_bytes.Control::2 627792
-system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5611176
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 72936
-system.ruby.network.routers2.throttle0.link_utilization 5.136920
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78843
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79329
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5676696
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634632
-system.ruby.network.routers2.throttle1.link_utilization 5.162242
-system.ruby.network.routers2.throttle1.msg_count.Control::2 78844
-system.ruby.network.routers2.throttle1.msg_count.Data::2 78287
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1042
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 630752
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5636664
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 75024
-system.ruby.network.routers3.throttle0.link_utilization 5.119365
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78570
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 79090
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5657040
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 632720
-system.ruby.network.routers3.throttle1.link_utilization 5.146472
-system.ruby.network.routers3.throttle1.msg_count.Control::2 78573
-system.ruby.network.routers3.throttle1.msg_count.Data::2 78015
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1075
-system.ruby.network.routers3.throttle1.msg_bytes.Control::2 628584
-system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5617080
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 77400
-system.ruby.network.routers4.throttle0.link_utilization 5.119248
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78574
-system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79036
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5657328
-system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 632288
-system.ruby.network.routers4.throttle1.link_utilization 5.143320
-system.ruby.network.routers4.throttle1.msg_count.Control::2 78575
-system.ruby.network.routers4.throttle1.msg_count.Data::2 78023
-system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1013
-system.ruby.network.routers4.throttle1.msg_bytes.Control::2 628600
-system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5617656
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 72936
-system.ruby.network.routers5.throttle0.link_utilization 5.116279
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78525
-system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79024
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5653800
-system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632192
-system.ruby.network.routers5.throttle1.link_utilization 5.142292
-system.ruby.network.routers5.throttle1.msg_count.Control::2 78525
-system.ruby.network.routers5.throttle1.msg_count.Data::2 77953
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1071
-system.ruby.network.routers5.throttle1.msg_bytes.Control::2 628200
-system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5612616
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 77112
-system.ruby.network.routers6.throttle0.link_utilization 5.110633
-system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78438
-system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78937
-system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5647536
-system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631496
-system.ruby.network.routers6.throttle1.link_utilization 5.136640
-system.ruby.network.routers6.throttle1.msg_count.Control::2 78440
-system.ruby.network.routers6.throttle1.msg_count.Data::2 77859
-system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1078
-system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627520
-system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5605848
-system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 77616
-system.ruby.network.routers7.throttle0.link_utilization 5.115302
-system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78512
-system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78988
-system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5652864
-system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 631904
-system.ruby.network.routers7.throttle1.link_utilization 5.140117
-system.ruby.network.routers7.throttle1.msg_count.Control::2 78515
-system.ruby.network.routers7.throttle1.msg_count.Data::2 77951
-system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1037
-system.ruby.network.routers7.throttle1.msg_bytes.Control::2 628120
-system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5612472
-system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 74664
-system.ruby.network.routers8.throttle0.link_utilization 40.660151
-system.ruby.network.routers8.throttle0.msg_count.Control::2 628472
-system.ruby.network.routers8.throttle0.msg_count.Data::2 624002
-system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5027776
-system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44928144
-system.ruby.network.routers8.throttle1.link_utilization 40.457804
-system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 620120
-system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 632339
-system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44648640
-system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5058712
-system.ruby.network.routers9.throttle0.link_utilization 5.115953
-system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78523
-system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78989
-system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5653656
-system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 631912
-system.ruby.network.routers9.throttle1.link_utilization 5.112626
-system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78471
-system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78946
-system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5649912
-system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 631568
-system.ruby.network.routers9.throttle2.link_utilization 5.136920
-system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78843
-system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79329
-system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5676696
-system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 634632
-system.ruby.network.routers9.throttle3.link_utilization 5.119365
-system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78570
-system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 79090
-system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5657040
-system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 632720
-system.ruby.network.routers9.throttle4.link_utilization 5.119248
-system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78574
-system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79036
-system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5657328
-system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 632288
-system.ruby.network.routers9.throttle5.link_utilization 5.116298
-system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78525
-system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79024
-system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5653800
-system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632192
-system.ruby.network.routers9.throttle6.link_utilization 5.110633
-system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78438
-system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78937
-system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5647536
-system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631496
-system.ruby.network.routers9.throttle7.link_utilization 5.115302
-system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78512
-system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78988
-system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5652864
-system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 631904
-system.ruby.network.routers9.throttle8.link_utilization 40.660151
-system.ruby.network.routers9.throttle8.msg_count.Control::2 628472
-system.ruby.network.routers9.throttle8.msg_count.Data::2 624002
-system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5027776
-system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44928144
-system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 628456 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.270507 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 1.327302 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 602976 95.95% 95.95% | 18460 2.94% 98.88% | 5975 0.95% 99.83% | 853 0.14% 99.97% | 168 0.03% 100.00% | 23 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 628456 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 632339 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 4.240058 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 10.251834 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 614994 97.26% 97.26% | 11474 1.81% 99.07% | 5225 0.83% 99.90% | 542 0.09% 99.98% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 632339 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 512
-system.ruby.LD.latency_hist_seqr::max_bucket 5119
-system.ruby.LD.latency_hist_seqr::samples 404420
-system.ruby.LD.latency_hist_seqr::mean 1563.542728
-system.ruby.LD.latency_hist_seqr::gmean 1541.515221
-system.ruby.LD.latency_hist_seqr::stdev 262.248075
-system.ruby.LD.latency_hist_seqr | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 404420
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 512
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 5119
-system.ruby.LD.miss_latency_hist_seqr::samples 404420
-system.ruby.LD.miss_latency_hist_seqr::mean 1563.542728
-system.ruby.LD.miss_latency_hist_seqr::gmean 1541.515221
-system.ruby.LD.miss_latency_hist_seqr::stdev 262.248075
-system.ruby.LD.miss_latency_hist_seqr | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 404420
-system.ruby.ST.latency_hist_seqr::bucket_size 512
-system.ruby.ST.latency_hist_seqr::max_bucket 5119
-system.ruby.ST.latency_hist_seqr::samples 224036
-system.ruby.ST.latency_hist_seqr::mean 1564.295926
-system.ruby.ST.latency_hist_seqr::gmean 1542.292779
-system.ruby.ST.latency_hist_seqr::stdev 262.297007
-system.ruby.ST.latency_hist_seqr | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 224036
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 512
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.miss_latency_hist_seqr::samples 224036
-system.ruby.ST.miss_latency_hist_seqr::mean 1564.295926
-system.ruby.ST.miss_latency_hist_seqr::gmean 1542.292779
-system.ruby.ST.miss_latency_hist_seqr::stdev 262.297007
-system.ruby.ST.miss_latency_hist_seqr | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 224036
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 8337
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1457.519731
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 1434.160972
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 261.316891
-system.ruby.L1Cache.miss_mach_latency_hist_seqr | 1 0.01% 0.01% | 260 3.12% 3.13% | 5041 60.47% 63.60% | 2865 34.36% 97.96% | 168 2.02% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 8337
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 512
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 620119
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 1565.240236
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 1543.293101
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 261.984881
-system.ruby.Directory.miss_mach_latency_hist_seqr | 76 0.01% 0.01% | 5844 0.94% 0.95% | 293021 47.25% 48.21% | 294571 47.50% 95.71% | 26418 4.26% 99.97% | 189 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 620119
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 3
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 3
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 3
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 3
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 80
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 79.895697
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev 5
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 3
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 256
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 2559
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 5455
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 1456.778185
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1433.055554
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::stdev 263.122030
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 1 0.02% 0.02% | 6 0.11% 0.13% | 171 3.13% 3.26% | 1270 23.28% 26.54% | 2035 37.31% 63.85% | 1383 25.35% 89.20% | 473 8.67% 97.87% | 103 1.89% 99.76% | 13 0.24% 100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 5455
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 398965
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1565.002506
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 1543.053698
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 261.935038
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 48 0.01% 0.01% | 3704 0.93% 0.94% | 188763 47.31% 48.25% | 189451 47.49% 95.74% | 16872 4.23% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 398965
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 2882
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1458.923317
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1436.255624
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 257.905109
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 2.88% 2.88% | 1736 60.24% 63.12% | 1009 35.01% 98.13% | 52 1.80% 99.93% | 2 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 2882
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 221154
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1565.669104
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 1543.725080
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 262.074821
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 28 0.01% 0.01% | 2140 0.97% 0.98% | 104258 47.14% 48.12% | 105120 47.53% 95.66% | 9546 4.32% 99.97% | 62 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 221154
-system.ruby.Directory_Controller.GETX 695129 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 620103 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX_NotOwner 3899 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 620120 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 620103 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 620135 0.00% 0.00%
-system.ruby.Directory_Controller.M.GETX 8337 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 620103 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX_NotOwner 3899 0.00% 0.00%
-system.ruby.Directory_Controller.IM.GETX 66370 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 620120 0.00% 0.00%
-system.ruby.Directory_Controller.MI.GETX 287 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 620103 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50377 12.46% 12.46% | 50576 12.51% 24.96% | 50610 12.51% 37.48% | 50632 12.52% 49.99% | 50644 12.52% 62.52% | 50559 12.50% 75.02% | 50404 12.46% 87.48% | 50629 12.52% 100.00%
-system.ruby.L1Cache_Controller.Load::total 404431
-system.ruby.L1Cache_Controller.Store | 28149 12.56% 12.56% | 27898 12.45% 25.02% | 28234 12.60% 37.62% | 27941 12.47% 50.09% | 27931 12.47% 62.56% | 27970 12.48% 75.04% | 28036 12.51% 87.55% | 27886 12.45% 100.00%
-system.ruby.L1Cache_Controller.Store::total 224045
-system.ruby.L1Cache_Controller.Data | 78523 12.49% 12.49% | 78471 12.49% 24.98% | 78843 12.55% 37.53% | 78570 12.50% 50.03% | 78574 12.50% 62.53% | 78525 12.49% 75.03% | 78438 12.48% 87.51% | 78512 12.49% 100.00%
-system.ruby.L1Cache_Controller.Data::total 628456
-system.ruby.L1Cache_Controller.Fwd_GETX | 1008 12.09% 12.09% | 1013 12.15% 24.24% | 1042 12.50% 36.74% | 1075 12.89% 49.63% | 1013 12.15% 61.78% | 1071 12.85% 74.63% | 1078 12.93% 87.56% | 1037 12.44% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 8337
-system.ruby.L1Cache_Controller.Replacement | 78522 12.49% 12.49% | 78470 12.49% 24.98% | 78840 12.55% 37.53% | 78569 12.50% 50.03% | 78571 12.50% 62.53% | 78525 12.50% 75.03% | 78436 12.48% 87.51% | 78511 12.49% 100.00%
-system.ruby.L1Cache_Controller.Replacement::total 628444
-system.ruby.L1Cache_Controller.Writeback_Ack | 77514 12.50% 12.50% | 77457 12.49% 24.99% | 77798 12.55% 37.54% | 77494 12.50% 50.03% | 77558 12.51% 62.54% | 77450 12.49% 75.03% | 77358 12.48% 87.51% | 77474 12.49% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 620103
-system.ruby.L1Cache_Controller.Writeback_Nack | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total 3899
-system.ruby.L1Cache_Controller.I.Load | 50377 12.46% 12.46% | 50576 12.51% 24.96% | 50610 12.51% 37.48% | 50632 12.52% 49.99% | 50644 12.52% 62.52% | 50559 12.50% 75.02% | 50404 12.46% 87.48% | 50629 12.52% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 404431
-system.ruby.L1Cache_Controller.I.Store | 28149 12.56% 12.56% | 27898 12.45% 25.02% | 28234 12.60% 37.62% | 27941 12.47% 50.09% | 27931 12.47% 62.56% | 27970 12.48% 75.04% | 28036 12.51% 87.55% | 27886 12.45% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 224045
-system.ruby.L1Cache_Controller.I.Replacement | 541 12.19% 12.19% | 537 12.10% 24.29% | 553 12.46% 36.75% | 554 12.48% 49.23% | 548 12.35% 61.58% | 568 12.80% 74.38% | 577 13.00% 87.38% | 560 12.62% 100.00%
-system.ruby.L1Cache_Controller.I.Replacement::total 4438
-system.ruby.L1Cache_Controller.II.Writeback_Nack | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3899
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 541 12.19% 12.19% | 537 12.10% 24.29% | 553 12.46% 36.75% | 554 12.48% 49.23% | 548 12.35% 61.58% | 568 12.80% 74.38% | 577 13.00% 87.38% | 560 12.62% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4438
-system.ruby.L1Cache_Controller.M.Replacement | 77981 12.50% 12.50% | 77933 12.49% 24.99% | 78287 12.55% 37.53% | 78015 12.50% 50.03% | 78023 12.50% 62.54% | 77957 12.49% 75.03% | 77859 12.48% 87.51% | 77951 12.49% 100.00%
-system.ruby.L1Cache_Controller.M.Replacement::total 624006
-system.ruby.L1Cache_Controller.MI.Fwd_GETX | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3899
-system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77514 12.50% 12.50% | 77457 12.49% 24.99% | 77798 12.55% 37.54% | 77494 12.50% 50.03% | 77558 12.51% 62.54% | 77450 12.49% 75.03% | 77358 12.48% 87.51% | 77474 12.49% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 620103
-system.ruby.L1Cache_Controller.IS.Data | 50375 12.46% 12.46% | 50575 12.51% 24.96% | 50609 12.51% 37.48% | 50632 12.52% 50.00% | 50643 12.52% 62.52% | 50556 12.50% 75.02% | 50402 12.46% 87.48% | 50628 12.52% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 404420
-system.ruby.L1Cache_Controller.IM.Data | 28148 12.56% 12.56% | 27896 12.45% 25.02% | 28234 12.60% 37.62% | 27938 12.47% 50.09% | 27931 12.47% 62.56% | 27969 12.48% 75.04% | 28036 12.51% 87.55% | 27884 12.45% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 224036
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu0.l1c.cpu_side
-
-[system.cpu0.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu1.l1c.cpu_side
-
-[system.cpu1.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu2]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu2.l1c.cpu_side
-
-[system.cpu2.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu2.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu2.port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu2.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu3]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu3.l1c.cpu_side
-
-[system.cpu3.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu3.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu3.port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu3.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu4]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu4.l1c.cpu_side
-
-[system.cpu4.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu4.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu4.port
-mem_side=system.toL2Bus.slave[4]
-
-[system.cpu4.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu5]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu5.l1c.cpu_side
-
-[system.cpu5.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu5.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu5.port
-mem_side=system.toL2Bus.slave[5]
-
-[system.cpu5.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu6]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu6.l1c.cpu_side
-
-[system.cpu6.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu6.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu6.port
-mem_side=system.toL2Bus.slave[6]
-
-[system.cpu6.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu7]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu7.l1c.cpu_side
-
-[system.cpu7.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu7.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu7.port
-mem_side=system.toL2Bus.slave[7]
-
-[system.cpu7.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=65536
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-system.cpu3: completed 10000 read, 5503 write accesses @55915500
-system.cpu4: completed 10000 read, 5302 write accesses @55980000
-system.cpu7: completed 10000 read, 5500 write accesses @56129000
-system.cpu2: completed 10000 read, 5342 write accesses @56146500
-system.cpu6: completed 10000 read, 5358 write accesses @56494500
-system.cpu0: completed 10000 read, 5493 write accesses @56861500
-system.cpu1: completed 10000 read, 5676 write accesses @57033500
-system.cpu5: completed 10000 read, 5528 write accesses @57497500
-system.cpu4: completed 20000 read, 10871 write accesses @105086000
-system.cpu7: completed 20000 read, 11018 write accesses @105227000
-system.cpu6: completed 20000 read, 10904 write accesses @105245500
-system.cpu0: completed 20000 read, 10841 write accesses @105416500
-system.cpu3: completed 20000 read, 11147 write accesses @105878500
-system.cpu2: completed 20000 read, 10930 write accesses @106485500
-system.cpu5: completed 20000 read, 10954 write accesses @106687000
-system.cpu1: completed 20000 read, 11324 write accesses @107095000
-system.cpu4: completed 30000 read, 16387 write accesses @154433500
-system.cpu6: completed 30000 read, 16529 write accesses @154891500
-system.cpu2: completed 30000 read, 16387 write accesses @154906000
-system.cpu3: completed 30000 read, 16756 write accesses @155604500
-system.cpu7: completed 30000 read, 16642 write accesses @155734000
-system.cpu5: completed 30000 read, 16445 write accesses @156039500
-system.cpu0: completed 30000 read, 16469 write accesses @156104500
-system.cpu1: completed 30000 read, 16825 write accesses @156708500
-system.cpu6: completed 40000 read, 21980 write accesses @203895500
-system.cpu4: completed 40000 read, 22029 write accesses @204285000
-system.cpu3: completed 40000 read, 22257 write accesses @204704000
-system.cpu7: completed 40000 read, 22193 write accesses @205001500
-system.cpu2: completed 40000 read, 22047 write accesses @205470000
-system.cpu5: completed 40000 read, 22004 write accesses @206055000
-system.cpu0: completed 40000 read, 21987 write accesses @206174000
-system.cpu1: completed 40000 read, 22532 write accesses @206732500
-system.cpu4: completed 50000 read, 27591 write accesses @253615500
-system.cpu6: completed 50000 read, 27369 write accesses @253616500
-system.cpu2: completed 50000 read, 27561 write accesses @254261500
-system.cpu7: completed 50000 read, 27945 write accesses @254398000
-system.cpu5: completed 50000 read, 27346 write accesses @254644500
-system.cpu3: completed 50000 read, 27794 write accesses @254687000
-system.cpu0: completed 50000 read, 27491 write accesses @255540000
-system.cpu1: completed 50000 read, 28147 write accesses @256393500
-system.cpu4: completed 60000 read, 33155 write accesses @302912000
-system.cpu6: completed 60000 read, 33024 write accesses @303044500
-system.cpu5: completed 60000 read, 32819 write accesses @303948500
-system.cpu7: completed 60000 read, 33412 write accesses @304003500
-system.cpu2: completed 60000 read, 33183 write accesses @305097000
-system.cpu3: completed 60000 read, 33603 write accesses @305311500
-system.cpu1: completed 60000 read, 33393 write accesses @305569000
-system.cpu0: completed 60000 read, 33038 write accesses @305621500
-system.cpu4: completed 70000 read, 38636 write accesses @352443000
-system.cpu5: completed 70000 read, 38516 write accesses @353701000
-system.cpu6: completed 70000 read, 38725 write accesses @353942000
-system.cpu7: completed 70000 read, 39072 write accesses @354424000
-system.cpu2: completed 70000 read, 38818 write accesses @354701000
-system.cpu1: completed 70000 read, 38717 write accesses @354858500
-system.cpu3: completed 70000 read, 39274 write accesses @355379500
-system.cpu0: completed 70000 read, 38744 write accesses @355617500
-system.cpu4: completed 80000 read, 44404 write accesses @402767500
-system.cpu2: completed 80000 read, 44188 write accesses @403291500
-system.cpu5: completed 80000 read, 44099 write accesses @403371500
-system.cpu7: completed 80000 read, 44629 write accesses @403854500
-system.cpu6: completed 80000 read, 44307 write accesses @404062000
-system.cpu0: completed 80000 read, 44206 write accesses @404147000
-system.cpu1: completed 80000 read, 44256 write accesses @404649000
-system.cpu3: completed 80000 read, 44966 write accesses @406154000
-system.cpu4: completed 90000 read, 49951 write accesses @452283500
-system.cpu5: completed 90000 read, 49582 write accesses @452363500
-system.cpu2: completed 90000 read, 49727 write accesses @452365500
-system.cpu6: completed 90000 read, 49789 write accesses @453642000
-system.cpu0: completed 90000 read, 49883 write accesses @453665500
-system.cpu7: completed 90000 read, 50370 write accesses @454276500
-system.cpu1: completed 90000 read, 49817 write accesses @454621500
-system.cpu3: completed 90000 read, 50461 write accesses @455559000
-system.cpu5: completed 100000 read, 55110 write accesses @501584000
+++ /dev/null
-Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 21 2016 14:24:31
-gem5 started Jul 21 2016 14:24:50
-gem5 executing on e108600-lin, pid 18184
-command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest-filter
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 501584000 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000520 # Number of seconds simulated
-sim_ticks 519755500 # Number of ticks simulated
-final_tick 519755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 97602781 # Simulator tick rate (ticks/s)
-host_mem_usage 236356 # Number of bytes of host memory used
-host_seconds 5.33 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0 252685 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 258147 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 248443 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 257431 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 256206 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 249786 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 257817 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 255503 # Number of bytes read from this memory
-system.physmem.bytes_read::total 2036018 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 1421696 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5545 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5403 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5468 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5504 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5430 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5562 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5554 # Number of bytes written to this memory
-system.physmem.bytes_written::total 1465524 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 13663 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 13833 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 13579 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 13621 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 13782 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 13599 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 13692 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 13646 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 109415 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 22214 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5545 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5403 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5468 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5504 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5430 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5562 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5554 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 66042 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 486161282 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 496670069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 477999752 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 495292498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 492935621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 480583659 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 496035155 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 491583062 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3917261097 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2735316894 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 10668478 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 10395272 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 10520331 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 10589595 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 10447220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 10316389 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 10701185 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 10685794 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2819641158 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2735316894 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 496829759 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 507065341 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 488520083 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 505882093 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 503382841 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 490900048 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 506736340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 502268855 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6736902255 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99523 # number of read accesses completed
-system.cpu0.num_writes 55175 # number of write accesses completed
-system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu0.l1c.tags.replacements 22190 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 391.732266 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13637 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22577 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.604022 # Average number of references to valid blocks.
-system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 391.732266 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.765102 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.765102 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 338094 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 338094 # Number of data accesses
-system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu0.l1c.ReadReq_hits::cpu0 8745 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8745 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1203 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1203 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9948 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9948 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9948 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9948 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36338 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36338 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 24073 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 24073 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60411 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60411 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60411 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60411 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 720327390 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 720327390 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 585363499 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 585363499 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1305690889 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1305690889 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1305690889 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1305690889 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45083 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45083 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25276 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25276 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70359 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70359 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70359 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70359 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806024 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.806024 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952405 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.952405 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.858611 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.858611 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.858611 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.858611 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19822.978425 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 19822.978425 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24316.184065 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 24316.184065 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 21613.462598 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 21613.462598 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 21613.462598 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 21613.462598 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 881814 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 67116 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.138655 # average number of cycles each access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l1c.writebacks::writebacks 9797 # number of writebacks
-system.cpu0.l1c.writebacks::total 9797 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36338 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36338 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24073 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 24073 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60411 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60411 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60411 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60411 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5547 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5547 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15416 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15416 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 683989390 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 683989390 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 561290499 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 561290499 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245279889 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1245279889 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245279889 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1245279889 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 771084187 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 771084187 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 771084187 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 771084187 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806024 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806024 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952405 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952405 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.858611 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.858611 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18822.978425 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18822.978425 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23316.184065 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23316.184065 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78131.947208 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78131.947208 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50018.434549 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50018.434549 # average overall mshr uncacheable latency
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 99560 # number of read accesses completed
-system.cpu1.num_writes 54738 # number of write accesses completed
-system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu1.l1c.tags.replacements 22160 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 392.166928 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13521 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22561 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.599309 # Average number of references to valid blocks.
-system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 392.166928 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.765951 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.765951 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 337076 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 337076 # Number of data accesses
-system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu1.l1c.ReadReq_hits::cpu1 8807 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8807 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1218 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1218 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 10025 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 10025 # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1 10025 # number of overall hits
-system.cpu1.l1c.overall_hits::total 10025 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 36399 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 36399 # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1 23708 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total 23708 # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1 60107 # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total 60107 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60107 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60107 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 728138208 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 728138208 # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1 572668423 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total 572668423 # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1 1300806631 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total 1300806631 # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1 1300806631 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total 1300806631 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45206 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45206 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 24926 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 24926 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1 70132 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total 70132 # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1 70132 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total 70132 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805181 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.805181 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.951135 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.951135 # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1 0.857055 # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total 0.857055 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.857055 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.857055 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 20004.346493 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 20004.346493 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24155.070989 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 24155.070989 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 21641.516479 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 21641.516479 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 21641.516479 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 21641.516479 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 883013 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 66936 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.191900 # average number of cycles each access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l1c.writebacks::writebacks 9595 # number of writebacks
-system.cpu1.l1c.writebacks::total 9595 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36399 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36399 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23708 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23708 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60107 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60107 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60107 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60107 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9955 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5404 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15359 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15359 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 691742208 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 691742208 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 548961423 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 548961423 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1240703631 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1240703631 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1240703631 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1240703631 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 776683501 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 776683501 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 776683501 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 776683501 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805181 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805181 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.951135 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.951135 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.857055 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.857055 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 19004.428913 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 19004.428913 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23155.113169 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23155.113169 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78019.437569 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78019.437569 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50568.624325 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50568.624325 # average overall mshr uncacheable latency
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 98983 # number of read accesses completed
-system.cpu2.num_writes 55204 # number of write accesses completed
-system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu2.l1c.tags.replacements 22113 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 391.892697 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13532 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks.
-system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 391.892697 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.765415 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.765415 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 337818 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 337818 # Number of data accesses
-system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1144 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1144 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9934 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9934 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9934 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9934 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36176 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36176 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 24169 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 24169 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60345 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 716181593 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 716181593 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 589266088 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 589266088 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 1305447681 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 1305447681 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 1305447681 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 1305447681 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44966 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 25313 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 25313 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 70279 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 70279 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 70279 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 70279 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804519 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.804519 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954806 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.954806 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.858649 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.858649 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.858649 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.858649 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19797.147086 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 19797.147086 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24381.070297 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 24381.070297 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 21633.071191 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 21633.071191 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 21633.071191 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 21633.071191 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 879879 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 66865 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.159037 # average number of cycles each access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks
-system.cpu2.l1c.writebacks::total 9745 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36176 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36176 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24169 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 24169 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9851 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5469 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15320 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15320 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 680005593 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 680005593 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 565098088 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 565098088 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245103681 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1245103681 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245103681 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1245103681 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769729433 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769729433 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769729433 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769729433 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804519 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804519 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954806 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954806 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858649 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858649 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18797.147086 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18797.147086 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23381.111672 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23381.111672 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78137.187392 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78137.187392 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50243.435574 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50243.435574 # average overall mshr uncacheable latency
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 100000 # number of read accesses completed
-system.cpu3.num_writes 55136 # number of write accesses completed
-system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu3.l1c.tags.replacements 22201 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 392.334218 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13633 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22606 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.603070 # Average number of references to valid blocks.
-system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 392.334218 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.766278 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.766278 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 339332 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 339332 # Number of data accesses
-system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu3.l1c.ReadReq_hits::cpu3 8805 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8805 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1190 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1190 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9995 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9995 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9995 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9995 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36852 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36852 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23757 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23757 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 60609 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 60609 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60609 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60609 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 737200497 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 737200497 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 577684792 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 577684792 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 1314885289 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 1314885289 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 1314885289 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 1314885289 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45657 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45657 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 24947 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 24947 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 70604 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 70604 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 70604 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 70604 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807149 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.807149 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952299 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.952299 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.858436 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.858436 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.858436 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.858436 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 20004.355177 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 20004.355177 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24316.403250 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 24316.403250 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 21694.555083 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 21694.555083 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 21694.555083 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 21694.555083 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 880663 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 67164 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.112129 # average number of cycles each access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.l1c.writebacks::writebacks 9556 # number of writebacks
-system.cpu3.l1c.writebacks::total 9556 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36852 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36852 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23757 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23757 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60609 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60609 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60609 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60609 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9752 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9752 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5506 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15258 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15258 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 700349497 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 700349497 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 553928792 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 553928792 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1254278289 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 1254278289 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1254278289 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1254278289 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 761853080 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 761853080 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 761853080 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 761853080 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807149 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807149 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952299 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952299 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.858436 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.858436 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 19004.382313 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 19004.382313 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23316.445342 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23316.445342 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78122.752256 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78122.752256 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 49931.385503 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 49931.385503 # average overall mshr uncacheable latency
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 99808 # number of read accesses completed
-system.cpu4.num_writes 55157 # number of write accesses completed
-system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu4.l1c.tags.replacements 22030 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 392.026241 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13726 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22418 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.612276 # Average number of references to valid blocks.
-system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 392.026241 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.765676 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.765676 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 338084 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 338084 # Number of data accesses
-system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu4.l1c.ReadReq_hits::cpu4 8869 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8869 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1181 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1181 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 10050 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 10050 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 10050 # number of overall hits
-system.cpu4.l1c.overall_hits::total 10050 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36458 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36458 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 23868 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 23868 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 60326 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 60326 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60326 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60326 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 723342269 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 723342269 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 578669341 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 578669341 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 1302011610 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 1302011610 # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4 1302011610 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total 1302011610 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45327 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45327 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4 25049 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4 70376 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total 70376 # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4 70376 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total 70376 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804333 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.804333 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952852 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.952852 # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4 0.857196 # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total 0.857196 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.857196 # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total 0.857196 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19840.426491 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 19840.426491 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24244.567664 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 24244.567664 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 21582.926267 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 21582.926267 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 21582.926267 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 21582.926267 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 883463 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 67109 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.164598 # average number of cycles each access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu4.l1c.writebacks::writebacks 9613 # number of writebacks
-system.cpu4.l1c.writebacks::total 9613 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36458 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23868 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23868 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60326 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60326 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60326 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60326 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5430 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15364 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 686885269 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 686885269 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 554802341 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 554802341 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1241687610 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 1241687610 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1241687610 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1241687610 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 775754665 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 775754665 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 775754665 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 775754665 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804333 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804333 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952852 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952852 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.857196 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.857196 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18840.453920 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18840.453920 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23244.609561 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23244.609561 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78090.866217 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78090.866217 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50491.712119 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50491.712119 # average overall mshr uncacheable latency
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 99404 # number of read accesses completed
-system.cpu5.num_writes 55162 # number of write accesses completed
-system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu5.l1c.tags.replacements 22439 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 391.788419 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13514 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22846 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.591526 # Average number of references to valid blocks.
-system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 391.788419 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.765212 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.765212 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 338295 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 338295 # Number of data accesses
-system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu5.l1c.ReadReq_hits::cpu5 8686 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8686 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1223 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1223 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9909 # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total 9909 # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5 9909 # number of overall hits
-system.cpu5.l1c.overall_hits::total 9909 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 36676 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 36676 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23788 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23788 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60464 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60464 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60464 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60464 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 728782621 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 728782621 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 575848202 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 575848202 # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5 1304630823 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total 1304630823 # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5 1304630823 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total 1304630823 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45362 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 45362 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5 25011 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5 70373 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total 70373 # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5 70373 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total 70373 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808518 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.808518 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951102 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.951102 # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5 0.859193 # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total 0.859193 # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5 0.859193 # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total 0.859193 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19870.831634 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 19870.831634 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24207.508071 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 24207.508071 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 21576.985032 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 21576.985032 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 21576.985032 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 21576.985032 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 880240 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 67028 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.132422 # average number of cycles each access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu5.l1c.writebacks::writebacks 9753 # number of writebacks
-system.cpu5.l1c.writebacks::total 9753 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36676 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23788 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60464 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60464 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60464 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60464 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9850 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5362 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15212 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 692108621 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 692108621 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 552061202 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 552061202 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1244169823 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 1244169823 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1244169823 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1244169823 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 771042075 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 771042075 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 771042075 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 771042075 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808518 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808518 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951102 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951102 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.859193 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.859193 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18870.886165 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18870.886165 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23207.550109 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23207.550109 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78278.383249 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78278.383249 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50686.436695 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50686.436695 # average overall mshr uncacheable latency
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 99584 # number of read accesses completed
-system.cpu6.num_writes 55158 # number of write accesses completed
-system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu6.l1c.tags.replacements 22137 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 391.593819 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13609 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22548 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.603557 # Average number of references to valid blocks.
-system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 391.593819 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.764832 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.764832 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 338403 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 338403 # Number of data accesses
-system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu6.l1c.ReadReq_hits::cpu6 8781 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8781 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1188 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1188 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9969 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9969 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9969 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9969 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36497 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36497 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 23948 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 23948 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60445 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60445 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60445 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60445 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 730258004 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 730258004 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 580007386 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 580007386 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 1310265390 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 1310265390 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 1310265390 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 1310265390 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45278 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45278 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 25136 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6 70414 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6 70414 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806065 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.806065 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952737 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.952737 # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6 0.858423 # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.858423 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 20008.713155 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 20008.713155 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24219.449891 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 24219.449891 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 21676.985524 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 21676.985524 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21676.985524 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 21676.985524 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 882368 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 67127 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.144755 # average number of cycles each access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu6.l1c.writebacks::writebacks 9587 # number of writebacks
-system.cpu6.l1c.writebacks::total 9587 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36497 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36497 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23948 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23948 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60445 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60445 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9817 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5564 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5564 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15381 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15381 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 693763004 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 693763004 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 556061386 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 556061386 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1249824390 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 1249824390 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1249824390 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1249824390 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767059984 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767059984 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 767059984 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 767059984 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806065 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806065 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952737 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952737 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 19008.767954 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 19008.767954 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23219.533406 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23219.533406 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78135.885097 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78135.885097 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 49870.618555 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 49870.618555 # average overall mshr uncacheable latency
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 98890 # number of read accesses completed
-system.cpu7.num_writes 55602 # number of write accesses completed
-system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu7.l1c.tags.replacements 22121 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 391.886114 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13491 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22504 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.599493 # Average number of references to valid blocks.
-system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 391.886114 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.765403 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.765403 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 383 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.748047 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 336547 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 336547 # Number of data accesses
-system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.cpu7.l1c.ReadReq_hits::cpu7 8615 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8615 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1223 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1223 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9838 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9838 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9838 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9838 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36077 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36077 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 24110 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 24110 # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7 60187 # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total 60187 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 60187 # number of overall misses
-system.cpu7.l1c.overall_misses::total 60187 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 719876948 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 719876948 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7 591584960 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total 591584960 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7 1311461908 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total 1311461908 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7 1311461908 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total 1311461908 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 44692 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7 25333 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total 25333 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7 70025 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total 70025 # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7 70025 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total 70025 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807236 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total 0.807236 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951723 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total 0.951723 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7 0.859507 # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total 0.859507 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7 0.859507 # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total 0.859507 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19953.902708 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 19953.902708 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24536.912484 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 24536.912484 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 21789.786964 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 21789.786964 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 21789.786964 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 21789.786964 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 881767 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 66704 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.219102 # average number of cycles each access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu7.l1c.writebacks::writebacks 9764 # number of writebacks
-system.cpu7.l1c.writebacks::total 9764 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36077 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36077 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24110 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 24110 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7 60187 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total 60187 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 60187 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 60187 # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5554 # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15362 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 683799948 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 683799948 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 567476960 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 567476960 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1251276908 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 1251276908 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1251276908 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1251276908 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 764550984 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 764550984 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 764550984 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 764550984 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807236 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807236 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951723 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951723 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.859507 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.859507 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18953.902708 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18953.902708 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23536.995438 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23536.995438 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 77951.772431 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 77951.772431 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49768.974352 # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49768.974352 # average overall mshr uncacheable latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 90719 # number of replacements
-system.l2c.tags.tagsinuse 1018.150991 # Cycle average of tags in use
-system.l2c.tags.total_refs 149983 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 91743 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 1.634817 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 9046000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 702.470265 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 39.119320 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 40.193520 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 38.067708 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 40.504400 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 39.836129 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 39.104490 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 39.067369 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 39.787790 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.686006 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.038202 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.039251 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2 0.037175 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3 0.039555 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.038902 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5 0.038188 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6 0.038152 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7 0.038855 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.994288 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 929 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 2127679 # Number of tag accesses
-system.l2c.tags.data_accesses 2127679 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 76258 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 76258 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0 455 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 421 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 452 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 407 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 451 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 439 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 454 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 475 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 3554 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 1826 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 1861 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 1960 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1829 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1856 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1881 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 14892 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0 9343 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1 9296 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2 9301 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3 9456 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4 9362 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5 9172 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6 9284 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7 9134 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 74348 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0 11169 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1 11157 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2 11261 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 11285 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 11233 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 10980 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 11140 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 11015 # number of demand (read+write) hits
-system.l2c.demand_hits::total 89240 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0 11169 # number of overall hits
-system.l2c.overall_hits::cpu1 11157 # number of overall hits
-system.l2c.overall_hits::cpu2 11261 # number of overall hits
-system.l2c.overall_hits::cpu3 11285 # number of overall hits
-system.l2c.overall_hits::cpu4 11233 # number of overall hits
-system.l2c.overall_hits::cpu5 10980 # number of overall hits
-system.l2c.overall_hits::cpu6 11140 # number of overall hits
-system.l2c.overall_hits::cpu7 11015 # number of overall hits
-system.l2c.overall_hits::total 89240 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0 1925 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1 1836 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2 1914 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 1906 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1942 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1877 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1898 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1911 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 15209 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0 4693 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1 4629 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2 4644 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3 4614 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4 4607 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5 4628 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6 4562 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7 4784 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 37161 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0 2455 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1 2583 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2 2376 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3 2554 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu4 2482 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu5 2499 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu6 2567 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu7 2497 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 20013 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0 7148 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1 7212 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2 7020 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3 7168 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4 7089 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5 7127 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6 7129 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7 7281 # number of demand (read+write) misses
-system.l2c.demand_misses::total 57174 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0 7148 # number of overall misses
-system.l2c.overall_misses::cpu1 7212 # number of overall misses
-system.l2c.overall_misses::cpu2 7020 # number of overall misses
-system.l2c.overall_misses::cpu3 7168 # number of overall misses
-system.l2c.overall_misses::cpu4 7089 # number of overall misses
-system.l2c.overall_misses::cpu5 7127 # number of overall misses
-system.l2c.overall_misses::cpu6 7129 # number of overall misses
-system.l2c.overall_misses::cpu7 7281 # number of overall misses
-system.l2c.overall_misses::total 57174 # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0 32240808 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1 31334307 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2 31443971 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3 32481798 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4 31939294 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5 32487949 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6 32438947 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7 31458982 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 255826056 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0 205522581 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1 201589053 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2 204096506 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3 201630443 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4 202953396 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5 200092863 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6 200475342 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7 208573158 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 1624933342 # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0 170016591 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1 178762923 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2 164403073 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3 176363992 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu4 171439292 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu5 173166429 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu6 177285527 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu7 173293048 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 1384730875 # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0 375539172 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1 380351976 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2 368499579 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3 377994435 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4 374392688 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5 373259292 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6 377760869 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7 381866206 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 3009664217 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0 375539172 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1 380351976 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2 368499579 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3 377994435 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4 374392688 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5 373259292 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6 377760869 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7 381866206 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 3009664217 # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks 76258 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 76258 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0 2380 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1 2257 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2 2366 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3 2313 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2393 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2352 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2386 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18763 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0 6519 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1 6490 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2 6604 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3 6443 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4 6478 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5 6436 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6 6418 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7 6665 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 52053 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0 11798 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1 11879 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2 11677 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3 12010 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu4 11844 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu5 11671 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu6 11851 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu7 11631 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 94361 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0 18317 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1 18369 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2 18281 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3 18453 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4 18322 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5 18107 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6 18269 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7 18296 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 146414 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0 18317 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1 18369 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2 18281 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3 18453 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4 18322 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5 18107 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6 18269 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7 18296 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 146414 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0 0.808824 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1 0.813469 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.808960 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.824038 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.811534 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.810449 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.806973 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.800922 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.810585 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0 0.719896 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1 0.713251 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2 0.703210 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3 0.716126 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4 0.711176 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5 0.719080 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6 0.710813 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7 0.717779 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.713907 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0 0.208086 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1 0.217443 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2 0.203477 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3 0.212656 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu4 0.209558 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu5 0.214120 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu6 0.216606 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu7 0.214685 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.212090 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0 0.390239 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1 0.392618 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2 0.384005 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3 0.388446 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4 0.386912 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5 0.393605 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6 0.390224 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7 0.397956 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.390495 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0 0.390239 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1 0.392618 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2 0.384005 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3 0.388446 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4 0.386912 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5 0.393605 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6 0.390224 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7 0.397956 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.390495 # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 16748.471688 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 17066.616013 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 16428.407001 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 17041.866737 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 16446.598352 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 17308.443793 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 17091.120653 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 16462.052329 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 16820.701953 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 43793.432985 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 43549.158134 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 43948.429371 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 43699.705895 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 44053.265900 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 43235.277226 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 43944.616835 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 43598.068144 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 43726.846479 # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0 69253.193890 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69207.480836 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69193.212542 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69054.029757 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69073.042707 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69294.289316 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69063.313985 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69400.499800 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 69191.569230 # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 52537.656967 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 52738.765391 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 52492.817521 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 52733.598633 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 52813.187756 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 52372.567981 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 52989.320943 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 52446.944925 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52640.434761 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 52537.656967 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 52738.765391 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 52492.817521 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 52733.598633 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 52813.187756 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 52372.567981 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 52989.320943 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 52446.944925 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52640.434761 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 47178 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 7722 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs 6.109557 # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 22214 # number of writebacks
-system.l2c.writebacks::total 22214 # number of writebacks
-system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu1 3 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu4 3 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu7 4 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total 18 # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0 16 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1 18 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2 19 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3 22 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4 24 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5 19 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6 17 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7 18 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total 153 # number of ReadExReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0 39 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1 35 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2 40 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3 33 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu4 29 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu5 39 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu6 37 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu7 32 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 284 # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0 55 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1 53 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2 59 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3 55 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4 53 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5 58 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6 54 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7 50 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 437 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0 55 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1 53 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2 59 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3 55 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4 53 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5 58 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6 54 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7 50 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 437 # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks 4803 # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total 4803 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0 1924 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1 1833 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2 1913 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3 1903 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4 1939 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6 1897 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7 1907 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 15191 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0 4677 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1 4611 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2 4625 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3 4592 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4 4583 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5 4609 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6 4545 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7 4766 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 37008 # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0 2416 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1 2548 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2 2336 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3 2521 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu4 2453 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu5 2460 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu6 2530 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu7 2465 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 19729 # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0 7093 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1 7159 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2 6961 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3 7113 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4 7036 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5 7069 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6 7075 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7 7231 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 56737 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0 7093 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1 7159 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2 6961 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3 7113 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4 7036 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5 7069 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6 7075 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7 7231 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 56737 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3 9751 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 78835 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0 5546 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1 5403 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2 5468 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3 5504 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu6 5563 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 43830 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0 15415 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1 15358 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2 15319 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3 15255 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu6 15380 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 122665 # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0 44370463 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900556 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43952891 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3 43546523 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44916850 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43178222 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6 43968016 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7 43732622 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 349566143 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0 157972902 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1 154816531 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2 157133230 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3 154812258 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4 156142960 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5 152972566 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6 154139305 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7 159984433 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1247974185 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 144081359 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 151505606 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 139163869 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 149583647 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 145392585 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146682187 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 150257353 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 146960130 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 1173626736 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0 302054261 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1 306322137 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2 296297099 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3 304395905 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4 301535545 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5 299654753 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6 304396658 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7 306944563 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 2421600921 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0 302054261 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1 306322137 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2 296297099 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3 304395905 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4 301535545 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5 299654753 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6 304396658 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7 306944563 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 2421600921 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 562092060 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 566771491 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 561276835 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 555967979 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 566543445 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 562440249 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 559671781 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 557696401 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 4492460241 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0 562092060 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1 566771491 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2 561276835 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3 555967979 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4 566543445 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5 562440249 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6 559671781 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7 557696401 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 4492460241 # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.808403 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.812140 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.808538 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.822741 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810280 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.809585 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.806548 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.799246 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.809625 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.717441 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.710478 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.700333 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.712711 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.707471 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.716128 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708165 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.715079 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.710968 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.204780 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.214496 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.200051 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.209908 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.207109 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.210779 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.213484 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.211934 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209080 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.387511 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.387511 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 23061.571206 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22859.004910 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22975.897020 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22883.091435 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 23164.956163 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 23028.385067 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 23177.657354 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22932.680650 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23011.397736 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 33776.545221 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33575.478421 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33974.752432 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33713.470819 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 34070.032730 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33189.968757 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33914.038504 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33567.862568 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 33721.740840 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59636.324089 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59460.598901 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59573.574058 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59335.044427 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59271.335100 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59626.905285 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59390.258103 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59618.713996 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59487.390947 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56955.320701 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56933.349171 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56976.635367 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 57016.508973 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 57030.747433 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 57100.532893 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 57010.469695 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56861.378569 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56985.605898 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36463.967564 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36903.990819 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36639.260722 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36444.967486 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36874.736071 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36973.458388 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36389.582640 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36303.632405 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 36623.814788 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 164288 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 148961 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 78834 # Transaction distribution
-system.membus.trans_dist::ReadResp 98509 # Transaction distribution
-system.membus.trans_dist::WriteReq 43828 # Transaction distribution
-system.membus.trans_dist::WriteResp 43821 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 22214 # Transaction distribution
-system.membus.trans_dist::CleanEvict 4965 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 52120 # Transaction distribution
-system.membus.trans_dist::ReadExReq 56238 # Transaction distribution
-system.membus.trans_dist::ReadExResp 10901 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 19680 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 431110 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 431110 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3501537 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 3501537 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 56051 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 276559 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 276559 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 276559 # Request fanout histogram
-system.membus.reqLayer0.occupancy 402118445 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 77.4 # Layer utilization (%)
-system.membus.respLayer0.occupancy 354384000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 68.2 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 665414 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 284013 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 335409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 85048 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 42676 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 42372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 78835 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370283 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43830 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43821 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 98472 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 166953 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29477 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161940 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161937 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 291468 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133769 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133274 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133373 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133750 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133468 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133407 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133623 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133404 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1068068 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1804723 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795646 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1797908 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1798742 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1795138 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1788203 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1789204 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1803712 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14373276 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 408427 # Total snoops (count)
-system.toL2Bus.snoopTraffic 21069312 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 705291 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.195765 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.989501 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 180431 25.58% 25.58% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 295517 41.90% 67.48% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 157808 22.37% 89.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 56265 7.98% 97.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 13098 1.86% 99.69% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 1998 0.28% 99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 166 0.02% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 8 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 705291 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 498497896 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 102236927 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 101928534 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 102159135 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 102401165 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 102112987 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 102230994 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 102247991 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101908995 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu0.l1c.cpu_side
-
-[system.cpu0.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu1.l1c.cpu_side
-
-[system.cpu1.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu2]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu2.l1c.cpu_side
-
-[system.cpu2.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu2.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu2.port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu2.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu3]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu3.l1c.cpu_side
-
-[system.cpu3.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu3.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu3.port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu3.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu4]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu4.l1c.cpu_side
-
-[system.cpu4.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu4.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu4.port
-mem_side=system.toL2Bus.slave[4]
-
-[system.cpu4.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu5]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu5.l1c.cpu_side
-
-[system.cpu5.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu5.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu5.port
-mem_side=system.toL2Bus.slave[5]
-
-[system.cpu5.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu6]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu6.l1c.cpu_side
-
-[system.cpu6.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu6.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu6.port
-mem_side=system.toL2Bus.slave[6]
-
-[system.cpu6.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu7]
-type=MemTest
-children=l1c
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-interval=1
-max_loads=100000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-percent_functional=50
-percent_reads=65
-percent_uncacheable=10
-power_model=Null
-progress_check=5000000
-progress_interval=10000
-size=65536
-suppress_func_warnings=false
-system=system
-port=system.cpu7.l1c.cpu_side
-
-[system.cpu7.l1c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu7.l1c.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu7.port
-mem_side=system.toL2Bus.slave[7]
-
-[system.cpu7.l1c.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=65536
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-system.cpu2: completed 10000 read, 5501 write accesses @55798000
-system.cpu1: completed 10000 read, 5520 write accesses @55942500
-system.cpu4: completed 10000 read, 5672 write accesses @55948000
-system.cpu0: completed 10000 read, 5544 write accesses @56022500
-system.cpu6: completed 10000 read, 5523 write accesses @56194500
-system.cpu5: completed 10000 read, 5576 write accesses @56196500
-system.cpu3: completed 10000 read, 5638 write accesses @56648500
-system.cpu7: completed 10000 read, 5609 write accesses @56820000
-system.cpu6: completed 20000 read, 11092 write accesses @104740000
-system.cpu4: completed 20000 read, 11217 write accesses @105227500
-system.cpu0: completed 20000 read, 11130 write accesses @105598500
-system.cpu5: completed 20000 read, 11119 write accesses @105604000
-system.cpu2: completed 20000 read, 11021 write accesses @105822000
-system.cpu7: completed 20000 read, 11085 write accesses @105988500
-system.cpu3: completed 20000 read, 11232 write accesses @106234000
-system.cpu1: completed 20000 read, 11093 write accesses @106248000
-system.cpu6: completed 30000 read, 16618 write accesses @154364000
-system.cpu4: completed 30000 read, 16727 write accesses @154528000
-system.cpu5: completed 30000 read, 16661 write accesses @154991500
-system.cpu0: completed 30000 read, 16578 write accesses @155150000
-system.cpu7: completed 30000 read, 16597 write accesses @155572000
-system.cpu3: completed 30000 read, 16777 write accesses @155692000
-system.cpu2: completed 30000 read, 16783 write accesses @155741500
-system.cpu1: completed 30000 read, 16605 write accesses @155757500
-system.cpu4: completed 40000 read, 22227 write accesses @203532500
-system.cpu0: completed 40000 read, 22094 write accesses @203735500
-system.cpu2: completed 40000 read, 22329 write accesses @204034500
-system.cpu6: completed 40000 read, 22323 write accesses @204341500
-system.cpu5: completed 40000 read, 22093 write accesses @204530500
-system.cpu3: completed 40000 read, 22449 write accesses @204979500
-system.cpu7: completed 40000 read, 22085 write accesses @205200000
-system.cpu1: completed 40000 read, 22157 write accesses @205324500
-system.cpu2: completed 50000 read, 27810 write accesses @252814500
-system.cpu0: completed 50000 read, 27524 write accesses @252975000
-system.cpu4: completed 50000 read, 27619 write accesses @253195000
-system.cpu6: completed 50000 read, 27815 write accesses @253668000
-system.cpu5: completed 50000 read, 27749 write accesses @254286500
-system.cpu3: completed 50000 read, 28015 write accesses @254662000
-system.cpu1: completed 50000 read, 27700 write accesses @255277000
-system.cpu7: completed 50000 read, 27537 write accesses @255788500
-system.cpu2: completed 60000 read, 33479 write accesses @302616500
-system.cpu4: completed 60000 read, 33151 write accesses @302639500
-system.cpu0: completed 60000 read, 33158 write accesses @302949000
-system.cpu5: completed 60000 read, 33293 write accesses @303327000
-system.cpu6: completed 60000 read, 33367 write accesses @303498500
-system.cpu3: completed 60000 read, 33551 write accesses @304167000
-system.cpu1: completed 60000 read, 33190 write accesses @304842500
-system.cpu7: completed 60000 read, 33105 write accesses @305455501
-system.cpu4: completed 70000 read, 38677 write accesses @351659000
-system.cpu0: completed 70000 read, 38797 write accesses @352214500
-system.cpu2: completed 70000 read, 39135 write accesses @352355500
-system.cpu6: completed 70000 read, 38839 write accesses @353200500
-system.cpu5: completed 70000 read, 38774 write accesses @353284000
-system.cpu3: completed 70000 read, 38980 write accesses @353497000
-system.cpu1: completed 70000 read, 38895 write accesses @355264000
-system.cpu7: completed 70000 read, 38703 write accesses @355598500
-system.cpu2: completed 80000 read, 44512 write accesses @400360000
-system.cpu4: completed 80000 read, 44241 write accesses @401405500
-system.cpu0: completed 80000 read, 44424 write accesses @401492500
-system.cpu6: completed 80000 read, 44426 write accesses @402695000
-system.cpu5: completed 80000 read, 44250 write accesses @402938000
-system.cpu3: completed 80000 read, 44495 write accesses @403103500
-system.cpu1: completed 80000 read, 44343 write accesses @403920500
-system.cpu7: completed 80000 read, 44194 write accesses @404626000
-system.cpu0: completed 90000 read, 49874 write accesses @450153000
-system.cpu2: completed 90000 read, 50018 write accesses @450453000
-system.cpu4: completed 90000 read, 49959 write accesses @452038500
-system.cpu3: completed 90000 read, 50050 write accesses @452249000
-system.cpu5: completed 90000 read, 49902 write accesses @452294500
-system.cpu6: completed 90000 read, 50125 write accesses @453074500
-system.cpu1: completed 90000 read, 49995 write accesses @453105500
-system.cpu7: completed 90000 read, 49805 write accesses @454516500
-system.cpu2: completed 100000 read, 55556 write accesses @500337000
+++ /dev/null
-Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 21 2016 14:24:31
-gem5 started Jul 21 2016 14:24:50
-gem5 executing on e108600-lin, pid 18186
-command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 500337000 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000522 # Number of seconds simulated
-sim_ticks 521659000 # Number of ticks simulated
-final_tick 521659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 99821577 # Simulator tick rate (ticks/s)
-host_mem_usage 236108 # Number of bytes of host memory used
-host_seconds 5.23 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0 261574 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 259726 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 254844 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 256223 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 261709 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 259188 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 257071 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 253171 # Number of bytes read from this memory
-system.physmem.bytes_read::total 2063506 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 1454400 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5412 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5468 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5497 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5381 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5437 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5503 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5505 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5688 # Number of bytes written to this memory
-system.physmem.bytes_written::total 1498291 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 13795 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 13774 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 13680 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 13673 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 13678 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 13740 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 13765 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 13771 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 109876 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 22725 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5412 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5468 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5497 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5381 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5437 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5503 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5505 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5688 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 66616 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 501427178 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 497884633 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 488526029 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 491169519 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 501685967 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 496853308 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 492795102 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 485318954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3955660690 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2788028195 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 10374593 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 10481943 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 10537535 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 10315168 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 10422517 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 10549037 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 10552871 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 10903675 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2872165533 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2788028195 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 511801771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 508366577 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 499063565 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 501484686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 512108485 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 507402345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 503347973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 496222628 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6827826224 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu0.num_reads 99316 # number of read accesses completed
-system.cpu0.num_writes 55523 # number of write accesses completed
-system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu0.l1c.tags.replacements 22284 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 390.956341 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13404 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.590667 # Average number of references to valid blocks.
-system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 390.956341 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.763587 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.763587 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 337730 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 337730 # Number of data accesses
-system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu0.l1c.ReadReq_hits::cpu0 8729 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8729 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1158 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1158 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9887 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9887 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9887 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9887 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36226 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36226 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 24124 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 24124 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60350 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60350 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60350 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60350 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 712731918 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 712731918 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 593276823 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 593276823 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1306008741 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1306008741 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1306008741 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1306008741 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 44955 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44955 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25282 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25282 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70237 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70237 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805828 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.805828 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954197 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.954197 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.859234 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.859234 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.859234 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.859234 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19674.596091 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 19674.596091 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24592.804800 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 24592.804800 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 21640.575659 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 21640.575659 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 21640.575659 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 21640.575659 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 872655 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 66710 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.081322 # average number of cycles each access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l1c.writebacks::writebacks 9923 # number of writebacks
-system.cpu0.l1c.writebacks::total 9923 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36226 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36226 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24124 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60350 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60350 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60350 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60350 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9863 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5414 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15277 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 676507918 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 676507918 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 569152823 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 569152823 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245660741 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1245660741 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245660741 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1245660741 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 770027425 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 770027425 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 770027425 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 770027425 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805828 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805828 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954197 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954197 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.859234 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.859234 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18674.651300 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18674.651300 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23592.804800 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23592.804800 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78072.333469 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78072.333469 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50404.361131 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50404.361131 # average overall mshr uncacheable latency
-system.cpu1.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu1.num_reads 99894 # number of read accesses completed
-system.cpu1.num_writes 55231 # number of write accesses completed
-system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu1.l1c.tags.replacements 22436 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 391.315294 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13542 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.593609 # Average number of references to valid blocks.
-system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 391.315294 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.764288 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.764288 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.736328 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338824 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338824 # Number of data accesses
-system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu1.l1c.ReadReq_hits::cpu1 8855 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8855 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 10004 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 10004 # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1 10004 # number of overall hits
-system.cpu1.l1c.overall_hits::total 10004 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 36651 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 36651 # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1 23831 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total 23831 # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1 60482 # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total 60482 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60482 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60482 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 724296905 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 724296905 # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1 578481683 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total 578481683 # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1 1302778588 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total 1302778588 # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1 1302778588 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total 1302778588 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45506 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45506 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 24980 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1 70486 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total 70486 # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1 70486 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total 70486 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805410 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.805410 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954003 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.954003 # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1 0.858071 # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total 0.858071 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.858071 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.858071 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 19761.995716 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 19761.995716 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24274.335236 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 24274.335236 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 21539.938957 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 21539.938957 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 21539.938957 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 21539.938957 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 869423 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 66885 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.998774 # average number of cycles each access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l1c.writebacks::writebacks 9819 # number of writebacks
-system.cpu1.l1c.writebacks::total 9819 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36651 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36651 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23831 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60482 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60482 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60482 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60482 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9872 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15341 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 687646905 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 687646905 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 554650683 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 554650683 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1242297588 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1242297588 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1242297588 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1242297588 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 771585814 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 771585814 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 771585814 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 771585814 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805410 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805410 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954003 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954003 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.858071 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.858071 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 18762.023001 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 18762.023001 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23274.335236 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23274.335236 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78159.016815 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78159.016815 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50295.666123 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50295.666123 # average overall mshr uncacheable latency
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu2.num_reads 99314 # number of read accesses completed
-system.cpu2.num_writes 55477 # number of write accesses completed
-system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu2.l1c.tags.replacements 22237 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 390.931192 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13493 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.596086 # Average number of references to valid blocks.
-system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 390.931192 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.763537 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.763537 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 337492 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 337492 # Number of data accesses
-system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu2.l1c.ReadReq_hits::cpu2 8705 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8705 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1188 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1188 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9893 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9893 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9893 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9893 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36190 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36190 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60319 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60319 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60319 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60319 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 713868287 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 713868287 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 591883556 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 591883556 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 1305751843 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 1305751843 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 1305751843 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 1305751843 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44895 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 44895 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 25317 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 25317 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 70212 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 70212 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 70212 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 70212 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806103 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.806103 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953075 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.953075 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.859098 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.859098 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.859098 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.859098 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19725.567477 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 19725.567477 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24529.966265 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 24529.966265 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 21647.438502 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 21647.438502 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 21647.438502 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 21647.438502 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 871392 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 66762 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.052215 # average number of cycles each access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.l1c.writebacks::writebacks 9753 # number of writebacks
-system.cpu2.l1c.writebacks::total 9753 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36190 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60319 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60319 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60319 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60319 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9852 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15350 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 677680287 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 677680287 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 567754556 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 567754556 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245434843 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1245434843 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245434843 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1245434843 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769926007 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769926007 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769926007 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769926007 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806103 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806103 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953075 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953075 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.859098 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.859098 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18725.622741 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18725.622741 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23529.966265 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23529.966265 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78149.208993 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78149.208993 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50158.046059 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50158.046059 # average overall mshr uncacheable latency
-system.cpu3.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu3.num_reads 99963 # number of read accesses completed
-system.cpu3.num_writes 54829 # number of write accesses completed
-system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu3.l1c.tags.replacements 22502 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 392.266593 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13442 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22904 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.586884 # Average number of references to valid blocks.
-system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 392.266593 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.766146 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.766146 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 338127 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 338127 # Number of data accesses
-system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu3.l1c.ReadReq_hits::cpu3 8758 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8758 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1160 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1160 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9918 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9918 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9918 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9918 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36654 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36654 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23751 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23751 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 60405 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 60405 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60405 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60405 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 726630781 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 726630781 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 580088175 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 580088175 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 1306718956 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 1306718956 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 1306718956 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 1306718956 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45412 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45412 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 24911 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 24911 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 70323 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 70323 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 70323 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 70323 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807143 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.807143 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953434 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.953434 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.858965 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.858965 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.858965 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.858965 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 19824.051427 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 19824.051427 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24423.736895 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 24423.736895 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 21632.629021 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 21632.629021 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 21632.629021 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 21632.629021 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 870625 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 66788 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.035650 # average number of cycles each access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.l1c.writebacks::writebacks 9808 # number of writebacks
-system.cpu3.l1c.writebacks::total 9808 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36654 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36654 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23751 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23751 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60405 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60405 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60405 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60405 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9824 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9824 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5382 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15206 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15206 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 689977781 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 689977781 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 556338175 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 556338175 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1246315956 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 1246315956 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1246315956 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1246315956 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 768661965 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 768661965 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 768661965 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 768661965 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807143 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807143 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953434 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953434 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.858965 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.858965 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 18824.078709 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 18824.078709 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23423.778999 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23423.778999 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78243.278196 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78243.278196 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 50549.912206 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 50549.912206 # average overall mshr uncacheable latency
-system.cpu4.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu4.num_reads 98794 # number of read accesses completed
-system.cpu4.num_writes 54937 # number of write accesses completed
-system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu4.l1c.tags.replacements 22508 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 392.668091 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13409 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22922 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.584984 # Average number of references to valid blocks.
-system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 392.668091 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.766930 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.766930 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.808594 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 337369 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 337369 # Number of data accesses
-system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1134 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1134 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9873 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 9873 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 9873 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9873 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36311 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36311 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 23983 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 23983 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 60294 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 60294 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60294 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60294 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 724331862 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 724331862 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 586488864 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 586488864 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 1310820726 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 1310820726 # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4 1310820726 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total 1310820726 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45050 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45050 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4 25117 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total 25117 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4 70167 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total 70167 # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4 70167 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total 70167 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806016 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.806016 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954851 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.954851 # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4 0.859293 # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total 0.859293 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.859293 # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total 0.859293 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19948.000936 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 19948.000936 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24454.357837 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 24454.357837 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 21740.483730 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 21740.483730 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 21740.483730 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 21740.483730 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 869421 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 66532 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.067712 # average number of cycles each access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu4.l1c.writebacks::writebacks 9883 # number of writebacks
-system.cpu4.l1c.writebacks::total 9883 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36311 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36311 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23983 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60294 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60294 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5439 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5439 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15180 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15180 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 688022862 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 688022862 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 562507864 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 562507864 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1250530726 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 1250530726 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1250530726 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1250530726 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 763019844 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 763019844 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 763019844 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 763019844 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806016 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806016 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954851 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954851 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.859293 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.859293 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18948.056016 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18948.056016 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23454.441229 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23454.441229 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78330.750847 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78330.750847 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50264.811858 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50264.811858 # average overall mshr uncacheable latency
-system.cpu5.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu5.num_reads 99762 # number of read accesses completed
-system.cpu5.num_writes 55488 # number of write accesses completed
-system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu5.l1c.tags.replacements 22372 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 391.676077 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13488 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22774 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.592254 # Average number of references to valid blocks.
-system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 391.676077 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.764992 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.764992 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 338416 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 338416 # Number of data accesses
-system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu5.l1c.ReadReq_hits::cpu5 8728 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8728 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1164 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1164 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9892 # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total 9892 # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5 9892 # number of overall hits
-system.cpu5.l1c.overall_hits::total 9892 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 36506 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 36506 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60501 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60501 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60501 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60501 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 721706442 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 721706442 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 584665158 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 584665158 # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5 1306371600 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total 1306371600 # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5 1306371600 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total 1306371600 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45234 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5 25159 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total 25159 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5 70393 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total 70393 # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5 70393 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total 70393 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807048 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.807048 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953734 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.953734 # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5 0.859475 # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total 0.859475 # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5 0.859475 # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total 0.859475 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19769.529447 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 19769.529447 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24366.124526 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 24366.124526 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 21592.562106 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 21592.562106 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 21592.562106 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 21592.562106 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 870792 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 66903 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.015739 # average number of cycles each access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu5.l1c.writebacks::writebacks 9839 # number of writebacks
-system.cpu5.l1c.writebacks::total 9839 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36506 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36506 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60501 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60501 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60501 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60501 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9845 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9845 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5507 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5507 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15352 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15352 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 685200442 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 685200442 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 560672158 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 560672158 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1245872600 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 1245872600 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1245872600 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1245872600 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 769357074 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 769357074 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 769357074 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 769357074 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807048 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807048 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953734 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953734 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.859475 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.859475 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18769.529447 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18769.529447 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23366.207877 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23366.207877 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78146.985678 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78146.985678 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50114.452449 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50114.452449 # average overall mshr uncacheable latency
-system.cpu6.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu6.num_reads 100000 # number of read accesses completed
-system.cpu6.num_writes 55102 # number of write accesses completed
-system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu6.l1c.tags.replacements 22254 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 391.922561 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13477 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22655 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.594880 # Average number of references to valid blocks.
-system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 391.922561 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.765474 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.765474 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 337953 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 337953 # Number of data accesses
-system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu6.l1c.ReadReq_hits::cpu6 8677 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8677 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1226 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1226 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9903 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9903 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9903 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9903 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36565 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36565 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 23825 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 23825 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60390 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60390 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60390 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60390 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 723690383 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 723690383 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 577264297 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 577264297 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 1300954680 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 1300954680 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 1300954680 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 1300954680 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45242 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45242 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 25051 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 25051 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6 70293 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6 70293 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808209 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.808209 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951060 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.951060 # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6 0.859118 # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total 0.859118 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.859118 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.859118 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 19791.887953 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 19791.887953 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24229.351396 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 24229.351396 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 21542.551416 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 21542.551416 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21542.551416 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 21542.551416 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 870051 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 66789 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.026861 # average number of cycles each access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu6.l1c.writebacks::writebacks 9787 # number of writebacks
-system.cpu6.l1c.writebacks::total 9787 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36565 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36565 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23825 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23825 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60390 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60390 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5506 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15410 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15410 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 687127383 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 687127383 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 553439297 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 553439297 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1240566680 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 1240566680 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1240566680 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1240566680 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 773835448 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 773835448 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 773835448 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 773835448 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808209 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808209 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951060 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951060 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859118 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859118 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 18791.942650 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 18791.942650 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23229.351396 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23229.351396 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78133.627625 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78133.627625 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 50216.446982 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 50216.446982 # average overall mshr uncacheable latency
-system.cpu7.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu7.num_reads 99606 # number of read accesses completed
-system.cpu7.num_writes 54773 # number of write accesses completed
-system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu7.l1c.tags.replacements 21949 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 391.189669 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13361 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22347 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.597888 # Average number of references to valid blocks.
-system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 391.189669 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.764042 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.764042 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 335877 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 335877 # Number of data accesses
-system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.cpu7.l1c.ReadReq_hits::cpu7 8692 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8692 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9840 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9840 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9840 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9840 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36424 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36424 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23598 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23598 # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7 60022 # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total 60022 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 60022 # number of overall misses
-system.cpu7.l1c.overall_misses::total 60022 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 721113865 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 721113865 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7 575330708 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total 575330708 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7 1296444573 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total 1296444573 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7 1296444573 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total 1296444573 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 45116 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 45116 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7 24746 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total 24746 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7 69862 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total 69862 # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7 69862 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total 69862 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807341 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953609 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total 0.953609 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7 0.859151 # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total 0.859151 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7 0.859151 # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total 0.859151 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19797.766994 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 19797.766994 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24380.485973 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 24380.485973 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 21599.489737 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 21599.489737 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 21599.489737 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 21599.489737 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 871786 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 66469 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.115678 # average number of cycles each access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu7.l1c.writebacks::writebacks 9508 # number of writebacks
-system.cpu7.l1c.writebacks::total 9508 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36424 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36424 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23598 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23598 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7 60022 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total 60022 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 60022 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 60022 # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9972 # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9972 # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5689 # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15661 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15661 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 684690865 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 684690865 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 551733708 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 551733708 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1236424573 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 1236424573 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1236424573 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1236424573 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 778989868 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 778989868 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 778989868 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 778989868 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807341 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953609 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953609 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.859151 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.859151 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18797.794449 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18797.794449 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23380.528350 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23380.528350 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78117.716406 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78117.716406 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49740.748867 # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49740.748867 # average overall mshr uncacheable latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 91944 # number of replacements
-system.l2c.tags.tagsinuse 1018.135199 # Cycle average of tags in use
-system.l2c.tags.total_refs 150035 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 92968 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 1.613835 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 8704000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 700.601873 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 40.249147 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 40.174988 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 39.327766 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 40.057426 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 39.781379 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 39.374996 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 39.797467 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 38.770159 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.684182 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.039306 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.039233 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2 0.038406 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3 0.039119 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.038849 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5 0.038452 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6 0.038865 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7 0.037861 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.994273 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 947 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 2139200 # Number of tag accesses
-system.l2c.tags.data_accesses 2139200 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 77024 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 77024 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0 414 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 433 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 398 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 417 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 426 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 450 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 421 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 435 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 3394 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 1862 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 1934 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 1949 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1865 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1828 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1873 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1869 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1854 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 15034 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0 9356 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1 9333 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2 9371 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3 9291 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4 9201 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5 9292 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6 9177 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7 9226 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 74247 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0 11218 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1 11267 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2 11320 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 11156 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 11029 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 11165 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 11046 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 11080 # number of demand (read+write) hits
-system.l2c.demand_hits::total 89281 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0 11218 # number of overall hits
-system.l2c.overall_hits::cpu1 11267 # number of overall hits
-system.l2c.overall_hits::cpu2 11320 # number of overall hits
-system.l2c.overall_hits::cpu3 11156 # number of overall hits
-system.l2c.overall_hits::cpu4 11029 # number of overall hits
-system.l2c.overall_hits::cpu5 11165 # number of overall hits
-system.l2c.overall_hits::cpu6 11046 # number of overall hits
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-system.l2c.UpgradeReq_misses::cpu4 1852 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1900 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1862 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1851 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 14964 # number of UpgradeReq misses
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-system.l2c.ReadSharedReq_misses::cpu4 2543 # number of ReadSharedReq misses
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-system.l2c.ReadSharedReq_misses::cpu7 2476 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 20070 # number of ReadSharedReq misses
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-system.l2c.demand_misses::cpu4 7334 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5 7211 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6 7174 # number of demand (read+write) misses
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-system.l2c.demand_misses::total 57889 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu6 7174 # number of overall misses
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-system.l2c.UpgradeReq_miss_latency::cpu7 30383968 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 248613949 # number of UpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu3 204329473 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4 209030536 # number of ReadExReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu7 201887028 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 1649560056 # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0 169116609 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1 174843463 # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu3 173149203 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu4 175448063 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu5 172961782 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu6 175284714 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu7 170387602 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 1381344532 # number of ReadSharedReq miss cycles
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-system.l2c.demand_miss_latency::cpu1 378649095 # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu3 377478676 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4 384478599 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5 378177997 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6 376690597 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7 372274630 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 3030904588 # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::total 3030904588 # number of overall miss cycles
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-system.l2c.WritebackDirty_accesses::total 77024 # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu3 2253 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu5 2350 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2283 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2286 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18358 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::cpu3 6583 # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::cpu5 6574 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6 6499 # number of ReadExReq accesses(hits+misses)
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-system.l2c.overall_accesses::cpu5 18376 # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total 147170 # number of overall (read+write) accesses
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-system.l2c.UpgradeReq_miss_rate::cpu3 0.814913 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.812994 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.808511 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.815594 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.809711 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.815121 # miss rate for UpgradeReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu3 0.212827 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu4 0.216536 # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu6 0.217046 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu7 0.211588 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.212793 # miss rate for ReadSharedReq accesses
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-system.l2c.overall_miss_rate::cpu6 0.393743 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7 0.390606 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.393348 # miss rate for overall accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1 17005.497831 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 16729.731895 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 16405.474401 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 16630.271598 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 16732.866316 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 16301.176692 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 16414.893571 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 16614.137196 # average UpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu3 43308.493641 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 43629.834273 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 43653.736439 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 43500.190713 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 43641.813230 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 43617.230916 # average ReadExReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68915.794249 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68928.822850 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68992.553284 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68909.076494 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68901.224057 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68815.671244 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 68826.334429 # average ReadSharedReq miss latency
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-system.l2c.demand_avg_miss_latency::cpu7 52418.280766 # average overall miss latency
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-system.l2c.blocked::no_mshrs 7668 # number of cycles access was blocked
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-system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits
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-system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits
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-system.l2c.UpgradeReq_mshr_hits::total 25 # number of UpgradeReq MSHR hits
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-system.l2c.ReadExReq_mshr_hits::cpu3 21 # number of ReadExReq MSHR hits
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-system.l2c.ReadExReq_mshr_hits::cpu6 26 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7 21 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total 166 # number of ReadExReq MSHR hits
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-system.l2c.ReadSharedReq_mshr_hits::total 267 # number of ReadSharedReq MSHR hits
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-system.l2c.demand_mshr_hits::cpu2 48 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3 48 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4 52 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5 62 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6 61 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7 62 # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_hits::cpu6 61 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7 62 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 433 # number of overall MSHR hits
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-system.l2c.CleanEvict_mshr_misses::total 4900 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1 1840 # number of UpgradeReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu3 1833 # number of UpgradeReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu5 1898 # number of UpgradeReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu7 1846 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 14939 # number of UpgradeReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::cpu7 4605 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 37653 # number of ReadExReq MSHR misses
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-system.l2c.ReadSharedReq_mshr_misses::cpu6 2509 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu7 2435 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 19803 # number of ReadSharedReq MSHR misses
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-system.l2c.demand_mshr_misses::cpu4 7282 # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu7 7040 # number of demand (read+write) MSHR misses
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-system.l2c.overall_mshr_misses::cpu6 7113 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7 7040 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 57456 # number of overall MSHR misses
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-system.l2c.ReadReq_mshr_uncacheable::cpu3 9823 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu5 9844 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu7 9971 # number of ReadReq MSHR uncacheable
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-system.l2c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable
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-system.l2c.WriteReq_mshr_uncacheable::cpu3 5381 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu4 5438 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu5 5504 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu6 5505 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 43897 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0 15276 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses
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-system.l2c.overall_mshr_uncacheable_misses::cpu3 15204 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu4 15179 # number of overall MSHR uncacheable misses
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-system.l2c.overall_mshr_uncacheable_misses::cpu6 15409 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu7 15660 # number of overall MSHR uncacheable misses
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900379 # number of UpgradeReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu3 41317767 # number of UpgradeReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43188221 # number of UpgradeReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu3 156613177 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4 160372266 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5 157473921 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6 154279145 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7 154804178 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1265958363 # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 148034574 # number of ReadSharedReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 146721083 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 148442317 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146274036 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 148395292 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 144143903 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 1169597992 # number of ReadSharedReq MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu3 303334260 # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu5 303747957 # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu7 298948081 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 2435556355 # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 556927201 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 552042138 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 557542912 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 561245949 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 564245669 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 4468939147 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0 558924481 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1 559228006 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2 558782791 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3 556927201 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4 552042138 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5 557542912 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6 561245949 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7 564245669 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 4468939147 # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.808081 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.829424 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.813582 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810799 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.807660 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.815155 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.807524 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.813760 # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.704528 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.707857 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.713504 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721106 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.711287 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708417 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710648 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.712410 # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.212267 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.205997 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.210540 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.213641 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.209541 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.214060 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.208084 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209962 # mshr miss rate for ReadSharedReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.390406 # mshr miss rate for overall accesses
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22900.155784 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22541.062193 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 22900.107201 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 22754.594837 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 22859.188071 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22453.338570 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22761.370708 # average UpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33649.557825 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33507.751783 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33343.235469 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 33599.888121 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33677.057528 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33509.805604 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33616.542454 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 33621.713091 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58986.188889 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58674.028537 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59143.234112 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59042.689336 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59163.936628 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59148.417307 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59145.194101 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59196.674743 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59061.656921 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56668.810808 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56647.893639 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56717.701076 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 56696.243612 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 56672.019095 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 56637.841528 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 56668.613590 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56588.674055 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56662.091378 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36588.405407 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36453.165113 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36402.787687 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36630.307880 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36368.808090 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36326.746938 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36423.255825 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36031.013346 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 36401.794839 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 165129 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 149421 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 78866 # Transaction distribution
-system.membus.trans_dist::ReadResp 98603 # Transaction distribution
-system.membus.trans_dist::WriteReq 43891 # Transaction distribution
-system.membus.trans_dist::WriteResp 43890 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 22725 # Transaction distribution
-system.membus.trans_dist::CleanEvict 5096 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 51962 # Transaction distribution
-system.membus.trans_dist::ReadExReq 56321 # Transaction distribution
-system.membus.trans_dist::ReadExResp 11265 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 19745 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 432364 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 432364 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3561537 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 3561537 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 55548 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 277065 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 277065 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 277065 # Request fanout histogram
-system.membus.reqLayer0.occupancy 406206026 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 77.9 # Layer utilization (%)
-system.membus.respLayer0.occupancy 356644000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 68.4 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 666785 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 283960 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 335937 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 86136 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 43107 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 43029 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 78870 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370375 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43897 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43890 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 99750 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 167866 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 28850 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 28850 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162383 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162380 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 291522 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133688 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 134001 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133796 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133576 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133426 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133904 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133634 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133439 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1069464 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1829226 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1815722 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1817716 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1809443 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1812235 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1808884 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1798064 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1779371 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14470661 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 409171 # Total snoops (count)
-system.toL2Bus.snoopTraffic 21085504 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 706797 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.196447 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.990756 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 181481 25.68% 25.68% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 294628 41.68% 67.36% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 158602 22.44% 89.80% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 56776 8.03% 97.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 13243 1.87% 99.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 1898 0.27% 99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 160 0.02% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 9 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 706797 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 500161714 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 102256739 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 102545160 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 102125332 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 102285646 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 102013056 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 102427641 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 102433420 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101994041 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.010000 # Number of seconds simulated
-sim_ticks 10000000000 # Number of ticks simulated
-final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 586000670 # Simulator tick rate (ticks/s)
-host_mem_usage 1428656 # Number of bytes of host memory used
-host_seconds 17.06 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::l0subsys0.tester0 2056192 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys0.tester1 2014720 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys1.tester0 2083456 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys1.tester1 2130880 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys2.tester0 2005568 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys2.tester1 2026048 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys3.tester0 2065280 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys3.tester1 2035584 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys4.tester0 2163904 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys4.tester1 2093312 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys5.tester0 2131712 # Number of bytes read from this memory
-system.physmem.bytes_read::l0subsys5.tester1 2070336 # Number of bytes read from this memory
-system.physmem.bytes_read::l2subsys0.tester 2185536 # Number of bytes read from this memory
-system.physmem.bytes_read::total 27062528 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 9533312 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9533312 # Number of bytes written to this memory
-system.physmem.num_reads::l0subsys0.tester0 32128 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys0.tester1 31480 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys1.tester0 32554 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys1.tester1 33295 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys2.tester0 31337 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys2.tester1 31657 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys3.tester0 32270 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys3.tester1 31806 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys4.tester0 33811 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys4.tester1 32708 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys5.tester0 33308 # Number of read requests responded to by this memory
-system.physmem.num_reads::l0subsys5.tester1 32349 # Number of read requests responded to by this memory
-system.physmem.num_reads::l2subsys0.tester 34149 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 422852 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 148958 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 148958 # Number of write requests responded to by this memory
-system.physmem.bw_read::l0subsys0.tester0 205619200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys0.tester1 201472000 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys1.tester0 208345600 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys1.tester1 213088000 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys2.tester0 200556800 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys2.tester1 202604800 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys3.tester0 206528000 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys3.tester1 203558400 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys4.tester0 216390400 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys4.tester1 209331200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys5.tester0 213171200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l0subsys5.tester1 207033600 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::l2subsys0.tester 218553600 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2706252800 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 953331200 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 953331200 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 953331200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys0.tester0 205619200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys0.tester1 201472000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys1.tester0 208345600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys1.tester1 213088000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys2.tester0 200556800 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys2.tester1 202604800 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys3.tester0 206528000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys3.tester1 203558400 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys4.tester0 216390400 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys4.tester1 209331200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys5.tester0 213171200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l0subsys5.tester1 207033600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::l2subsys0.tester 218553600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3659584000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 422854 # Number of read requests accepted
-system.physmem.writeReqs 148958 # Number of write requests accepted
-system.physmem.readBursts 422854 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 148958 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 27060224 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 2432 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9531904 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 27062656 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9533312 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 38 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 26538 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26515 # Per bank write bursts
-system.physmem.perBankRdBursts::2 26457 # Per bank write bursts
-system.physmem.perBankRdBursts::3 26413 # Per bank write bursts
-system.physmem.perBankRdBursts::4 26526 # Per bank write bursts
-system.physmem.perBankRdBursts::5 26432 # Per bank write bursts
-system.physmem.perBankRdBursts::6 26460 # Per bank write bursts
-system.physmem.perBankRdBursts::7 26446 # Per bank write bursts
-system.physmem.perBankRdBursts::8 26723 # Per bank write bursts
-system.physmem.perBankRdBursts::9 26408 # Per bank write bursts
-system.physmem.perBankRdBursts::10 26159 # Per bank write bursts
-system.physmem.perBankRdBursts::11 26321 # Per bank write bursts
-system.physmem.perBankRdBursts::12 26387 # Per bank write bursts
-system.physmem.perBankRdBursts::13 26566 # Per bank write bursts
-system.physmem.perBankRdBursts::14 26098 # Per bank write bursts
-system.physmem.perBankRdBursts::15 26367 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9312 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9367 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9386 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9443 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9257 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9263 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9303 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9331 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9435 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9399 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9280 # Per bank write bursts
-system.physmem.perBankWrBursts::11 9145 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9382 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9282 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9214 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9137 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 9999908219 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 422854 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 148958 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 43122 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 85605 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 84278 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 61946 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 43434 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 30724 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 21728 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 15491 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 10921 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 7752 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 5579 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 3961 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 2651 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1810 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1278 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 839 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 584 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 407 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 163 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 99 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 60 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 46 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 32 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 21 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4877 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6843 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7878 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 8666 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 9331 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 9709 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 9888 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 10059 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9944 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 10042 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 10156 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 10189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 10292 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 10096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 9928 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1820 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 503 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 412 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 340 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 268 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 225 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 199 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 180 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 170 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 565061 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 64.756251 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 64.522780 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 7.121324 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 558476 98.83% 98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 6582 1.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 565061 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 9305 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 45.437292 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 43.280128 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 45.255047 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 9302 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 2 0.02% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-4351 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 9305 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 9305 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.006018 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.005571 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.126830 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 9281 99.74% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 3 0.03% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 13 0.14% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 6 0.06% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 9305 # Writes before turning the bus around for reads
-system.physmem.totQLat 23113331872 # Total ticks spent queuing
-system.physmem.totMemAccLat 31041131872 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2114080000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 54665.23 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 73415.23 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2706.02 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 953.19 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2706.27 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 953.33 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 28.59 # Data bus utilization in percentage
-system.physmem.busUtilRead 21.14 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 7.45 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 3.92 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.94 # Average write queue length when enqueuing
-system.physmem.readRowHits 2662 # Number of row buffer hits during reads
-system.physmem.writeRowHits 4016 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 0.63 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 2.70 # Row buffer hit rate for writes
-system.physmem.avgGap 17488.10 # Average gap between requests
-system.physmem.pageHitRate 1.17 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2139737040 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1167515250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1651455000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 483654240 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 6798762495 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 34896750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 12929011815 # Total energy per rank (pJ)
-system.physmem_0.averagePower 1293.176305 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 21746512 # Time in different power states
-system.physmem_0.memoryStateTime::REF 333840000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 9642298751 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2131012800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1162755000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1645597200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 481140000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 6796546335 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 36816750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 12906859125 # Total energy per rank (pJ)
-system.physmem_1.averagePower 1290.965729 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 25323820 # Time in different power states
-system.physmem_1.memoryStateTime::REF 333840000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 9638682193 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys0.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys0.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys0.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys0.tester0.numPackets 65034 # Number of packets generated
-system.l0subsys0.tester0.numRetries 2631 # Number of retries
-system.l0subsys0.tester0.retryTicks 64675381 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys0.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys0.tester1.numPackets 65594 # Number of packets generated
-system.l0subsys0.tester1.numRetries 2683 # Number of retries
-system.l0subsys0.tester1.retryTicks 67015418 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys0.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.l0subsys0.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys0.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l0subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys0.xbar.trans_dist::ReadReq 84077 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::ReadResp 79156 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4921 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::WriteReq 46551 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::WriteResp 46551 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::WritebackDirty 22891 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::CleanEvict 74163 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::UpgradeReq 16582 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::ReadExReq 21053 # Transaction distribution
-system.l0subsys0.xbar.trans_dist::ReadSharedReq 27577 # Transaction distribution
-system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 130068 # Packet count per connected master and slave (bytes)
-system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 131188 # Packet count per connected master and slave (bytes)
-system.l0subsys0.xbar.pkt_count::total 261256 # Packet count per connected master and slave (bytes)
-system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 520272 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 524752 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys0.xbar.pkt_size::total 1045024 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys0.xbar.snoops 162266 # Total snoops (count)
-system.l0subsys0.xbar.snoopTraffic 1465024 # Total snoop traffic (bytes)
-system.l0subsys0.xbar.snoop_fanout::samples 295596 # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::mean 0 # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::stdev 0 # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::0 295596 100.00% 100.00% # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::max_value 0 # Request fanout histogram
-system.l0subsys0.xbar.snoop_fanout::total 295596 # Request fanout histogram
-system.l0subsys0.xbar.reqLayer0.occupancy 246613193 # Layer occupancy (ticks)
-system.l0subsys0.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.l0subsys0.xbar.respLayer0.occupancy 112497122 # Layer occupancy (ticks)
-system.l0subsys0.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
-system.l0subsys0.xbar.respLayer1.occupancy 113637927 # Layer occupancy (ticks)
-system.l0subsys0.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
-system.l0subsys1.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys1.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys1.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys1.tester0.numPackets 64234 # Number of packets generated
-system.l0subsys1.tester0.numRetries 2842 # Number of retries
-system.l0subsys1.tester0.retryTicks 72381522 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys1.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys1.tester1.numPackets 67237 # Number of packets generated
-system.l0subsys1.tester1.numRetries 2791 # Number of retries
-system.l0subsys1.tester1.retryTicks 70676938 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys1.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.l0subsys1.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys1.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys1.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l0subsys1.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys1.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys1.xbar.trans_dist::ReadReq 84459 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::ReadResp 79428 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 5031 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::WriteReq 47012 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::WriteResp 47011 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::WritebackDirty 23704 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::CleanEvict 74816 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::UpgradeReq 15753 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::ReadExReq 20596 # Transaction distribution
-system.l0subsys1.xbar.trans_dist::ReadSharedReq 26573 # Transaction distribution
-system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 128468 # Packet count per connected master and slave (bytes)
-system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 134473 # Packet count per connected master and slave (bytes)
-system.l0subsys1.xbar.pkt_count::total 262941 # Packet count per connected master and slave (bytes)
-system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 513872 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 537896 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys1.xbar.pkt_size::total 1051768 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys1.xbar.snoops 161442 # Total snoops (count)
-system.l0subsys1.xbar.snoopTraffic 1517056 # Total snoop traffic (bytes)
-system.l0subsys1.xbar.snoop_fanout::samples 295865 # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::mean 0 # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::stdev 0 # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::0 295865 100.00% 100.00% # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::max_value 0 # Request fanout histogram
-system.l0subsys1.xbar.snoop_fanout::total 295865 # Request fanout histogram
-system.l0subsys1.xbar.reqLayer0.occupancy 248872620 # Layer occupancy (ticks)
-system.l0subsys1.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.l0subsys1.xbar.respLayer0.occupancy 110615455 # Layer occupancy (ticks)
-system.l0subsys1.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
-system.l0subsys1.xbar.respLayer1.occupancy 116451863 # Layer occupancy (ticks)
-system.l0subsys1.xbar.respLayer1.utilization 1.2 # Layer utilization (%)
-system.l0subsys2.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys2.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys2.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys2.tester0.numPackets 65812 # Number of packets generated
-system.l0subsys2.tester0.numRetries 2732 # Number of retries
-system.l0subsys2.tester0.retryTicks 67922794 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys2.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys2.tester1.numPackets 65437 # Number of packets generated
-system.l0subsys2.tester1.numRetries 2695 # Number of retries
-system.l0subsys2.tester1.retryTicks 66990492 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys2.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.l0subsys2.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys2.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys2.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l0subsys2.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys2.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys2.xbar.trans_dist::ReadReq 84334 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::ReadResp 79404 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4929 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::WriteReq 46915 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::WriteResp 46915 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::WritebackDirty 22486 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::CleanEvict 73149 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::UpgradeReq 16126 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::ReadExReq 21115 # Transaction distribution
-system.l0subsys2.xbar.trans_dist::ReadSharedReq 28234 # Transaction distribution
-system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 131623 # Packet count per connected master and slave (bytes)
-system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 130874 # Packet count per connected master and slave (bytes)
-system.l0subsys2.xbar.pkt_count::total 262497 # Packet count per connected master and slave (bytes)
-system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 526488 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 523496 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys2.xbar.pkt_size::total 1049984 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys2.xbar.snoops 161110 # Total snoops (count)
-system.l0subsys2.xbar.snoopTraffic 1439104 # Total snoop traffic (bytes)
-system.l0subsys2.xbar.snoop_fanout::samples 295231 # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::mean 0 # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::stdev 0 # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::0 295231 100.00% 100.00% # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::max_value 0 # Request fanout histogram
-system.l0subsys2.xbar.snoop_fanout::total 295231 # Request fanout histogram
-system.l0subsys2.xbar.reqLayer0.occupancy 248142071 # Layer occupancy (ticks)
-system.l0subsys2.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.l0subsys2.xbar.respLayer0.occupancy 114094156 # Layer occupancy (ticks)
-system.l0subsys2.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
-system.l0subsys2.xbar.respLayer1.occupancy 113403149 # Layer occupancy (ticks)
-system.l0subsys2.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
-system.l0subsys3.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys3.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys3.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys3.tester0.numPackets 65010 # Number of packets generated
-system.l0subsys3.tester0.numRetries 2630 # Number of retries
-system.l0subsys3.tester0.retryTicks 64351691 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys3.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys3.tester1.numPackets 65550 # Number of packets generated
-system.l0subsys3.tester1.numRetries 2637 # Number of retries
-system.l0subsys3.tester1.retryTicks 67267239 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys3.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.l0subsys3.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys3.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys3.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l0subsys3.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys3.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys3.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys3.xbar.trans_dist::ReadReq 83832 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::ReadResp 78911 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4921 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::WriteReq 46728 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::WriteResp 46727 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::WritebackDirty 23115 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::CleanEvict 73076 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::UpgradeReq 16273 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::ReadExReq 21213 # Transaction distribution
-system.l0subsys3.xbar.trans_dist::ReadSharedReq 27196 # Transaction distribution
-system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 130019 # Packet count per connected master and slave (bytes)
-system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 131100 # Packet count per connected master and slave (bytes)
-system.l0subsys3.xbar.pkt_count::total 261119 # Packet count per connected master and slave (bytes)
-system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 520080 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 524400 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys3.xbar.pkt_size::total 1044480 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys3.xbar.snoops 160873 # Total snoops (count)
-system.l0subsys3.xbar.snoopTraffic 1479360 # Total snoop traffic (bytes)
-system.l0subsys3.xbar.snoop_fanout::samples 294076 # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::mean 0 # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::stdev 0 # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::0 294076 100.00% 100.00% # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::max_value 0 # Request fanout histogram
-system.l0subsys3.xbar.snoop_fanout::total 294076 # Request fanout histogram
-system.l0subsys3.xbar.reqLayer0.occupancy 246366404 # Layer occupancy (ticks)
-system.l0subsys3.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.l0subsys3.xbar.respLayer0.occupancy 112403324 # Layer occupancy (ticks)
-system.l0subsys3.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
-system.l0subsys3.xbar.respLayer1.occupancy 113183873 # Layer occupancy (ticks)
-system.l0subsys3.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
-system.l0subsys4.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys4.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys4.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys4.tester0.numPackets 66012 # Number of packets generated
-system.l0subsys4.tester0.numRetries 2782 # Number of retries
-system.l0subsys4.tester0.retryTicks 70240058 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys4.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys4.tester1.numPackets 66554 # Number of packets generated
-system.l0subsys4.tester1.numRetries 2702 # Number of retries
-system.l0subsys4.tester1.retryTicks 70715102 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys4.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.l0subsys4.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys4.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys4.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l0subsys4.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys4.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys4.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys4.xbar.trans_dist::ReadReq 85335 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::ReadResp 80858 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4477 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::WriteReq 47231 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::WriteResp 47231 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::WritebackDirty 23610 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::CleanEvict 76410 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::UpgradeReq 15815 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::ReadExReq 19797 # Transaction distribution
-system.l0subsys4.xbar.trans_dist::ReadSharedReq 26031 # Transaction distribution
-system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 132024 # Packet count per connected master and slave (bytes)
-system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 133108 # Packet count per connected master and slave (bytes)
-system.l0subsys4.xbar.pkt_count::total 265132 # Packet count per connected master and slave (bytes)
-system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 528096 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 532432 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys4.xbar.pkt_size::total 1060528 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys4.xbar.snoops 161663 # Total snoops (count)
-system.l0subsys4.xbar.snoopTraffic 1511040 # Total snoop traffic (bytes)
-system.l0subsys4.xbar.snoop_fanout::samples 297063 # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::mean 0 # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::stdev 0 # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::0 297063 100.00% 100.00% # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::max_value 0 # Request fanout histogram
-system.l0subsys4.xbar.snoop_fanout::total 297063 # Request fanout histogram
-system.l0subsys4.xbar.reqLayer0.occupancy 250291221 # Layer occupancy (ticks)
-system.l0subsys4.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.l0subsys4.xbar.respLayer0.occupancy 115013486 # Layer occupancy (ticks)
-system.l0subsys4.xbar.respLayer0.utilization 1.2 # Layer utilization (%)
-system.l0subsys4.xbar.respLayer1.occupancy 114676529 # Layer occupancy (ticks)
-system.l0subsys4.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
-system.l0subsys5.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys5.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys5.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys5.tester0.numPackets 66218 # Number of packets generated
-system.l0subsys5.tester0.numRetries 2474 # Number of retries
-system.l0subsys5.tester0.retryTicks 63721903 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys5.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys5.tester1.numPackets 66053 # Number of packets generated
-system.l0subsys5.tester1.numRetries 2552 # Number of retries
-system.l0subsys5.tester1.retryTicks 62099800 # Time spent waiting due to back-pressure (ticks)
-system.l0subsys5.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.l0subsys5.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys5.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys5.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l0subsys5.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l0subsys5.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l0subsys5.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l0subsys5.xbar.trans_dist::ReadReq 85318 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::ReadResp 80121 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 5196 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::WriteReq 46953 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::WriteResp 46953 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::WritebackDirty 23264 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::CleanEvict 76398 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::UpgradeReq 16610 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::ReadExReq 21094 # Transaction distribution
-system.l0subsys5.xbar.trans_dist::ReadSharedReq 27416 # Transaction distribution
-system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 132435 # Packet count per connected master and slave (bytes)
-system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 132106 # Packet count per connected master and slave (bytes)
-system.l0subsys5.xbar.pkt_count::total 264541 # Packet count per connected master and slave (bytes)
-system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 529736 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 528424 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys5.xbar.pkt_size::total 1058160 # Cumulative packet size per connected master and slave (bytes)
-system.l0subsys5.xbar.snoops 164782 # Total snoops (count)
-system.l0subsys5.xbar.snoopTraffic 1488896 # Total snoop traffic (bytes)
-system.l0subsys5.xbar.snoop_fanout::samples 299602 # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::mean 0 # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::stdev 0 # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::0 299602 100.00% 100.00% # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::max_value 0 # Request fanout histogram
-system.l0subsys5.xbar.snoop_fanout::total 299602 # Request fanout histogram
-system.l0subsys5.xbar.reqLayer0.occupancy 249141230 # Layer occupancy (ticks)
-system.l0subsys5.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.l0subsys5.xbar.respLayer0.occupancy 114371637 # Layer occupancy (ticks)
-system.l0subsys5.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
-system.l0subsys5.xbar.respLayer1.occupancy 114160981 # Layer occupancy (ticks)
-system.l0subsys5.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
-system.l1subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys0.cache0.tags.replacements 63572 # number of replacements
-system.l1subsys0.cache0.tags.tagsinuse 502.721619 # Cycle average of tags in use
-system.l1subsys0.cache0.tags.total_refs 28948 # Total number of references to valid blocks.
-system.l1subsys0.cache0.tags.sampled_refs 64070 # Sample count of references to valid blocks.
-system.l1subsys0.cache0.tags.avg_refs 0.451818 # Average number of references to valid blocks.
-system.l1subsys0.cache0.tags.warmup_cycle 175326000 # Cycle when the warmup percentage was hit.
-system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester0 252.816838 # Average occupied blocks per requestor
-system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester1 249.904781 # Average occupied blocks per requestor
-system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester0 0.493783 # Average percentage of cache occupancy
-system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester1 0.488095 # Average percentage of cache occupancy
-system.l1subsys0.cache0.tags.occ_percent::total 0.981878 # Average percentage of cache occupancy
-system.l1subsys0.cache0.tags.occ_task_id_blocks::1024 498 # Occupied blocks per task id
-system.l1subsys0.cache0.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.l1subsys0.cache0.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id
-system.l1subsys0.cache0.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
-system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.972656 # Percentage of cache occupancy per task id
-system.l1subsys0.cache0.tags.tag_accesses 622356 # Number of tag accesses
-system.l1subsys0.cache0.tags.data_accesses 622356 # Number of data accesses
-system.l1subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9054 # number of ReadReq hits
-system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9218 # number of ReadReq hits
-system.l1subsys0.cache0.ReadReq_hits::total 18272 # number of ReadReq hits
-system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester0 1043 # number of WriteReq hits
-system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester1 1065 # number of WriteReq hits
-system.l1subsys0.cache0.WriteReq_hits::total 2108 # number of WriteReq hits
-system.l1subsys0.cache0.demand_hits::l0subsys0.tester0 10097 # number of demand (read+write) hits
-system.l1subsys0.cache0.demand_hits::l0subsys0.tester1 10283 # number of demand (read+write) hits
-system.l1subsys0.cache0.demand_hits::total 20380 # number of demand (read+write) hits
-system.l1subsys0.cache0.overall_hits::l0subsys0.tester0 10097 # number of overall hits
-system.l1subsys0.cache0.overall_hits::l0subsys0.tester1 10283 # number of overall hits
-system.l1subsys0.cache0.overall_hits::total 20380 # number of overall hits
-system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester0 32756 # number of ReadReq misses
-system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester1 33049 # number of ReadReq misses
-system.l1subsys0.cache0.ReadReq_misses::total 65805 # number of ReadReq misses
-system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester0 22181 # number of WriteReq misses
-system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester1 22262 # number of WriteReq misses
-system.l1subsys0.cache0.WriteReq_misses::total 44443 # number of WriteReq misses
-system.l1subsys0.cache0.demand_misses::l0subsys0.tester0 54937 # number of demand (read+write) misses
-system.l1subsys0.cache0.demand_misses::l0subsys0.tester1 55311 # number of demand (read+write) misses
-system.l1subsys0.cache0.demand_misses::total 110248 # number of demand (read+write) misses
-system.l1subsys0.cache0.overall_misses::l0subsys0.tester0 54937 # number of overall misses
-system.l1subsys0.cache0.overall_misses::l0subsys0.tester1 55311 # number of overall misses
-system.l1subsys0.cache0.overall_misses::total 110248 # number of overall misses
-system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester0 3001619678 # number of ReadReq miss cycles
-system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester1 2958296743 # number of ReadReq miss cycles
-system.l1subsys0.cache0.ReadReq_miss_latency::total 5959916421 # number of ReadReq miss cycles
-system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester0 1842729426 # number of WriteReq miss cycles
-system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester1 1811086120 # number of WriteReq miss cycles
-system.l1subsys0.cache0.WriteReq_miss_latency::total 3653815546 # number of WriteReq miss cycles
-system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester0 4844349104 # number of demand (read+write) miss cycles
-system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester1 4769382863 # number of demand (read+write) miss cycles
-system.l1subsys0.cache0.demand_miss_latency::total 9613731967 # number of demand (read+write) miss cycles
-system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester0 4844349104 # number of overall miss cycles
-system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester1 4769382863 # number of overall miss cycles
-system.l1subsys0.cache0.overall_miss_latency::total 9613731967 # number of overall miss cycles
-system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester0 41810 # number of ReadReq accesses(hits+misses)
-system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester1 42267 # number of ReadReq accesses(hits+misses)
-system.l1subsys0.cache0.ReadReq_accesses::total 84077 # number of ReadReq accesses(hits+misses)
-system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester0 23224 # number of WriteReq accesses(hits+misses)
-system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester1 23327 # number of WriteReq accesses(hits+misses)
-system.l1subsys0.cache0.WriteReq_accesses::total 46551 # number of WriteReq accesses(hits+misses)
-system.l1subsys0.cache0.demand_accesses::l0subsys0.tester0 65034 # number of demand (read+write) accesses
-system.l1subsys0.cache0.demand_accesses::l0subsys0.tester1 65594 # number of demand (read+write) accesses
-system.l1subsys0.cache0.demand_accesses::total 130628 # number of demand (read+write) accesses
-system.l1subsys0.cache0.overall_accesses::l0subsys0.tester0 65034 # number of overall (read+write) accesses
-system.l1subsys0.cache0.overall_accesses::l0subsys0.tester1 65594 # number of overall (read+write) accesses
-system.l1subsys0.cache0.overall_accesses::total 130628 # number of overall (read+write) accesses
-system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester0 0.783449 # miss rate for ReadReq accesses
-system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester1 0.781910 # miss rate for ReadReq accesses
-system.l1subsys0.cache0.ReadReq_miss_rate::total 0.782675 # miss rate for ReadReq accesses
-system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester0 0.955090 # miss rate for WriteReq accesses
-system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester1 0.954345 # miss rate for WriteReq accesses
-system.l1subsys0.cache0.WriteReq_miss_rate::total 0.954716 # miss rate for WriteReq accesses
-system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester0 0.844743 # miss rate for demand accesses
-system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester1 0.843233 # miss rate for demand accesses
-system.l1subsys0.cache0.demand_miss_rate::total 0.843984 # miss rate for demand accesses
-system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester0 0.844743 # miss rate for overall accesses
-system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester1 0.843233 # miss rate for overall accesses
-system.l1subsys0.cache0.overall_miss_rate::total 0.843984 # miss rate for overall accesses
-system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester0 91635.721028 # average ReadReq miss latency
-system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester1 89512.443432 # average ReadReq miss latency
-system.l1subsys0.cache0.ReadReq_avg_miss_latency::total 90569.355231 # average ReadReq miss latency
-system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester0 83076.931879 # average WriteReq miss latency
-system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester1 81353.253077 # average WriteReq miss latency
-system.l1subsys0.cache0.WriteReq_avg_miss_latency::total 82213.521724 # average WriteReq miss latency
-system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester0 88180.080893 # average overall miss latency
-system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester1 86228.469256 # average overall miss latency
-system.l1subsys0.cache0.demand_avg_miss_latency::total 87200.964798 # average overall miss latency
-system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester0 88180.080893 # average overall miss latency
-system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester1 86228.469256 # average overall miss latency
-system.l1subsys0.cache0.overall_avg_miss_latency::total 87200.964798 # average overall miss latency
-system.l1subsys0.cache0.blocked_cycles::no_mshrs 255047 # number of cycles access was blocked
-system.l1subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l1subsys0.cache0.blocked::no_mshrs 7903 # number of cycles access was blocked
-system.l1subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked
-system.l1subsys0.cache0.avg_blocked_cycles::no_mshrs 32.272175 # average number of cycles each access was blocked
-system.l1subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l1subsys0.cache0.writebacks::writebacks 22887 # number of writebacks
-system.l1subsys0.cache0.writebacks::total 22887 # number of writebacks
-system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester0 1216 # number of ReadReq MSHR hits
-system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester1 1243 # number of ReadReq MSHR hits
-system.l1subsys0.cache0.ReadReq_mshr_hits::total 2459 # number of ReadReq MSHR hits
-system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester0 661 # number of WriteReq MSHR hits
-system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester1 689 # number of WriteReq MSHR hits
-system.l1subsys0.cache0.WriteReq_mshr_hits::total 1350 # number of WriteReq MSHR hits
-system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester0 1877 # number of demand (read+write) MSHR hits
-system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester1 1932 # number of demand (read+write) MSHR hits
-system.l1subsys0.cache0.demand_mshr_hits::total 3809 # number of demand (read+write) MSHR hits
-system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester0 1877 # number of overall MSHR hits
-system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester1 1932 # number of overall MSHR hits
-system.l1subsys0.cache0.overall_mshr_hits::total 3809 # number of overall MSHR hits
-system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester0 31540 # number of ReadReq MSHR misses
-system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester1 31806 # number of ReadReq MSHR misses
-system.l1subsys0.cache0.ReadReq_mshr_misses::total 63346 # number of ReadReq MSHR misses
-system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester0 21520 # number of WriteReq MSHR misses
-system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester1 21573 # number of WriteReq MSHR misses
-system.l1subsys0.cache0.WriteReq_mshr_misses::total 43093 # number of WriteReq MSHR misses
-system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester0 53060 # number of demand (read+write) MSHR misses
-system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester1 53379 # number of demand (read+write) MSHR misses
-system.l1subsys0.cache0.demand_mshr_misses::total 106439 # number of demand (read+write) MSHR misses
-system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester0 53060 # number of overall MSHR misses
-system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester1 53379 # number of overall MSHR misses
-system.l1subsys0.cache0.overall_mshr_misses::total 106439 # number of overall MSHR misses
-system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester0 2943016198 # number of ReadReq MSHR miss cycles
-system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester1 2898664159 # number of ReadReq MSHR miss cycles
-system.l1subsys0.cache0.ReadReq_mshr_miss_latency::total 5841680357 # number of ReadReq MSHR miss cycles
-system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester0 1812017394 # number of WriteReq MSHR miss cycles
-system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester1 1780656760 # number of WriteReq MSHR miss cycles
-system.l1subsys0.cache0.WriteReq_mshr_miss_latency::total 3592674154 # number of WriteReq MSHR miss cycles
-system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester0 4755033592 # number of demand (read+write) MSHR miss cycles
-system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester1 4679320919 # number of demand (read+write) MSHR miss cycles
-system.l1subsys0.cache0.demand_mshr_miss_latency::total 9434354511 # number of demand (read+write) MSHR miss cycles
-system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester0 4755033592 # number of overall MSHR miss cycles
-system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester1 4679320919 # number of overall MSHR miss cycles
-system.l1subsys0.cache0.overall_mshr_miss_latency::total 9434354511 # number of overall MSHR miss cycles
-system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester0 0.754365 # mshr miss rate for ReadReq accesses
-system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester1 0.752502 # mshr miss rate for ReadReq accesses
-system.l1subsys0.cache0.ReadReq_mshr_miss_rate::total 0.753428 # mshr miss rate for ReadReq accesses
-system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester0 0.926628 # mshr miss rate for WriteReq accesses
-system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester1 0.924808 # mshr miss rate for WriteReq accesses
-system.l1subsys0.cache0.WriteReq_mshr_miss_rate::total 0.925716 # mshr miss rate for WriteReq accesses
-system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester0 0.815881 # mshr miss rate for demand accesses
-system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester1 0.813779 # mshr miss rate for demand accesses
-system.l1subsys0.cache0.demand_mshr_miss_rate::total 0.814825 # mshr miss rate for demand accesses
-system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester0 0.815881 # mshr miss rate for overall accesses
-system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester1 0.813779 # mshr miss rate for overall accesses
-system.l1subsys0.cache0.overall_mshr_miss_rate::total 0.814825 # mshr miss rate for overall accesses
-system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester0 93310.596005 # average ReadReq mshr miss latency
-system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester1 91135.765547 # average ReadReq mshr miss latency
-system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 92218.614546 # average ReadReq mshr miss latency
-system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester0 84201.551766 # average WriteReq mshr miss latency
-system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester1 82540.989199 # average WriteReq mshr miss latency
-system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 83370.249321 # average WriteReq mshr miss latency
-system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester0 89616.162684 # average overall mshr miss latency
-system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester1 87662.206467 # average overall mshr miss latency
-system.l1subsys0.cache0.demand_avg_mshr_miss_latency::total 88636.256551 # average overall mshr miss latency
-system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 89616.162684 # average overall mshr miss latency
-system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 87662.206467 # average overall mshr miss latency
-system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 88636.256551 # average overall mshr miss latency
-system.l1subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys0.cache1.tags.replacements 65828 # number of replacements
-system.l1subsys0.cache1.tags.tagsinuse 503.967314 # Cycle average of tags in use
-system.l1subsys0.cache1.tags.total_refs 28277 # Total number of references to valid blocks.
-system.l1subsys0.cache1.tags.sampled_refs 66340 # Sample count of references to valid blocks.
-system.l1subsys0.cache1.tags.avg_refs 0.426244 # Average number of references to valid blocks.
-system.l1subsys0.cache1.tags.warmup_cycle 396891000 # Cycle when the warmup percentage was hit.
-system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 249.180331 # Average occupied blocks per requestor
-system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 254.786982 # Average occupied blocks per requestor
-system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.486680 # Average percentage of cache occupancy
-system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.497631 # Average percentage of cache occupancy
-system.l1subsys0.cache1.tags.occ_percent::total 0.984311 # Average percentage of cache occupancy
-system.l1subsys0.cache1.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.l1subsys0.cache1.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
-system.l1subsys0.cache1.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
-system.l1subsys0.cache1.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
-system.l1subsys0.cache1.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.l1subsys0.cache1.tags.tag_accesses 626837 # Number of tag accesses
-system.l1subsys0.cache1.tags.data_accesses 626837 # Number of data accesses
-system.l1subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester0 8196 # number of ReadReq hits
-system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester1 9493 # number of ReadReq hits
-system.l1subsys0.cache1.ReadReq_hits::total 17689 # number of ReadReq hits
-system.l1subsys0.cache1.WriteReq_hits::l0subsys1.tester0 993 # number of WriteReq hits
-system.l1subsys0.cache1.WriteReq_hits::l0subsys1.tester1 1169 # number of WriteReq hits
-system.l1subsys0.cache1.WriteReq_hits::total 2162 # number of WriteReq hits
-system.l1subsys0.cache1.demand_hits::l0subsys1.tester0 9189 # number of demand (read+write) hits
-system.l1subsys0.cache1.demand_hits::l0subsys1.tester1 10662 # number of demand (read+write) hits
-system.l1subsys0.cache1.demand_hits::total 19851 # number of demand (read+write) hits
-system.l1subsys0.cache1.overall_hits::l0subsys1.tester0 9189 # number of overall hits
-system.l1subsys0.cache1.overall_hits::l0subsys1.tester1 10662 # number of overall hits
-system.l1subsys0.cache1.overall_hits::total 19851 # number of overall hits
-system.l1subsys0.cache1.ReadReq_misses::l0subsys1.tester0 32989 # number of ReadReq misses
-system.l1subsys0.cache1.ReadReq_misses::l0subsys1.tester1 33781 # number of ReadReq misses
-system.l1subsys0.cache1.ReadReq_misses::total 66770 # number of ReadReq misses
-system.l1subsys0.cache1.WriteReq_misses::l0subsys1.tester0 22056 # number of WriteReq misses
-system.l1subsys0.cache1.WriteReq_misses::l0subsys1.tester1 22794 # number of WriteReq misses
-system.l1subsys0.cache1.WriteReq_misses::total 44850 # number of WriteReq misses
-system.l1subsys0.cache1.demand_misses::l0subsys1.tester0 55045 # number of demand (read+write) misses
-system.l1subsys0.cache1.demand_misses::l0subsys1.tester1 56575 # number of demand (read+write) misses
-system.l1subsys0.cache1.demand_misses::total 111620 # number of demand (read+write) misses
-system.l1subsys0.cache1.overall_misses::l0subsys1.tester0 55045 # number of overall misses
-system.l1subsys0.cache1.overall_misses::l0subsys1.tester1 56575 # number of overall misses
-system.l1subsys0.cache1.overall_misses::total 111620 # number of overall misses
-system.l1subsys0.cache1.ReadReq_miss_latency::l0subsys1.tester0 2994338952 # number of ReadReq miss cycles
-system.l1subsys0.cache1.ReadReq_miss_latency::l0subsys1.tester1 3071169807 # number of ReadReq miss cycles
-system.l1subsys0.cache1.ReadReq_miss_latency::total 6065508759 # number of ReadReq miss cycles
-system.l1subsys0.cache1.WriteReq_miss_latency::l0subsys1.tester0 1858284940 # number of WriteReq miss cycles
-system.l1subsys0.cache1.WriteReq_miss_latency::l0subsys1.tester1 1885823655 # number of WriteReq miss cycles
-system.l1subsys0.cache1.WriteReq_miss_latency::total 3744108595 # number of WriteReq miss cycles
-system.l1subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4852623892 # number of demand (read+write) miss cycles
-system.l1subsys0.cache1.demand_miss_latency::l0subsys1.tester1 4956993462 # number of demand (read+write) miss cycles
-system.l1subsys0.cache1.demand_miss_latency::total 9809617354 # number of demand (read+write) miss cycles
-system.l1subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4852623892 # number of overall miss cycles
-system.l1subsys0.cache1.overall_miss_latency::l0subsys1.tester1 4956993462 # number of overall miss cycles
-system.l1subsys0.cache1.overall_miss_latency::total 9809617354 # number of overall miss cycles
-system.l1subsys0.cache1.ReadReq_accesses::l0subsys1.tester0 41185 # number of ReadReq accesses(hits+misses)
-system.l1subsys0.cache1.ReadReq_accesses::l0subsys1.tester1 43274 # number of ReadReq accesses(hits+misses)
-system.l1subsys0.cache1.ReadReq_accesses::total 84459 # number of ReadReq accesses(hits+misses)
-system.l1subsys0.cache1.WriteReq_accesses::l0subsys1.tester0 23049 # number of WriteReq accesses(hits+misses)
-system.l1subsys0.cache1.WriteReq_accesses::l0subsys1.tester1 23963 # number of WriteReq accesses(hits+misses)
-system.l1subsys0.cache1.WriteReq_accesses::total 47012 # number of WriteReq accesses(hits+misses)
-system.l1subsys0.cache1.demand_accesses::l0subsys1.tester0 64234 # number of demand (read+write) accesses
-system.l1subsys0.cache1.demand_accesses::l0subsys1.tester1 67237 # number of demand (read+write) accesses
-system.l1subsys0.cache1.demand_accesses::total 131471 # number of demand (read+write) accesses
-system.l1subsys0.cache1.overall_accesses::l0subsys1.tester0 64234 # number of overall (read+write) accesses
-system.l1subsys0.cache1.overall_accesses::l0subsys1.tester1 67237 # number of overall (read+write) accesses
-system.l1subsys0.cache1.overall_accesses::total 131471 # number of overall (read+write) accesses
-system.l1subsys0.cache1.ReadReq_miss_rate::l0subsys1.tester0 0.800996 # miss rate for ReadReq accesses
-system.l1subsys0.cache1.ReadReq_miss_rate::l0subsys1.tester1 0.780630 # miss rate for ReadReq accesses
-system.l1subsys0.cache1.ReadReq_miss_rate::total 0.790561 # miss rate for ReadReq accesses
-system.l1subsys0.cache1.WriteReq_miss_rate::l0subsys1.tester0 0.956918 # miss rate for WriteReq accesses
-system.l1subsys0.cache1.WriteReq_miss_rate::l0subsys1.tester1 0.951216 # miss rate for WriteReq accesses
-system.l1subsys0.cache1.WriteReq_miss_rate::total 0.954012 # miss rate for WriteReq accesses
-system.l1subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.856945 # miss rate for demand accesses
-system.l1subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.841427 # miss rate for demand accesses
-system.l1subsys0.cache1.demand_miss_rate::total 0.849009 # miss rate for demand accesses
-system.l1subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.856945 # miss rate for overall accesses
-system.l1subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.841427 # miss rate for overall accesses
-system.l1subsys0.cache1.overall_miss_rate::total 0.849009 # miss rate for overall accesses
-system.l1subsys0.cache1.ReadReq_avg_miss_latency::l0subsys1.tester0 90767.799933 # average ReadReq miss latency
-system.l1subsys0.cache1.ReadReq_avg_miss_latency::l0subsys1.tester1 90914.117610 # average ReadReq miss latency
-system.l1subsys0.cache1.ReadReq_avg_miss_latency::total 90841.826554 # average ReadReq miss latency
-system.l1subsys0.cache1.WriteReq_avg_miss_latency::l0subsys1.tester0 84253.035002 # average WriteReq miss latency
-system.l1subsys0.cache1.WriteReq_avg_miss_latency::l0subsys1.tester1 82733.335746 # average WriteReq miss latency
-system.l1subsys0.cache1.WriteReq_avg_miss_latency::total 83480.682163 # average WriteReq miss latency
-system.l1subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 88157.396530 # average overall miss latency
-system.l1subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 87618.090358 # average overall miss latency
-system.l1subsys0.cache1.demand_avg_miss_latency::total 87884.047250 # average overall miss latency
-system.l1subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 88157.396530 # average overall miss latency
-system.l1subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 87618.090358 # average overall miss latency
-system.l1subsys0.cache1.overall_avg_miss_latency::total 87884.047250 # average overall miss latency
-system.l1subsys0.cache1.blocked_cycles::no_mshrs 279679 # number of cycles access was blocked
-system.l1subsys0.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l1subsys0.cache1.blocked::no_mshrs 8747 # number of cycles access was blocked
-system.l1subsys0.cache1.blocked::no_targets 0 # number of cycles access was blocked
-system.l1subsys0.cache1.avg_blocked_cycles::no_mshrs 31.974277 # average number of cycles each access was blocked
-system.l1subsys0.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l1subsys0.cache1.writebacks::writebacks 23700 # number of writebacks
-system.l1subsys0.cache1.writebacks::total 23700 # number of writebacks
-system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester0 1375 # number of ReadReq MSHR hits
-system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester1 1361 # number of ReadReq MSHR hits
-system.l1subsys0.cache1.ReadReq_mshr_hits::total 2736 # number of ReadReq MSHR hits
-system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester0 770 # number of WriteReq MSHR hits
-system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester1 782 # number of WriteReq MSHR hits
-system.l1subsys0.cache1.WriteReq_mshr_hits::total 1552 # number of WriteReq MSHR hits
-system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 2145 # number of demand (read+write) MSHR hits
-system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 2143 # number of demand (read+write) MSHR hits
-system.l1subsys0.cache1.demand_mshr_hits::total 4288 # number of demand (read+write) MSHR hits
-system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 2145 # number of overall MSHR hits
-system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 2143 # number of overall MSHR hits
-system.l1subsys0.cache1.overall_mshr_hits::total 4288 # number of overall MSHR hits
-system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester0 31614 # number of ReadReq MSHR misses
-system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester1 32420 # number of ReadReq MSHR misses
-system.l1subsys0.cache1.ReadReq_mshr_misses::total 64034 # number of ReadReq MSHR misses
-system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester0 21286 # number of WriteReq MSHR misses
-system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester1 22012 # number of WriteReq MSHR misses
-system.l1subsys0.cache1.WriteReq_mshr_misses::total 43298 # number of WriteReq MSHR misses
-system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 52900 # number of demand (read+write) MSHR misses
-system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 54432 # number of demand (read+write) MSHR misses
-system.l1subsys0.cache1.demand_mshr_misses::total 107332 # number of demand (read+write) MSHR misses
-system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 52900 # number of overall MSHR misses
-system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester1 54432 # number of overall MSHR misses
-system.l1subsys0.cache1.overall_mshr_misses::total 107332 # number of overall MSHR misses
-system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester0 2931797311 # number of ReadReq MSHR miss cycles
-system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester1 3008653517 # number of ReadReq MSHR miss cycles
-system.l1subsys0.cache1.ReadReq_mshr_miss_latency::total 5940450828 # number of ReadReq MSHR miss cycles
-system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester0 1826715134 # number of WriteReq MSHR miss cycles
-system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester1 1854734052 # number of WriteReq MSHR miss cycles
-system.l1subsys0.cache1.WriteReq_mshr_miss_latency::total 3681449186 # number of WriteReq MSHR miss cycles
-system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 4758512445 # number of demand (read+write) MSHR miss cycles
-system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 4863387569 # number of demand (read+write) MSHR miss cycles
-system.l1subsys0.cache1.demand_mshr_miss_latency::total 9621900014 # number of demand (read+write) MSHR miss cycles
-system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 4758512445 # number of overall MSHR miss cycles
-system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 4863387569 # number of overall MSHR miss cycles
-system.l1subsys0.cache1.overall_mshr_miss_latency::total 9621900014 # number of overall MSHR miss cycles
-system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester0 0.767610 # mshr miss rate for ReadReq accesses
-system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester1 0.749180 # mshr miss rate for ReadReq accesses
-system.l1subsys0.cache1.ReadReq_mshr_miss_rate::total 0.758167 # mshr miss rate for ReadReq accesses
-system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester0 0.923511 # mshr miss rate for WriteReq accesses
-system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester1 0.918583 # mshr miss rate for WriteReq accesses
-system.l1subsys0.cache1.WriteReq_mshr_miss_rate::total 0.920999 # mshr miss rate for WriteReq accesses
-system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.823551 # mshr miss rate for demand accesses
-system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.809554 # mshr miss rate for demand accesses
-system.l1subsys0.cache1.demand_mshr_miss_rate::total 0.816393 # mshr miss rate for demand accesses
-system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.823551 # mshr miss rate for overall accesses
-system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.809554 # mshr miss rate for overall accesses
-system.l1subsys0.cache1.overall_mshr_miss_rate::total 0.816393 # mshr miss rate for overall accesses
-system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester0 92737.309768 # average ReadReq mshr miss latency
-system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester1 92802.391024 # average ReadReq mshr miss latency
-system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::total 92770.259987 # average ReadReq mshr miss latency
-system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester0 85817.679883 # average WriteReq mshr miss latency
-system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester1 84260.133200 # average WriteReq mshr miss latency
-system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::total 85025.848446 # average WriteReq mshr miss latency
-system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 89952.976276 # average overall mshr miss latency
-system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 89347.949166 # average overall mshr miss latency
-system.l1subsys0.cache1.demand_avg_mshr_miss_latency::total 89646.144803 # average overall mshr miss latency
-system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 89952.976276 # average overall mshr miss latency
-system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 89347.949166 # average overall mshr miss latency
-system.l1subsys0.cache1.overall_avg_mshr_miss_latency::total 89646.144803 # average overall mshr miss latency
-system.l1subsys0.xbar.snoop_filter.tot_requests 345070 # Total number of requests made to the snoop filter.
-system.l1subsys0.xbar.snoop_filter.hit_single_requests 163003 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l1subsys0.xbar.snoop_filter.hit_multi_requests 8917 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l1subsys0.xbar.snoop_filter.tot_snoops 156506 # Total number of snoops made to the snoop filter.
-system.l1subsys0.xbar.snoop_filter.hit_single_snoops 138247 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 18259 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l1subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys0.xbar.trans_dist::ReadResp 154272 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 4493 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::WritebackDirty 92411 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::CleanEvict 188842 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::UpgradeReq 38589 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::UpgradeResp 23198 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::ReadExReq 102825 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::ReadExResp 93371 # Transaction distribution
-system.l1subsys0.xbar.trans_dist::ReadSharedReq 169934 # Transaction distribution
-system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 301161 # Packet count per connected master and slave (bytes)
-system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 304465 # Packet count per connected master and slave (bytes)
-system.l1subsys0.xbar.pkt_count::total 605626 # Packet count per connected master and slave (bytes)
-system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 9099264 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 9173504 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys0.xbar.pkt_size::total 18272768 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys0.xbar.snoops 321974 # Total snoops (count)
-system.l1subsys0.xbar.snoopTraffic 7063936 # Total snoop traffic (bytes)
-system.l1subsys0.xbar.snoop_fanout::samples 463201 # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::mean 0.438401 # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::stdev 0.570127 # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::0 278392 60.10% 60.10% # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::1 166550 35.96% 96.06% # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::2 18259 3.94% 100.00% # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::max_value 2 # Request fanout histogram
-system.l1subsys0.xbar.snoop_fanout::total 463201 # Request fanout histogram
-system.l1subsys0.xbar.reqLayer0.occupancy 536944163 # Layer occupancy (ticks)
-system.l1subsys0.xbar.reqLayer0.utilization 5.4 # Layer utilization (%)
-system.l1subsys0.xbar.snoopLayer0.occupancy 181542409 # Layer occupancy (ticks)
-system.l1subsys0.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%)
-system.l1subsys0.xbar.respLayer0.occupancy 313026103 # Layer occupancy (ticks)
-system.l1subsys0.xbar.respLayer0.utilization 3.1 # Layer utilization (%)
-system.l1subsys0.xbar.respLayer1.occupancy 316235883 # Layer occupancy (ticks)
-system.l1subsys0.xbar.respLayer1.utilization 3.2 # Layer utilization (%)
-system.l1subsys1.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys1.cache0.tags.replacements 62894 # number of replacements
-system.l1subsys1.cache0.tags.tagsinuse 502.360512 # Cycle average of tags in use
-system.l1subsys1.cache0.tags.total_refs 30318 # Total number of references to valid blocks.
-system.l1subsys1.cache0.tags.sampled_refs 63398 # Sample count of references to valid blocks.
-system.l1subsys1.cache0.tags.avg_refs 0.478217 # Average number of references to valid blocks.
-system.l1subsys1.cache0.tags.warmup_cycle 195013000 # Cycle when the warmup percentage was hit.
-system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester0 249.855893 # Average occupied blocks per requestor
-system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester1 252.504619 # Average occupied blocks per requestor
-system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester0 0.488000 # Average percentage of cache occupancy
-system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester1 0.493173 # Average percentage of cache occupancy
-system.l1subsys1.cache0.tags.occ_percent::total 0.981173 # Average percentage of cache occupancy
-system.l1subsys1.cache0.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
-system.l1subsys1.cache0.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
-system.l1subsys1.cache0.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id
-system.l1subsys1.cache0.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
-system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
-system.l1subsys1.cache0.tags.tag_accesses 623844 # Number of tag accesses
-system.l1subsys1.cache0.tags.data_accesses 623844 # Number of data accesses
-system.l1subsys1.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 9625 # number of ReadReq hits
-system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9444 # number of ReadReq hits
-system.l1subsys1.cache0.ReadReq_hits::total 19069 # number of ReadReq hits
-system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester0 1133 # number of WriteReq hits
-system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester1 1194 # number of WriteReq hits
-system.l1subsys1.cache0.WriteReq_hits::total 2327 # number of WriteReq hits
-system.l1subsys1.cache0.demand_hits::l0subsys2.tester0 10758 # number of demand (read+write) hits
-system.l1subsys1.cache0.demand_hits::l0subsys2.tester1 10638 # number of demand (read+write) hits
-system.l1subsys1.cache0.demand_hits::total 21396 # number of demand (read+write) hits
-system.l1subsys1.cache0.overall_hits::l0subsys2.tester0 10758 # number of overall hits
-system.l1subsys1.cache0.overall_hits::l0subsys2.tester1 10638 # number of overall hits
-system.l1subsys1.cache0.overall_hits::total 21396 # number of overall hits
-system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester0 32686 # number of ReadReq misses
-system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester1 32579 # number of ReadReq misses
-system.l1subsys1.cache0.ReadReq_misses::total 65265 # number of ReadReq misses
-system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester0 22368 # number of WriteReq misses
-system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester1 22220 # number of WriteReq misses
-system.l1subsys1.cache0.WriteReq_misses::total 44588 # number of WriteReq misses
-system.l1subsys1.cache0.demand_misses::l0subsys2.tester0 55054 # number of demand (read+write) misses
-system.l1subsys1.cache0.demand_misses::l0subsys2.tester1 54799 # number of demand (read+write) misses
-system.l1subsys1.cache0.demand_misses::total 109853 # number of demand (read+write) misses
-system.l1subsys1.cache0.overall_misses::l0subsys2.tester0 55054 # number of overall misses
-system.l1subsys1.cache0.overall_misses::l0subsys2.tester1 54799 # number of overall misses
-system.l1subsys1.cache0.overall_misses::total 109853 # number of overall misses
-system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester0 2952180938 # number of ReadReq miss cycles
-system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester1 2978156965 # number of ReadReq miss cycles
-system.l1subsys1.cache0.ReadReq_miss_latency::total 5930337903 # number of ReadReq miss cycles
-system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester0 1826783335 # number of WriteReq miss cycles
-system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester1 1815663793 # number of WriteReq miss cycles
-system.l1subsys1.cache0.WriteReq_miss_latency::total 3642447128 # number of WriteReq miss cycles
-system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester0 4778964273 # number of demand (read+write) miss cycles
-system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester1 4793820758 # number of demand (read+write) miss cycles
-system.l1subsys1.cache0.demand_miss_latency::total 9572785031 # number of demand (read+write) miss cycles
-system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester0 4778964273 # number of overall miss cycles
-system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester1 4793820758 # number of overall miss cycles
-system.l1subsys1.cache0.overall_miss_latency::total 9572785031 # number of overall miss cycles
-system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester0 42311 # number of ReadReq accesses(hits+misses)
-system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester1 42023 # number of ReadReq accesses(hits+misses)
-system.l1subsys1.cache0.ReadReq_accesses::total 84334 # number of ReadReq accesses(hits+misses)
-system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester0 23501 # number of WriteReq accesses(hits+misses)
-system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester1 23414 # number of WriteReq accesses(hits+misses)
-system.l1subsys1.cache0.WriteReq_accesses::total 46915 # number of WriteReq accesses(hits+misses)
-system.l1subsys1.cache0.demand_accesses::l0subsys2.tester0 65812 # number of demand (read+write) accesses
-system.l1subsys1.cache0.demand_accesses::l0subsys2.tester1 65437 # number of demand (read+write) accesses
-system.l1subsys1.cache0.demand_accesses::total 131249 # number of demand (read+write) accesses
-system.l1subsys1.cache0.overall_accesses::l0subsys2.tester0 65812 # number of overall (read+write) accesses
-system.l1subsys1.cache0.overall_accesses::l0subsys2.tester1 65437 # number of overall (read+write) accesses
-system.l1subsys1.cache0.overall_accesses::total 131249 # number of overall (read+write) accesses
-system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester0 0.772518 # miss rate for ReadReq accesses
-system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester1 0.775266 # miss rate for ReadReq accesses
-system.l1subsys1.cache0.ReadReq_miss_rate::total 0.773887 # miss rate for ReadReq accesses
-system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester0 0.951789 # miss rate for WriteReq accesses
-system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester1 0.949005 # miss rate for WriteReq accesses
-system.l1subsys1.cache0.WriteReq_miss_rate::total 0.950400 # miss rate for WriteReq accesses
-system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester0 0.836534 # miss rate for demand accesses
-system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester1 0.837431 # miss rate for demand accesses
-system.l1subsys1.cache0.demand_miss_rate::total 0.836982 # miss rate for demand accesses
-system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester0 0.836534 # miss rate for overall accesses
-system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester1 0.837431 # miss rate for overall accesses
-system.l1subsys1.cache0.overall_miss_rate::total 0.836982 # miss rate for overall accesses
-system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester0 90319.431500 # average ReadReq miss latency
-system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester1 91413.394058 # average ReadReq miss latency
-system.l1subsys1.cache0.ReadReq_avg_miss_latency::total 90865.516019 # average ReadReq miss latency
-system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester0 81669.498167 # average WriteReq miss latency
-system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester1 81713.041989 # average WriteReq miss latency
-system.l1subsys1.cache0.WriteReq_avg_miss_latency::total 81691.197811 # average WriteReq miss latency
-system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester0 86805.032750 # average overall miss latency
-system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester1 87480.077337 # average overall miss latency
-system.l1subsys1.cache0.demand_avg_miss_latency::total 87141.771558 # average overall miss latency
-system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester0 86805.032750 # average overall miss latency
-system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester1 87480.077337 # average overall miss latency
-system.l1subsys1.cache0.overall_avg_miss_latency::total 87141.771558 # average overall miss latency
-system.l1subsys1.cache0.blocked_cycles::no_mshrs 273729 # number of cycles access was blocked
-system.l1subsys1.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l1subsys1.cache0.blocked::no_mshrs 8512 # number of cycles access was blocked
-system.l1subsys1.cache0.blocked::no_targets 0 # number of cycles access was blocked
-system.l1subsys1.cache0.avg_blocked_cycles::no_mshrs 32.158012 # average number of cycles each access was blocked
-system.l1subsys1.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l1subsys1.cache0.writebacks::writebacks 22484 # number of writebacks
-system.l1subsys1.cache0.writebacks::total 22484 # number of writebacks
-system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester0 1351 # number of ReadReq MSHR hits
-system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester1 1340 # number of ReadReq MSHR hits
-system.l1subsys1.cache0.ReadReq_mshr_hits::total 2691 # number of ReadReq MSHR hits
-system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester0 761 # number of WriteReq MSHR hits
-system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester1 811 # number of WriteReq MSHR hits
-system.l1subsys1.cache0.WriteReq_mshr_hits::total 1572 # number of WriteReq MSHR hits
-system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester0 2112 # number of demand (read+write) MSHR hits
-system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester1 2151 # number of demand (read+write) MSHR hits
-system.l1subsys1.cache0.demand_mshr_hits::total 4263 # number of demand (read+write) MSHR hits
-system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester0 2112 # number of overall MSHR hits
-system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester1 2151 # number of overall MSHR hits
-system.l1subsys1.cache0.overall_mshr_hits::total 4263 # number of overall MSHR hits
-system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester0 31335 # number of ReadReq MSHR misses
-system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester1 31239 # number of ReadReq MSHR misses
-system.l1subsys1.cache0.ReadReq_mshr_misses::total 62574 # number of ReadReq MSHR misses
-system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester0 21607 # number of WriteReq MSHR misses
-system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester1 21409 # number of WriteReq MSHR misses
-system.l1subsys1.cache0.WriteReq_mshr_misses::total 43016 # number of WriteReq MSHR misses
-system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester0 52942 # number of demand (read+write) MSHR misses
-system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester1 52648 # number of demand (read+write) MSHR misses
-system.l1subsys1.cache0.demand_mshr_misses::total 105590 # number of demand (read+write) MSHR misses
-system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester0 52942 # number of overall MSHR misses
-system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester1 52648 # number of overall MSHR misses
-system.l1subsys1.cache0.overall_mshr_misses::total 105590 # number of overall MSHR misses
-system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester0 2891074988 # number of ReadReq MSHR miss cycles
-system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester1 2917502752 # number of ReadReq MSHR miss cycles
-system.l1subsys1.cache0.ReadReq_mshr_miss_latency::total 5808577740 # number of ReadReq MSHR miss cycles
-system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester0 1795222958 # number of WriteReq MSHR miss cycles
-system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester1 1782842702 # number of WriteReq MSHR miss cycles
-system.l1subsys1.cache0.WriteReq_mshr_miss_latency::total 3578065660 # number of WriteReq MSHR miss cycles
-system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester0 4686297946 # number of demand (read+write) MSHR miss cycles
-system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester1 4700345454 # number of demand (read+write) MSHR miss cycles
-system.l1subsys1.cache0.demand_mshr_miss_latency::total 9386643400 # number of demand (read+write) MSHR miss cycles
-system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester0 4686297946 # number of overall MSHR miss cycles
-system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester1 4700345454 # number of overall MSHR miss cycles
-system.l1subsys1.cache0.overall_mshr_miss_latency::total 9386643400 # number of overall MSHR miss cycles
-system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester0 0.740588 # mshr miss rate for ReadReq accesses
-system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester1 0.743379 # mshr miss rate for ReadReq accesses
-system.l1subsys1.cache0.ReadReq_mshr_miss_rate::total 0.741978 # mshr miss rate for ReadReq accesses
-system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester0 0.919408 # mshr miss rate for WriteReq accesses
-system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester1 0.914367 # mshr miss rate for WriteReq accesses
-system.l1subsys1.cache0.WriteReq_mshr_miss_rate::total 0.916892 # mshr miss rate for WriteReq accesses
-system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester0 0.804443 # mshr miss rate for demand accesses
-system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester1 0.804560 # mshr miss rate for demand accesses
-system.l1subsys1.cache0.demand_mshr_miss_rate::total 0.804501 # mshr miss rate for demand accesses
-system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester0 0.804443 # mshr miss rate for overall accesses
-system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester1 0.804560 # mshr miss rate for overall accesses
-system.l1subsys1.cache0.overall_mshr_miss_rate::total 0.804501 # mshr miss rate for overall accesses
-system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester0 92263.443051 # average ReadReq mshr miss latency
-system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester1 93392.962387 # average ReadReq mshr miss latency
-system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::total 92827.336274 # average ReadReq mshr miss latency
-system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester0 83085.248207 # average WriteReq mshr miss latency
-system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester1 83275.384278 # average WriteReq mshr miss latency
-system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::total 83179.878650 # average WriteReq mshr miss latency
-system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester0 88517.584262 # average overall mshr miss latency
-system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester1 89278.708669 # average overall mshr miss latency
-system.l1subsys1.cache0.demand_avg_mshr_miss_latency::total 88897.086845 # average overall mshr miss latency
-system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 88517.584262 # average overall mshr miss latency
-system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89278.708669 # average overall mshr miss latency
-system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 88897.086845 # average overall mshr miss latency
-system.l1subsys1.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys1.cache1.tags.replacements 63994 # number of replacements
-system.l1subsys1.cache1.tags.tagsinuse 503.289590 # Cycle average of tags in use
-system.l1subsys1.cache1.tags.total_refs 28611 # Total number of references to valid blocks.
-system.l1subsys1.cache1.tags.sampled_refs 64495 # Sample count of references to valid blocks.
-system.l1subsys1.cache1.tags.avg_refs 0.443616 # Average number of references to valid blocks.
-system.l1subsys1.cache1.tags.warmup_cycle 273027000 # Cycle when the warmup percentage was hit.
-system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester0 252.648267 # Average occupied blocks per requestor
-system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester1 250.641323 # Average occupied blocks per requestor
-system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester0 0.493454 # Average percentage of cache occupancy
-system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester1 0.489534 # Average percentage of cache occupancy
-system.l1subsys1.cache1.tags.occ_percent::total 0.982987 # Average percentage of cache occupancy
-system.l1subsys1.cache1.tags.occ_task_id_blocks::1024 501 # Occupied blocks per task id
-system.l1subsys1.cache1.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
-system.l1subsys1.cache1.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
-system.l1subsys1.cache1.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
-system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id
-system.l1subsys1.cache1.tags.tag_accesses 622355 # Number of tag accesses
-system.l1subsys1.cache1.tags.data_accesses 622355 # Number of data accesses
-system.l1subsys1.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 8800 # number of ReadReq hits
-system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9171 # number of ReadReq hits
-system.l1subsys1.cache1.ReadReq_hits::total 17971 # number of ReadReq hits
-system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester0 1063 # number of WriteReq hits
-system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester1 1139 # number of WriteReq hits
-system.l1subsys1.cache1.WriteReq_hits::total 2202 # number of WriteReq hits
-system.l1subsys1.cache1.demand_hits::l0subsys3.tester0 9863 # number of demand (read+write) hits
-system.l1subsys1.cache1.demand_hits::l0subsys3.tester1 10310 # number of demand (read+write) hits
-system.l1subsys1.cache1.demand_hits::total 20173 # number of demand (read+write) hits
-system.l1subsys1.cache1.overall_hits::l0subsys3.tester0 9863 # number of overall hits
-system.l1subsys1.cache1.overall_hits::l0subsys3.tester1 10310 # number of overall hits
-system.l1subsys1.cache1.overall_hits::total 20173 # number of overall hits
-system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester0 33078 # number of ReadReq misses
-system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester1 32783 # number of ReadReq misses
-system.l1subsys1.cache1.ReadReq_misses::total 65861 # number of ReadReq misses
-system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester0 22069 # number of WriteReq misses
-system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester1 22457 # number of WriteReq misses
-system.l1subsys1.cache1.WriteReq_misses::total 44526 # number of WriteReq misses
-system.l1subsys1.cache1.demand_misses::l0subsys3.tester0 55147 # number of demand (read+write) misses
-system.l1subsys1.cache1.demand_misses::l0subsys3.tester1 55240 # number of demand (read+write) misses
-system.l1subsys1.cache1.demand_misses::total 110387 # number of demand (read+write) misses
-system.l1subsys1.cache1.overall_misses::l0subsys3.tester0 55147 # number of overall misses
-system.l1subsys1.cache1.overall_misses::l0subsys3.tester1 55240 # number of overall misses
-system.l1subsys1.cache1.overall_misses::total 110387 # number of overall misses
-system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester0 2996863885 # number of ReadReq miss cycles
-system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester1 2917691560 # number of ReadReq miss cycles
-system.l1subsys1.cache1.ReadReq_miss_latency::total 5914555445 # number of ReadReq miss cycles
-system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester0 1848193916 # number of WriteReq miss cycles
-system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester1 1820903145 # number of WriteReq miss cycles
-system.l1subsys1.cache1.WriteReq_miss_latency::total 3669097061 # number of WriteReq miss cycles
-system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester0 4845057801 # number of demand (read+write) miss cycles
-system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester1 4738594705 # number of demand (read+write) miss cycles
-system.l1subsys1.cache1.demand_miss_latency::total 9583652506 # number of demand (read+write) miss cycles
-system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester0 4845057801 # number of overall miss cycles
-system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester1 4738594705 # number of overall miss cycles
-system.l1subsys1.cache1.overall_miss_latency::total 9583652506 # number of overall miss cycles
-system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester0 41878 # number of ReadReq accesses(hits+misses)
-system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester1 41954 # number of ReadReq accesses(hits+misses)
-system.l1subsys1.cache1.ReadReq_accesses::total 83832 # number of ReadReq accesses(hits+misses)
-system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester0 23132 # number of WriteReq accesses(hits+misses)
-system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester1 23596 # number of WriteReq accesses(hits+misses)
-system.l1subsys1.cache1.WriteReq_accesses::total 46728 # number of WriteReq accesses(hits+misses)
-system.l1subsys1.cache1.demand_accesses::l0subsys3.tester0 65010 # number of demand (read+write) accesses
-system.l1subsys1.cache1.demand_accesses::l0subsys3.tester1 65550 # number of demand (read+write) accesses
-system.l1subsys1.cache1.demand_accesses::total 130560 # number of demand (read+write) accesses
-system.l1subsys1.cache1.overall_accesses::l0subsys3.tester0 65010 # number of overall (read+write) accesses
-system.l1subsys1.cache1.overall_accesses::l0subsys3.tester1 65550 # number of overall (read+write) accesses
-system.l1subsys1.cache1.overall_accesses::total 130560 # number of overall (read+write) accesses
-system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester0 0.789866 # miss rate for ReadReq accesses
-system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester1 0.781403 # miss rate for ReadReq accesses
-system.l1subsys1.cache1.ReadReq_miss_rate::total 0.785631 # miss rate for ReadReq accesses
-system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester0 0.954046 # miss rate for WriteReq accesses
-system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester1 0.951729 # miss rate for WriteReq accesses
-system.l1subsys1.cache1.WriteReq_miss_rate::total 0.952876 # miss rate for WriteReq accesses
-system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester0 0.848285 # miss rate for demand accesses
-system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester1 0.842715 # miss rate for demand accesses
-system.l1subsys1.cache1.demand_miss_rate::total 0.845489 # miss rate for demand accesses
-system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester0 0.848285 # miss rate for overall accesses
-system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester1 0.842715 # miss rate for overall accesses
-system.l1subsys1.cache1.overall_miss_rate::total 0.845489 # miss rate for overall accesses
-system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester0 90599.911875 # average ReadReq miss latency
-system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester1 89000.139096 # average ReadReq miss latency
-system.l1subsys1.cache1.ReadReq_avg_miss_latency::total 89803.608281 # average ReadReq miss latency
-system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester0 83746.155965 # average WriteReq miss latency
-system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester1 81083.989179 # average WriteReq miss latency
-system.l1subsys1.cache1.WriteReq_avg_miss_latency::total 82403.473499 # average WriteReq miss latency
-system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester0 87857.141839 # average overall miss latency
-system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester1 85781.946144 # average overall miss latency
-system.l1subsys1.cache1.demand_avg_miss_latency::total 86818.669825 # average overall miss latency
-system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester0 87857.141839 # average overall miss latency
-system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester1 85781.946144 # average overall miss latency
-system.l1subsys1.cache1.overall_avg_miss_latency::total 86818.669825 # average overall miss latency
-system.l1subsys1.cache1.blocked_cycles::no_mshrs 248811 # number of cycles access was blocked
-system.l1subsys1.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l1subsys1.cache1.blocked::no_mshrs 7700 # number of cycles access was blocked
-system.l1subsys1.cache1.blocked::no_targets 0 # number of cycles access was blocked
-system.l1subsys1.cache1.avg_blocked_cycles::no_mshrs 32.313117 # average number of cycles each access was blocked
-system.l1subsys1.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l1subsys1.cache1.writebacks::writebacks 23111 # number of writebacks
-system.l1subsys1.cache1.writebacks::total 23111 # number of writebacks
-system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester0 1265 # number of ReadReq MSHR hits
-system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester1 1191 # number of ReadReq MSHR hits
-system.l1subsys1.cache1.ReadReq_mshr_hits::total 2456 # number of ReadReq MSHR hits
-system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester0 636 # number of WriteReq MSHR hits
-system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester1 652 # number of WriteReq MSHR hits
-system.l1subsys1.cache1.WriteReq_mshr_hits::total 1288 # number of WriteReq MSHR hits
-system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester0 1901 # number of demand (read+write) MSHR hits
-system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester1 1843 # number of demand (read+write) MSHR hits
-system.l1subsys1.cache1.demand_mshr_hits::total 3744 # number of demand (read+write) MSHR hits
-system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester0 1901 # number of overall MSHR hits
-system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester1 1843 # number of overall MSHR hits
-system.l1subsys1.cache1.overall_mshr_hits::total 3744 # number of overall MSHR hits
-system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester0 31813 # number of ReadReq MSHR misses
-system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester1 31592 # number of ReadReq MSHR misses
-system.l1subsys1.cache1.ReadReq_mshr_misses::total 63405 # number of ReadReq MSHR misses
-system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester0 21433 # number of WriteReq MSHR misses
-system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester1 21805 # number of WriteReq MSHR misses
-system.l1subsys1.cache1.WriteReq_mshr_misses::total 43238 # number of WriteReq MSHR misses
-system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester0 53246 # number of demand (read+write) MSHR misses
-system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester1 53397 # number of demand (read+write) MSHR misses
-system.l1subsys1.cache1.demand_mshr_misses::total 106643 # number of demand (read+write) MSHR misses
-system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester0 53246 # number of overall MSHR misses
-system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester1 53397 # number of overall MSHR misses
-system.l1subsys1.cache1.overall_mshr_misses::total 106643 # number of overall MSHR misses
-system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester0 2936678534 # number of ReadReq MSHR miss cycles
-system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester1 2859058481 # number of ReadReq MSHR miss cycles
-system.l1subsys1.cache1.ReadReq_mshr_miss_latency::total 5795737015 # number of ReadReq MSHR miss cycles
-system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester0 1817912539 # number of WriteReq MSHR miss cycles
-system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester1 1790790455 # number of WriteReq MSHR miss cycles
-system.l1subsys1.cache1.WriteReq_mshr_miss_latency::total 3608702994 # number of WriteReq MSHR miss cycles
-system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester0 4754591073 # number of demand (read+write) MSHR miss cycles
-system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester1 4649848936 # number of demand (read+write) MSHR miss cycles
-system.l1subsys1.cache1.demand_mshr_miss_latency::total 9404440009 # number of demand (read+write) MSHR miss cycles
-system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester0 4754591073 # number of overall MSHR miss cycles
-system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester1 4649848936 # number of overall MSHR miss cycles
-system.l1subsys1.cache1.overall_mshr_miss_latency::total 9404440009 # number of overall MSHR miss cycles
-system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester0 0.759659 # mshr miss rate for ReadReq accesses
-system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester1 0.753015 # mshr miss rate for ReadReq accesses
-system.l1subsys1.cache1.ReadReq_mshr_miss_rate::total 0.756334 # mshr miss rate for ReadReq accesses
-system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester0 0.926552 # mshr miss rate for WriteReq accesses
-system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester1 0.924097 # mshr miss rate for WriteReq accesses
-system.l1subsys1.cache1.WriteReq_mshr_miss_rate::total 0.925312 # mshr miss rate for WriteReq accesses
-system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester0 0.819043 # mshr miss rate for demand accesses
-system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester1 0.814600 # mshr miss rate for demand accesses
-system.l1subsys1.cache1.demand_mshr_miss_rate::total 0.816812 # mshr miss rate for demand accesses
-system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester0 0.819043 # mshr miss rate for overall accesses
-system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester1 0.814600 # mshr miss rate for overall accesses
-system.l1subsys1.cache1.overall_mshr_miss_rate::total 0.816812 # mshr miss rate for overall accesses
-system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester0 92310.644516 # average ReadReq mshr miss latency
-system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester1 90499.445461 # average ReadReq mshr miss latency
-system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::total 91408.201483 # average ReadReq mshr miss latency
-system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester0 84818.389353 # average WriteReq mshr miss latency
-system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester1 82127.514561 # average WriteReq mshr miss latency
-system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::total 83461.376428 # average WriteReq mshr miss latency
-system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester0 89294.802858 # average overall mshr miss latency
-system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester1 87080.714947 # average overall mshr miss latency
-system.l1subsys1.cache1.demand_avg_mshr_miss_latency::total 88186.191396 # average overall mshr miss latency
-system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester0 89294.802858 # average overall mshr miss latency
-system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester1 87080.714947 # average overall mshr miss latency
-system.l1subsys1.cache1.overall_avg_mshr_miss_latency::total 88186.191396 # average overall mshr miss latency
-system.l1subsys1.xbar.snoop_filter.tot_requests 340971 # Total number of requests made to the snoop filter.
-system.l1subsys1.xbar.snoop_filter.hit_single_requests 160937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l1subsys1.xbar.snoop_filter.hit_multi_requests 9094 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l1subsys1.xbar.snoop_filter.tot_snoops 156359 # Total number of snoops made to the snoop filter.
-system.l1subsys1.xbar.snoop_filter.hit_single_snoops 137796 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 18563 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l1subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys1.xbar.trans_dist::ReadResp 153671 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 4438 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::WritebackDirty 90488 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::CleanEvict 185296 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::UpgradeReq 38860 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::UpgradeResp 23637 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::ReadExReq 102525 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::ReadExResp 93076 # Transaction distribution
-system.l1subsys1.xbar.trans_dist::ReadSharedReq 169429 # Transaction distribution
-system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 299650 # Packet count per connected master and slave (bytes)
-system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 300840 # Packet count per connected master and slave (bytes)
-system.l1subsys1.xbar.pkt_count::total 600490 # Packet count per connected master and slave (bytes)
-system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 9042560 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 9075776 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys1.xbar.pkt_size::total 18118336 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys1.xbar.snoops 321671 # Total snoops (count)
-system.l1subsys1.xbar.snoopTraffic 7090944 # Total snoop traffic (bytes)
-system.l1subsys1.xbar.snoop_fanout::samples 459710 # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::mean 0.443486 # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::stdev 0.572334 # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::0 274398 59.69% 59.69% # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::1 166749 36.27% 95.96% # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::2 18563 4.04% 100.00% # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::max_value 2 # Request fanout histogram
-system.l1subsys1.xbar.snoop_fanout::total 459710 # Request fanout histogram
-system.l1subsys1.xbar.reqLayer0.occupancy 530478299 # Layer occupancy (ticks)
-system.l1subsys1.xbar.reqLayer0.utilization 5.3 # Layer utilization (%)
-system.l1subsys1.xbar.snoopLayer0.occupancy 184704449 # Layer occupancy (ticks)
-system.l1subsys1.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%)
-system.l1subsys1.xbar.respLayer0.occupancy 310357504 # Layer occupancy (ticks)
-system.l1subsys1.xbar.respLayer0.utilization 3.1 # Layer utilization (%)
-system.l1subsys1.xbar.respLayer1.occupancy 313853796 # Layer occupancy (ticks)
-system.l1subsys1.xbar.respLayer1.utilization 3.1 # Layer utilization (%)
-system.l1subsys2.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys2.cache0.tags.replacements 66509 # number of replacements
-system.l1subsys2.cache0.tags.tagsinuse 503.868093 # Cycle average of tags in use
-system.l1subsys2.cache0.tags.total_refs 30279 # Total number of references to valid blocks.
-system.l1subsys2.cache0.tags.sampled_refs 67016 # Sample count of references to valid blocks.
-system.l1subsys2.cache0.tags.avg_refs 0.451817 # Average number of references to valid blocks.
-system.l1subsys2.cache0.tags.warmup_cycle 829394000 # Cycle when the warmup percentage was hit.
-system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester0 256.450231 # Average occupied blocks per requestor
-system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester1 247.417862 # Average occupied blocks per requestor
-system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester0 0.500879 # Average percentage of cache occupancy
-system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester1 0.483238 # Average percentage of cache occupancy
-system.l1subsys2.cache0.tags.occ_percent::total 0.984117 # Average percentage of cache occupancy
-system.l1subsys2.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id
-system.l1subsys2.cache0.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
-system.l1subsys2.cache0.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id
-system.l1subsys2.cache0.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
-system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id
-system.l1subsys2.cache0.tags.tag_accesses 631189 # Number of tag accesses
-system.l1subsys2.cache0.tags.data_accesses 631189 # Number of data accesses
-system.l1subsys2.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10236 # number of ReadReq hits
-system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 8788 # number of ReadReq hits
-system.l1subsys2.cache0.ReadReq_hits::total 19024 # number of ReadReq hits
-system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester0 1819 # number of WriteReq hits
-system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester1 1004 # number of WriteReq hits
-system.l1subsys2.cache0.WriteReq_hits::total 2823 # number of WriteReq hits
-system.l1subsys2.cache0.demand_hits::l0subsys4.tester0 12055 # number of demand (read+write) hits
-system.l1subsys2.cache0.demand_hits::l0subsys4.tester1 9792 # number of demand (read+write) hits
-system.l1subsys2.cache0.demand_hits::total 21847 # number of demand (read+write) hits
-system.l1subsys2.cache0.overall_hits::l0subsys4.tester0 12055 # number of overall hits
-system.l1subsys2.cache0.overall_hits::l0subsys4.tester1 9792 # number of overall hits
-system.l1subsys2.cache0.overall_hits::total 21847 # number of overall hits
-system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester0 32304 # number of ReadReq misses
-system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester1 34007 # number of ReadReq misses
-system.l1subsys2.cache0.ReadReq_misses::total 66311 # number of ReadReq misses
-system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester0 21653 # number of WriteReq misses
-system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester1 22755 # number of WriteReq misses
-system.l1subsys2.cache0.WriteReq_misses::total 44408 # number of WriteReq misses
-system.l1subsys2.cache0.demand_misses::l0subsys4.tester0 53957 # number of demand (read+write) misses
-system.l1subsys2.cache0.demand_misses::l0subsys4.tester1 56762 # number of demand (read+write) misses
-system.l1subsys2.cache0.demand_misses::total 110719 # number of demand (read+write) misses
-system.l1subsys2.cache0.overall_misses::l0subsys4.tester0 53957 # number of overall misses
-system.l1subsys2.cache0.overall_misses::l0subsys4.tester1 56762 # number of overall misses
-system.l1subsys2.cache0.overall_misses::total 110719 # number of overall misses
-system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester0 3033418520 # number of ReadReq miss cycles
-system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester1 3062242477 # number of ReadReq miss cycles
-system.l1subsys2.cache0.ReadReq_miss_latency::total 6095660997 # number of ReadReq miss cycles
-system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester0 1821498988 # number of WriteReq miss cycles
-system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester1 1866435160 # number of WriteReq miss cycles
-system.l1subsys2.cache0.WriteReq_miss_latency::total 3687934148 # number of WriteReq miss cycles
-system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester0 4854917508 # number of demand (read+write) miss cycles
-system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester1 4928677637 # number of demand (read+write) miss cycles
-system.l1subsys2.cache0.demand_miss_latency::total 9783595145 # number of demand (read+write) miss cycles
-system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester0 4854917508 # number of overall miss cycles
-system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester1 4928677637 # number of overall miss cycles
-system.l1subsys2.cache0.overall_miss_latency::total 9783595145 # number of overall miss cycles
-system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester0 42540 # number of ReadReq accesses(hits+misses)
-system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester1 42795 # number of ReadReq accesses(hits+misses)
-system.l1subsys2.cache0.ReadReq_accesses::total 85335 # number of ReadReq accesses(hits+misses)
-system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester0 23472 # number of WriteReq accesses(hits+misses)
-system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester1 23759 # number of WriteReq accesses(hits+misses)
-system.l1subsys2.cache0.WriteReq_accesses::total 47231 # number of WriteReq accesses(hits+misses)
-system.l1subsys2.cache0.demand_accesses::l0subsys4.tester0 66012 # number of demand (read+write) accesses
-system.l1subsys2.cache0.demand_accesses::l0subsys4.tester1 66554 # number of demand (read+write) accesses
-system.l1subsys2.cache0.demand_accesses::total 132566 # number of demand (read+write) accesses
-system.l1subsys2.cache0.overall_accesses::l0subsys4.tester0 66012 # number of overall (read+write) accesses
-system.l1subsys2.cache0.overall_accesses::l0subsys4.tester1 66554 # number of overall (read+write) accesses
-system.l1subsys2.cache0.overall_accesses::total 132566 # number of overall (read+write) accesses
-system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester0 0.759379 # miss rate for ReadReq accesses
-system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester1 0.794649 # miss rate for ReadReq accesses
-system.l1subsys2.cache0.ReadReq_miss_rate::total 0.777067 # miss rate for ReadReq accesses
-system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester0 0.922503 # miss rate for WriteReq accesses
-system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester1 0.957742 # miss rate for WriteReq accesses
-system.l1subsys2.cache0.WriteReq_miss_rate::total 0.940230 # miss rate for WriteReq accesses
-system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester0 0.817382 # miss rate for demand accesses
-system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester1 0.852871 # miss rate for demand accesses
-system.l1subsys2.cache0.demand_miss_rate::total 0.835199 # miss rate for demand accesses
-system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester0 0.817382 # miss rate for overall accesses
-system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester1 0.852871 # miss rate for overall accesses
-system.l1subsys2.cache0.overall_miss_rate::total 0.835199 # miss rate for overall accesses
-system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester0 93902.257306 # average ReadReq miss latency
-system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester1 90047.416032 # average ReadReq miss latency
-system.l1subsys2.cache0.ReadReq_avg_miss_latency::total 91925.336626 # average ReadReq miss latency
-system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester0 84122.245786 # average WriteReq miss latency
-system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester1 82023.078884 # average WriteReq miss latency
-system.l1subsys2.cache0.WriteReq_avg_miss_latency::total 83046.616556 # average WriteReq miss latency
-system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester0 89977.528551 # average overall miss latency
-system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester1 86830.584493 # average overall miss latency
-system.l1subsys2.cache0.demand_avg_miss_latency::total 88364.193544 # average overall miss latency
-system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester0 89977.528551 # average overall miss latency
-system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester1 86830.584493 # average overall miss latency
-system.l1subsys2.cache0.overall_avg_miss_latency::total 88364.193544 # average overall miss latency
-system.l1subsys2.cache0.blocked_cycles::no_mshrs 263390 # number of cycles access was blocked
-system.l1subsys2.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l1subsys2.cache0.blocked::no_mshrs 8190 # number of cycles access was blocked
-system.l1subsys2.cache0.blocked::no_targets 0 # number of cycles access was blocked
-system.l1subsys2.cache0.avg_blocked_cycles::no_mshrs 32.159951 # average number of cycles each access was blocked
-system.l1subsys2.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l1subsys2.cache0.writebacks::writebacks 23607 # number of writebacks
-system.l1subsys2.cache0.writebacks::total 23607 # number of writebacks
-system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester0 970 # number of ReadReq MSHR hits
-system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester1 984 # number of ReadReq MSHR hits
-system.l1subsys2.cache0.ReadReq_mshr_hits::total 1954 # number of ReadReq MSHR hits
-system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester0 557 # number of WriteReq MSHR hits
-system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester1 530 # number of WriteReq MSHR hits
-system.l1subsys2.cache0.WriteReq_mshr_hits::total 1087 # number of WriteReq MSHR hits
-system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester0 1527 # number of demand (read+write) MSHR hits
-system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester1 1514 # number of demand (read+write) MSHR hits
-system.l1subsys2.cache0.demand_mshr_hits::total 3041 # number of demand (read+write) MSHR hits
-system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester0 1527 # number of overall MSHR hits
-system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester1 1514 # number of overall MSHR hits
-system.l1subsys2.cache0.overall_mshr_hits::total 3041 # number of overall MSHR hits
-system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester0 31334 # number of ReadReq MSHR misses
-system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester1 33023 # number of ReadReq MSHR misses
-system.l1subsys2.cache0.ReadReq_mshr_misses::total 64357 # number of ReadReq MSHR misses
-system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester0 21096 # number of WriteReq MSHR misses
-system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester1 22225 # number of WriteReq MSHR misses
-system.l1subsys2.cache0.WriteReq_mshr_misses::total 43321 # number of WriteReq MSHR misses
-system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester0 52430 # number of demand (read+write) MSHR misses
-system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester1 55248 # number of demand (read+write) MSHR misses
-system.l1subsys2.cache0.demand_mshr_misses::total 107678 # number of demand (read+write) MSHR misses
-system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester0 52430 # number of overall MSHR misses
-system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester1 55248 # number of overall MSHR misses
-system.l1subsys2.cache0.overall_mshr_misses::total 107678 # number of overall MSHR misses
-system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester0 2981407825 # number of ReadReq MSHR miss cycles
-system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester1 3008088243 # number of ReadReq MSHR miss cycles
-system.l1subsys2.cache0.ReadReq_mshr_miss_latency::total 5989496068 # number of ReadReq MSHR miss cycles
-system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester0 1792490103 # number of WriteReq MSHR miss cycles
-system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester1 1837443596 # number of WriteReq MSHR miss cycles
-system.l1subsys2.cache0.WriteReq_mshr_miss_latency::total 3629933699 # number of WriteReq MSHR miss cycles
-system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester0 4773897928 # number of demand (read+write) MSHR miss cycles
-system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester1 4845531839 # number of demand (read+write) MSHR miss cycles
-system.l1subsys2.cache0.demand_mshr_miss_latency::total 9619429767 # number of demand (read+write) MSHR miss cycles
-system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester0 4773897928 # number of overall MSHR miss cycles
-system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester1 4845531839 # number of overall MSHR miss cycles
-system.l1subsys2.cache0.overall_mshr_miss_latency::total 9619429767 # number of overall MSHR miss cycles
-system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester0 0.736577 # mshr miss rate for ReadReq accesses
-system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester1 0.771656 # mshr miss rate for ReadReq accesses
-system.l1subsys2.cache0.ReadReq_mshr_miss_rate::total 0.754169 # mshr miss rate for ReadReq accesses
-system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester0 0.898773 # mshr miss rate for WriteReq accesses
-system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester1 0.935435 # mshr miss rate for WriteReq accesses
-system.l1subsys2.cache0.WriteReq_mshr_miss_rate::total 0.917215 # mshr miss rate for WriteReq accesses
-system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester0 0.794250 # mshr miss rate for demand accesses
-system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester1 0.830123 # mshr miss rate for demand accesses
-system.l1subsys2.cache0.demand_mshr_miss_rate::total 0.812260 # mshr miss rate for demand accesses
-system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester0 0.794250 # mshr miss rate for overall accesses
-system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester1 0.830123 # mshr miss rate for overall accesses
-system.l1subsys2.cache0.overall_mshr_miss_rate::total 0.812260 # mshr miss rate for overall accesses
-system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester0 95149.289111 # average ReadReq mshr miss latency
-system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester1 91090.701723 # average ReadReq mshr miss latency
-system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::total 93066.738164 # average ReadReq mshr miss latency
-system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester0 84968.245307 # average WriteReq mshr miss latency
-system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester1 82674.627492 # average WriteReq mshr miss latency
-system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::total 83791.549110 # average WriteReq mshr miss latency
-system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester0 91052.792829 # average overall mshr miss latency
-system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester1 87705.108583 # average overall mshr miss latency
-system.l1subsys2.cache0.demand_avg_mshr_miss_latency::total 89335.145220 # average overall mshr miss latency
-system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91052.792829 # average overall mshr miss latency
-system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 87705.108583 # average overall mshr miss latency
-system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 89335.145220 # average overall mshr miss latency
-system.l1subsys2.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys2.cache1.tags.replacements 65601 # number of replacements
-system.l1subsys2.cache1.tags.tagsinuse 502.970157 # Cycle average of tags in use
-system.l1subsys2.cache1.tags.total_refs 28017 # Total number of references to valid blocks.
-system.l1subsys2.cache1.tags.sampled_refs 66106 # Sample count of references to valid blocks.
-system.l1subsys2.cache1.tags.avg_refs 0.423819 # Average number of references to valid blocks.
-system.l1subsys2.cache1.tags.warmup_cycle 368043000 # Cycle when the warmup percentage was hit.
-system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester0 256.035642 # Average occupied blocks per requestor
-system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester1 246.934515 # Average occupied blocks per requestor
-system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester0 0.500070 # Average percentage of cache occupancy
-system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester1 0.482294 # Average percentage of cache occupancy
-system.l1subsys2.cache1.tags.occ_percent::total 0.982364 # Average percentage of cache occupancy
-system.l1subsys2.cache1.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id
-system.l1subsys2.cache1.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
-system.l1subsys2.cache1.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
-system.l1subsys2.cache1.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
-system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id
-system.l1subsys2.cache1.tags.tag_accesses 631185 # Number of tag accesses
-system.l1subsys2.cache1.tags.data_accesses 631185 # Number of data accesses
-system.l1subsys2.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 8598 # number of ReadReq hits
-system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 8958 # number of ReadReq hits
-system.l1subsys2.cache1.ReadReq_hits::total 17556 # number of ReadReq hits
-system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester0 971 # number of WriteReq hits
-system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester1 994 # number of WriteReq hits
-system.l1subsys2.cache1.WriteReq_hits::total 1965 # number of WriteReq hits
-system.l1subsys2.cache1.demand_hits::l0subsys5.tester0 9569 # number of demand (read+write) hits
-system.l1subsys2.cache1.demand_hits::l0subsys5.tester1 9952 # number of demand (read+write) hits
-system.l1subsys2.cache1.demand_hits::total 19521 # number of demand (read+write) hits
-system.l1subsys2.cache1.overall_hits::l0subsys5.tester0 9569 # number of overall hits
-system.l1subsys2.cache1.overall_hits::l0subsys5.tester1 9952 # number of overall hits
-system.l1subsys2.cache1.overall_hits::total 19521 # number of overall hits
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-system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester1 33576 # number of ReadReq misses
-system.l1subsys2.cache1.ReadReq_misses::total 67762 # number of ReadReq misses
-system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester0 22463 # number of WriteReq misses
-system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester1 22525 # number of WriteReq misses
-system.l1subsys2.cache1.WriteReq_misses::total 44988 # number of WriteReq misses
-system.l1subsys2.cache1.demand_misses::l0subsys5.tester0 56649 # number of demand (read+write) misses
-system.l1subsys2.cache1.demand_misses::l0subsys5.tester1 56101 # number of demand (read+write) misses
-system.l1subsys2.cache1.demand_misses::total 112750 # number of demand (read+write) misses
-system.l1subsys2.cache1.overall_misses::l0subsys5.tester0 56649 # number of overall misses
-system.l1subsys2.cache1.overall_misses::l0subsys5.tester1 56101 # number of overall misses
-system.l1subsys2.cache1.overall_misses::total 112750 # number of overall misses
-system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester0 3101171642 # number of ReadReq miss cycles
-system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester1 3046677897 # number of ReadReq miss cycles
-system.l1subsys2.cache1.ReadReq_miss_latency::total 6147849539 # number of ReadReq miss cycles
-system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester0 1867972083 # number of WriteReq miss cycles
-system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester1 1852914357 # number of WriteReq miss cycles
-system.l1subsys2.cache1.WriteReq_miss_latency::total 3720886440 # number of WriteReq miss cycles
-system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester0 4969143725 # number of demand (read+write) miss cycles
-system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester1 4899592254 # number of demand (read+write) miss cycles
-system.l1subsys2.cache1.demand_miss_latency::total 9868735979 # number of demand (read+write) miss cycles
-system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester0 4969143725 # number of overall miss cycles
-system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester1 4899592254 # number of overall miss cycles
-system.l1subsys2.cache1.overall_miss_latency::total 9868735979 # number of overall miss cycles
-system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester0 42784 # number of ReadReq accesses(hits+misses)
-system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester1 42534 # number of ReadReq accesses(hits+misses)
-system.l1subsys2.cache1.ReadReq_accesses::total 85318 # number of ReadReq accesses(hits+misses)
-system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester0 23434 # number of WriteReq accesses(hits+misses)
-system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester1 23519 # number of WriteReq accesses(hits+misses)
-system.l1subsys2.cache1.WriteReq_accesses::total 46953 # number of WriteReq accesses(hits+misses)
-system.l1subsys2.cache1.demand_accesses::l0subsys5.tester0 66218 # number of demand (read+write) accesses
-system.l1subsys2.cache1.demand_accesses::l0subsys5.tester1 66053 # number of demand (read+write) accesses
-system.l1subsys2.cache1.demand_accesses::total 132271 # number of demand (read+write) accesses
-system.l1subsys2.cache1.overall_accesses::l0subsys5.tester0 66218 # number of overall (read+write) accesses
-system.l1subsys2.cache1.overall_accesses::l0subsys5.tester1 66053 # number of overall (read+write) accesses
-system.l1subsys2.cache1.overall_accesses::total 132271 # number of overall (read+write) accesses
-system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester0 0.799037 # miss rate for ReadReq accesses
-system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester1 0.789392 # miss rate for ReadReq accesses
-system.l1subsys2.cache1.ReadReq_miss_rate::total 0.794229 # miss rate for ReadReq accesses
-system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester0 0.958564 # miss rate for WriteReq accesses
-system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester1 0.957736 # miss rate for WriteReq accesses
-system.l1subsys2.cache1.WriteReq_miss_rate::total 0.958150 # miss rate for WriteReq accesses
-system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester0 0.855492 # miss rate for demand accesses
-system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester1 0.849333 # miss rate for demand accesses
-system.l1subsys2.cache1.demand_miss_rate::total 0.852417 # miss rate for demand accesses
-system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester0 0.855492 # miss rate for overall accesses
-system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester1 0.849333 # miss rate for overall accesses
-system.l1subsys2.cache1.overall_miss_rate::total 0.852417 # miss rate for overall accesses
-system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester0 90714.668051 # average ReadReq miss latency
-system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester1 90739.751519 # average ReadReq miss latency
-system.l1subsys2.cache1.ReadReq_avg_miss_latency::total 90727.096883 # average ReadReq miss latency
-system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester0 83157.729733 # average WriteReq miss latency
-system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester1 82260.348812 # average WriteReq miss latency
-system.l1subsys2.cache1.WriteReq_avg_miss_latency::total 82708.420912 # average WriteReq miss latency
-system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester0 87718.119031 # average overall miss latency
-system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester1 87335.203544 # average overall miss latency
-system.l1subsys2.cache1.demand_avg_miss_latency::total 87527.591831 # average overall miss latency
-system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester0 87718.119031 # average overall miss latency
-system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester1 87335.203544 # average overall miss latency
-system.l1subsys2.cache1.overall_avg_miss_latency::total 87527.591831 # average overall miss latency
-system.l1subsys2.cache1.blocked_cycles::no_mshrs 243675 # number of cycles access was blocked
-system.l1subsys2.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l1subsys2.cache1.blocked::no_mshrs 7511 # number of cycles access was blocked
-system.l1subsys2.cache1.blocked::no_targets 0 # number of cycles access was blocked
-system.l1subsys2.cache1.avg_blocked_cycles::no_mshrs 32.442418 # average number of cycles each access was blocked
-system.l1subsys2.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l1subsys2.cache1.writebacks::writebacks 23261 # number of writebacks
-system.l1subsys2.cache1.writebacks::total 23261 # number of writebacks
-system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester0 1398 # number of ReadReq MSHR hits
-system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester1 1315 # number of ReadReq MSHR hits
-system.l1subsys2.cache1.ReadReq_mshr_hits::total 2713 # number of ReadReq MSHR hits
-system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester0 724 # number of WriteReq MSHR hits
-system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester1 737 # number of WriteReq MSHR hits
-system.l1subsys2.cache1.WriteReq_mshr_hits::total 1461 # number of WriteReq MSHR hits
-system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester0 2122 # number of demand (read+write) MSHR hits
-system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester1 2052 # number of demand (read+write) MSHR hits
-system.l1subsys2.cache1.demand_mshr_hits::total 4174 # number of demand (read+write) MSHR hits
-system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester0 2122 # number of overall MSHR hits
-system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester1 2052 # number of overall MSHR hits
-system.l1subsys2.cache1.overall_mshr_hits::total 4174 # number of overall MSHR hits
-system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester0 32788 # number of ReadReq MSHR misses
-system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester1 32261 # number of ReadReq MSHR misses
-system.l1subsys2.cache1.ReadReq_mshr_misses::total 65049 # number of ReadReq MSHR misses
-system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester0 21739 # number of WriteReq MSHR misses
-system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester1 21788 # number of WriteReq MSHR misses
-system.l1subsys2.cache1.WriteReq_mshr_misses::total 43527 # number of WriteReq MSHR misses
-system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester0 54527 # number of demand (read+write) MSHR misses
-system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester1 54049 # number of demand (read+write) MSHR misses
-system.l1subsys2.cache1.demand_mshr_misses::total 108576 # number of demand (read+write) MSHR misses
-system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester0 54527 # number of overall MSHR misses
-system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester1 54049 # number of overall MSHR misses
-system.l1subsys2.cache1.overall_mshr_misses::total 108576 # number of overall MSHR misses
-system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester0 3037090619 # number of ReadReq MSHR miss cycles
-system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester1 2984778636 # number of ReadReq MSHR miss cycles
-system.l1subsys2.cache1.ReadReq_mshr_miss_latency::total 6021869255 # number of ReadReq MSHR miss cycles
-system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester0 1837384657 # number of WriteReq MSHR miss cycles
-system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester1 1821394302 # number of WriteReq MSHR miss cycles
-system.l1subsys2.cache1.WriteReq_mshr_miss_latency::total 3658778959 # number of WriteReq MSHR miss cycles
-system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester0 4874475276 # number of demand (read+write) MSHR miss cycles
-system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester1 4806172938 # number of demand (read+write) MSHR miss cycles
-system.l1subsys2.cache1.demand_mshr_miss_latency::total 9680648214 # number of demand (read+write) MSHR miss cycles
-system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester0 4874475276 # number of overall MSHR miss cycles
-system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester1 4806172938 # number of overall MSHR miss cycles
-system.l1subsys2.cache1.overall_mshr_miss_latency::total 9680648214 # number of overall MSHR miss cycles
-system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester0 0.766361 # mshr miss rate for ReadReq accesses
-system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester1 0.758476 # mshr miss rate for ReadReq accesses
-system.l1subsys2.cache1.ReadReq_mshr_miss_rate::total 0.762430 # mshr miss rate for ReadReq accesses
-system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester0 0.927669 # mshr miss rate for WriteReq accesses
-system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester1 0.926400 # mshr miss rate for WriteReq accesses
-system.l1subsys2.cache1.WriteReq_mshr_miss_rate::total 0.927033 # mshr miss rate for WriteReq accesses
-system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester0 0.823447 # mshr miss rate for demand accesses
-system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester1 0.818267 # mshr miss rate for demand accesses
-system.l1subsys2.cache1.demand_mshr_miss_rate::total 0.820860 # mshr miss rate for demand accesses
-system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester0 0.823447 # mshr miss rate for overall accesses
-system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester1 0.818267 # mshr miss rate for overall accesses
-system.l1subsys2.cache1.overall_mshr_miss_rate::total 0.820860 # mshr miss rate for overall accesses
-system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester0 92628.114524 # average ReadReq mshr miss latency
-system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester1 92519.718422 # average ReadReq mshr miss latency
-system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::total 92574.355563 # average ReadReq mshr miss latency
-system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester0 84520.201343 # average WriteReq mshr miss latency
-system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester1 83596.213604 # average WriteReq mshr miss latency
-system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::total 84057.687389 # average WriteReq mshr miss latency
-system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester0 89395.625580 # average overall mshr miss latency
-system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester1 88922.513608 # average overall mshr miss latency
-system.l1subsys2.cache1.demand_avg_mshr_miss_latency::total 89160.111019 # average overall mshr miss latency
-system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester0 89395.625580 # average overall mshr miss latency
-system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester1 88922.513608 # average overall mshr miss latency
-system.l1subsys2.cache1.overall_avg_mshr_miss_latency::total 89160.111019 # average overall mshr miss latency
-system.l1subsys2.xbar.snoop_filter.tot_requests 350018 # Total number of requests made to the snoop filter.
-system.l1subsys2.xbar.snoop_filter.hit_single_requests 165507 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l1subsys2.xbar.snoop_filter.hit_multi_requests 8863 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l1subsys2.xbar.snoop_filter.tot_snoops 157282 # Total number of snoops made to the snoop filter.
-system.l1subsys2.xbar.snoop_filter.hit_single_snoops 139819 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 17463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l1subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l1subsys2.xbar.trans_dist::ReadResp 155964 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 4483 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::WritebackDirty 93011 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::CleanEvict 193898 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::UpgradeReq 38837 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::UpgradeResp 23341 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::ReadExReq 102617 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::ReadExResp 93375 # Transaction distribution
-system.l1subsys2.xbar.trans_dist::ReadSharedReq 171504 # Transaction distribution
-system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 304422 # Packet count per connected master and slave (bytes)
-system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 307736 # Packet count per connected master and slave (bytes)
-system.l1subsys2.xbar.pkt_count::total 612158 # Packet count per connected master and slave (bytes)
-system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 9114816 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 9277120 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys2.xbar.pkt_size::total 18391936 # Cumulative packet size per connected master and slave (bytes)
-system.l1subsys2.xbar.snoops 324128 # Total snoops (count)
-system.l1subsys2.xbar.snoopTraffic 7056320 # Total snoop traffic (bytes)
-system.l1subsys2.xbar.snoop_fanout::samples 467757 # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::mean 0.433484 # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::stdev 0.565900 # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::0 282455 60.38% 60.38% # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::1 167839 35.88% 96.27% # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::2 17463 3.73% 100.00% # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::max_value 2 # Request fanout histogram
-system.l1subsys2.xbar.snoop_fanout::total 467757 # Request fanout histogram
-system.l1subsys2.xbar.reqLayer0.occupancy 543938741 # Layer occupancy (ticks)
-system.l1subsys2.xbar.reqLayer0.utilization 5.4 # Layer utilization (%)
-system.l1subsys2.xbar.snoopLayer0.occupancy 179965490 # Layer occupancy (ticks)
-system.l1subsys2.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%)
-system.l1subsys2.xbar.respLayer0.occupancy 316289424 # Layer occupancy (ticks)
-system.l1subsys2.xbar.respLayer0.utilization 3.2 # Layer utilization (%)
-system.l1subsys2.xbar.respLayer1.occupancy 319642014 # Layer occupancy (ticks)
-system.l1subsys2.xbar.respLayer1.utilization 3.2 # Layer utilization (%)
-system.l2subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache0.tags.replacements 33659 # number of replacements
-system.l2subsys0.cache0.tags.tagsinuse 498.694876 # Cycle average of tags in use
-system.l2subsys0.cache0.tags.total_refs 11307 # Total number of references to valid blocks.
-system.l2subsys0.cache0.tags.sampled_refs 34163 # Sample count of references to valid blocks.
-system.l2subsys0.cache0.tags.avg_refs 0.330972 # Average number of references to valid blocks.
-system.l2subsys0.cache0.tags.warmup_cycle 1001764000 # Cycle when the warmup percentage was hit.
-system.l2subsys0.cache0.tags.occ_blocks::l2subsys0.tester 498.694876 # Average occupied blocks per requestor
-system.l2subsys0.cache0.tags.occ_percent::l2subsys0.tester 0.974013 # Average percentage of cache occupancy
-system.l2subsys0.cache0.tags.occ_percent::total 0.974013 # Average percentage of cache occupancy
-system.l2subsys0.cache0.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
-system.l2subsys0.cache0.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.l2subsys0.cache0.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
-system.l2subsys0.cache0.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
-system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
-system.l2subsys0.cache0.tags.tag_accesses 325927 # Number of tag accesses
-system.l2subsys0.cache0.tags.data_accesses 325927 # Number of data accesses
-system.l2subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 7262 # number of ReadReq hits
-system.l2subsys0.cache0.ReadReq_hits::total 7262 # number of ReadReq hits
-system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 605 # number of WriteReq hits
-system.l2subsys0.cache0.WriteReq_hits::total 605 # number of WriteReq hits
-system.l2subsys0.cache0.demand_hits::l2subsys0.tester 7867 # number of demand (read+write) hits
-system.l2subsys0.cache0.demand_hits::total 7867 # number of demand (read+write) hits
-system.l2subsys0.cache0.overall_hits::l2subsys0.tester 7867 # number of overall hits
-system.l2subsys0.cache0.overall_hits::total 7867 # number of overall hits
-system.l2subsys0.cache0.ReadReq_misses::l2subsys0.tester 36028 # number of ReadReq misses
-system.l2subsys0.cache0.ReadReq_misses::total 36028 # number of ReadReq misses
-system.l2subsys0.cache0.WriteReq_misses::l2subsys0.tester 23553 # number of WriteReq misses
-system.l2subsys0.cache0.WriteReq_misses::total 23553 # number of WriteReq misses
-system.l2subsys0.cache0.demand_misses::l2subsys0.tester 59581 # number of demand (read+write) misses
-system.l2subsys0.cache0.demand_misses::total 59581 # number of demand (read+write) misses
-system.l2subsys0.cache0.overall_misses::l2subsys0.tester 59581 # number of overall misses
-system.l2subsys0.cache0.overall_misses::total 59581 # number of overall misses
-system.l2subsys0.cache0.ReadReq_miss_latency::l2subsys0.tester 2432084535 # number of ReadReq miss cycles
-system.l2subsys0.cache0.ReadReq_miss_latency::total 2432084535 # number of ReadReq miss cycles
-system.l2subsys0.cache0.WriteReq_miss_latency::l2subsys0.tester 1416934536 # number of WriteReq miss cycles
-system.l2subsys0.cache0.WriteReq_miss_latency::total 1416934536 # number of WriteReq miss cycles
-system.l2subsys0.cache0.demand_miss_latency::l2subsys0.tester 3849019071 # number of demand (read+write) miss cycles
-system.l2subsys0.cache0.demand_miss_latency::total 3849019071 # number of demand (read+write) miss cycles
-system.l2subsys0.cache0.overall_miss_latency::l2subsys0.tester 3849019071 # number of overall miss cycles
-system.l2subsys0.cache0.overall_miss_latency::total 3849019071 # number of overall miss cycles
-system.l2subsys0.cache0.ReadReq_accesses::l2subsys0.tester 43290 # number of ReadReq accesses(hits+misses)
-system.l2subsys0.cache0.ReadReq_accesses::total 43290 # number of ReadReq accesses(hits+misses)
-system.l2subsys0.cache0.WriteReq_accesses::l2subsys0.tester 24158 # number of WriteReq accesses(hits+misses)
-system.l2subsys0.cache0.WriteReq_accesses::total 24158 # number of WriteReq accesses(hits+misses)
-system.l2subsys0.cache0.demand_accesses::l2subsys0.tester 67448 # number of demand (read+write) accesses
-system.l2subsys0.cache0.demand_accesses::total 67448 # number of demand (read+write) accesses
-system.l2subsys0.cache0.overall_accesses::l2subsys0.tester 67448 # number of overall (read+write) accesses
-system.l2subsys0.cache0.overall_accesses::total 67448 # number of overall (read+write) accesses
-system.l2subsys0.cache0.ReadReq_miss_rate::l2subsys0.tester 0.832248 # miss rate for ReadReq accesses
-system.l2subsys0.cache0.ReadReq_miss_rate::total 0.832248 # miss rate for ReadReq accesses
-system.l2subsys0.cache0.WriteReq_miss_rate::l2subsys0.tester 0.974957 # miss rate for WriteReq accesses
-system.l2subsys0.cache0.WriteReq_miss_rate::total 0.974957 # miss rate for WriteReq accesses
-system.l2subsys0.cache0.demand_miss_rate::l2subsys0.tester 0.883362 # miss rate for demand accesses
-system.l2subsys0.cache0.demand_miss_rate::total 0.883362 # miss rate for demand accesses
-system.l2subsys0.cache0.overall_miss_rate::l2subsys0.tester 0.883362 # miss rate for overall accesses
-system.l2subsys0.cache0.overall_miss_rate::total 0.883362 # miss rate for overall accesses
-system.l2subsys0.cache0.ReadReq_avg_miss_latency::l2subsys0.tester 67505.399550 # average ReadReq miss latency
-system.l2subsys0.cache0.ReadReq_avg_miss_latency::total 67505.399550 # average ReadReq miss latency
-system.l2subsys0.cache0.WriteReq_avg_miss_latency::l2subsys0.tester 60159.407974 # average WriteReq miss latency
-system.l2subsys0.cache0.WriteReq_avg_miss_latency::total 60159.407974 # average WriteReq miss latency
-system.l2subsys0.cache0.demand_avg_miss_latency::l2subsys0.tester 64601.451318 # average overall miss latency
-system.l2subsys0.cache0.demand_avg_miss_latency::total 64601.451318 # average overall miss latency
-system.l2subsys0.cache0.overall_avg_miss_latency::l2subsys0.tester 64601.451318 # average overall miss latency
-system.l2subsys0.cache0.overall_avg_miss_latency::total 64601.451318 # average overall miss latency
-system.l2subsys0.cache0.blocked_cycles::no_mshrs 22051 # number of cycles access was blocked
-system.l2subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2subsys0.cache0.blocked::no_mshrs 434 # number of cycles access was blocked
-system.l2subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked
-system.l2subsys0.cache0.avg_blocked_cycles::no_mshrs 50.808756 # average number of cycles each access was blocked
-system.l2subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2subsys0.cache0.writebacks::writebacks 12098 # number of writebacks
-system.l2subsys0.cache0.writebacks::total 12098 # number of writebacks
-system.l2subsys0.cache0.ReadReq_mshr_hits::l2subsys0.tester 8 # number of ReadReq MSHR hits
-system.l2subsys0.cache0.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
-system.l2subsys0.cache0.WriteReq_mshr_hits::l2subsys0.tester 6 # number of WriteReq MSHR hits
-system.l2subsys0.cache0.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits
-system.l2subsys0.cache0.demand_mshr_hits::l2subsys0.tester 14 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache0.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache0.overall_mshr_hits::l2subsys0.tester 14 # number of overall MSHR hits
-system.l2subsys0.cache0.overall_mshr_hits::total 14 # number of overall MSHR hits
-system.l2subsys0.cache0.ReadReq_mshr_misses::l2subsys0.tester 36020 # number of ReadReq MSHR misses
-system.l2subsys0.cache0.ReadReq_mshr_misses::total 36020 # number of ReadReq MSHR misses
-system.l2subsys0.cache0.WriteReq_mshr_misses::l2subsys0.tester 23547 # number of WriteReq MSHR misses
-system.l2subsys0.cache0.WriteReq_mshr_misses::total 23547 # number of WriteReq MSHR misses
-system.l2subsys0.cache0.demand_mshr_misses::l2subsys0.tester 59567 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache0.demand_mshr_misses::total 59567 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache0.overall_mshr_misses::l2subsys0.tester 59567 # number of overall MSHR misses
-system.l2subsys0.cache0.overall_mshr_misses::total 59567 # number of overall MSHR misses
-system.l2subsys0.cache0.ReadReq_mshr_miss_latency::l2subsys0.tester 2396005584 # number of ReadReq MSHR miss cycles
-system.l2subsys0.cache0.ReadReq_mshr_miss_latency::total 2396005584 # number of ReadReq MSHR miss cycles
-system.l2subsys0.cache0.WriteReq_mshr_miss_latency::l2subsys0.tester 1393365242 # number of WriteReq MSHR miss cycles
-system.l2subsys0.cache0.WriteReq_mshr_miss_latency::total 1393365242 # number of WriteReq MSHR miss cycles
-system.l2subsys0.cache0.demand_mshr_miss_latency::l2subsys0.tester 3789370826 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache0.demand_mshr_miss_latency::total 3789370826 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache0.overall_mshr_miss_latency::l2subsys0.tester 3789370826 # number of overall MSHR miss cycles
-system.l2subsys0.cache0.overall_mshr_miss_latency::total 3789370826 # number of overall MSHR miss cycles
-system.l2subsys0.cache0.ReadReq_mshr_miss_rate::l2subsys0.tester 0.832063 # mshr miss rate for ReadReq accesses
-system.l2subsys0.cache0.ReadReq_mshr_miss_rate::total 0.832063 # mshr miss rate for ReadReq accesses
-system.l2subsys0.cache0.WriteReq_mshr_miss_rate::l2subsys0.tester 0.974708 # mshr miss rate for WriteReq accesses
-system.l2subsys0.cache0.WriteReq_mshr_miss_rate::total 0.974708 # mshr miss rate for WriteReq accesses
-system.l2subsys0.cache0.demand_mshr_miss_rate::l2subsys0.tester 0.883154 # mshr miss rate for demand accesses
-system.l2subsys0.cache0.demand_mshr_miss_rate::total 0.883154 # mshr miss rate for demand accesses
-system.l2subsys0.cache0.overall_mshr_miss_rate::l2subsys0.tester 0.883154 # mshr miss rate for overall accesses
-system.l2subsys0.cache0.overall_mshr_miss_rate::total 0.883154 # mshr miss rate for overall accesses
-system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::l2subsys0.tester 66518.755802 # average ReadReq mshr miss latency
-system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 66518.755802 # average ReadReq mshr miss latency
-system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::l2subsys0.tester 59173.790377 # average WriteReq mshr miss latency
-system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 59173.790377 # average WriteReq mshr miss latency
-system.l2subsys0.cache0.demand_avg_mshr_miss_latency::l2subsys0.tester 63615.270636 # average overall mshr miss latency
-system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 63615.270636 # average overall mshr miss latency
-system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 63615.270636 # average overall mshr miss latency
-system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 63615.270636 # average overall mshr miss latency
-system.l2subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache1.tags.replacements 151853 # number of replacements
-system.l2subsys0.cache1.tags.tagsinuse 1524.082956 # Cycle average of tags in use
-system.l2subsys0.cache1.tags.total_refs 82258 # Total number of references to valid blocks.
-system.l2subsys0.cache1.tags.sampled_refs 153387 # Sample count of references to valid blocks.
-system.l2subsys0.cache1.tags.avg_refs 0.536278 # Average number of references to valid blocks.
-system.l2subsys0.cache1.tags.warmup_cycle 439051000 # Cycle when the warmup percentage was hit.
-system.l2subsys0.cache1.tags.occ_blocks::writebacks 190.667622 # Average occupied blocks per requestor
-system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester0 328.055957 # Average occupied blocks per requestor
-system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester1 322.496146 # Average occupied blocks per requestor
-system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 335.799241 # Average occupied blocks per requestor
-system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 347.063989 # Average occupied blocks per requestor
-system.l2subsys0.cache1.tags.occ_percent::writebacks 0.124133 # Average percentage of cache occupancy
-system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester0 0.213578 # Average percentage of cache occupancy
-system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester1 0.209958 # Average percentage of cache occupancy
-system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.218619 # Average percentage of cache occupancy
-system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.225953 # Average percentage of cache occupancy
-system.l2subsys0.cache1.tags.occ_percent::total 0.992242 # Average percentage of cache occupancy
-system.l2subsys0.cache1.tags.occ_task_id_blocks::1024 1534 # Occupied blocks per task id
-system.l2subsys0.cache1.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
-system.l2subsys0.cache1.tags.age_task_id_blocks_1024::1 1102 # Occupied blocks per task id
-system.l2subsys0.cache1.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id
-system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.998698 # Percentage of cache occupancy per task id
-system.l2subsys0.cache1.tags.tag_accesses 4165543 # Number of tag accesses
-system.l2subsys0.cache1.tags.data_accesses 4165543 # Number of data accesses
-system.l2subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache1.WritebackDirty_hits::writebacks 46587 # number of WritebackDirty hits
-system.l2subsys0.cache1.WritebackDirty_hits::total 46587 # number of WritebackDirty hits
-system.l2subsys0.cache1.UpgradeReq_hits::l0subsys0.tester0 168 # number of UpgradeReq hits
-system.l2subsys0.cache1.UpgradeReq_hits::l0subsys0.tester1 121 # number of UpgradeReq hits
-system.l2subsys0.cache1.UpgradeReq_hits::l0subsys1.tester0 142 # number of UpgradeReq hits
-system.l2subsys0.cache1.UpgradeReq_hits::l0subsys1.tester1 160 # number of UpgradeReq hits
-system.l2subsys0.cache1.UpgradeReq_hits::total 591 # number of UpgradeReq hits
-system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 42 # number of ReadExReq hits
-system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester1 49 # number of ReadExReq hits
-system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester0 38 # number of ReadExReq hits
-system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester1 33 # number of ReadExReq hits
-system.l2subsys0.cache1.ReadExReq_hits::total 162 # number of ReadExReq hits
-system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester0 686 # number of ReadSharedReq hits
-system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester1 632 # number of ReadSharedReq hits
-system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester0 726 # number of ReadSharedReq hits
-system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester1 731 # number of ReadSharedReq hits
-system.l2subsys0.cache1.ReadSharedReq_hits::total 2775 # number of ReadSharedReq hits
-system.l2subsys0.cache1.demand_hits::l0subsys0.tester0 728 # number of demand (read+write) hits
-system.l2subsys0.cache1.demand_hits::l0subsys0.tester1 681 # number of demand (read+write) hits
-system.l2subsys0.cache1.demand_hits::l0subsys1.tester0 764 # number of demand (read+write) hits
-system.l2subsys0.cache1.demand_hits::l0subsys1.tester1 764 # number of demand (read+write) hits
-system.l2subsys0.cache1.demand_hits::total 2937 # number of demand (read+write) hits
-system.l2subsys0.cache1.overall_hits::l0subsys0.tester0 728 # number of overall hits
-system.l2subsys0.cache1.overall_hits::l0subsys0.tester1 681 # number of overall hits
-system.l2subsys0.cache1.overall_hits::l0subsys1.tester0 764 # number of overall hits
-system.l2subsys0.cache1.overall_hits::l0subsys1.tester1 764 # number of overall hits
-system.l2subsys0.cache1.overall_hits::total 2937 # number of overall hits
-system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester0 3496 # number of UpgradeReq misses
-system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester1 3545 # number of UpgradeReq misses
-system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester0 3229 # number of UpgradeReq misses
-system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester1 3694 # number of UpgradeReq misses
-system.l2subsys0.cache1.UpgradeReq_misses::total 13964 # number of UpgradeReq misses
-system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester0 16533 # number of ReadExReq misses
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-system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester1 16964 # number of ReadExReq misses
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-system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester0 1610224177 # number of ReadExReq miss cycles
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-system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester0 2766545210 # number of ReadSharedReq miss cycles
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-system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester1 95289.808064 # average ReadExReq miss latency
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-system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester1 93981.549814 # average ReadSharedReq miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester0 95731.520468 # average ReadSharedReq miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester1 95753.892003 # average ReadSharedReq miss latency
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-system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 95826.277247 # average overall miss latency
-system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 95584.996632 # average overall miss latency
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-system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester0 351 # number of ReadExReq MSHR hits
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-system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester0 568 # number of ReadSharedReq MSHR hits
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-system.l2subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 44755 # number of overall MSHR misses
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-system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::total 9916830320 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester0 3896538573 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester1 3813451123 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 3904360400 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 3973317608 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache1.demand_mshr_miss_latency::total 15587667704 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester0 3896538573 # number of overall MSHR miss cycles
-system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester1 3813451123 # number of overall MSHR miss cycles
-system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 3904360400 # number of overall MSHR miss cycles
-system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 3973317608 # number of overall MSHR miss cycles
-system.l2subsys0.cache1.overall_mshr_miss_latency::total 15587667704 # number of overall MSHR miss cycles
-system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester0 0.954148 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester1 0.966994 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester0 0.957876 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester1 0.958485 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::total 0.959395 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester0 0.977496 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester1 0.977410 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester0 0.976863 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester1 0.978173 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::total 0.977487 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester0 0.955076 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester1 0.959657 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester0 0.956321 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester1 0.956122 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::total 0.956794 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester0 0.963142 # mshr miss rate for demand accesses
-system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester1 0.966052 # mshr miss rate for demand accesses
-system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.963758 # mshr miss rate for demand accesses
-system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.964033 # mshr miss rate for demand accesses
-system.l2subsys0.cache1.demand_mshr_miss_rate::total 0.964248 # mshr miss rate for demand accesses
-system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester0 0.963142 # mshr miss rate for overall accesses
-system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester1 0.966052 # mshr miss rate for overall accesses
-system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.963758 # mshr miss rate for overall accesses
-system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.964033 # mshr miss rate for overall accesses
-system.l2subsys0.cache1.overall_mshr_miss_rate::total 0.964248 # mshr miss rate for overall accesses
-system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester0 23367.876144 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester1 23401.571509 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester0 23469.231651 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester1 23802.763400 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::total 23514.911415 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester0 87302.967905 # average ReadExReq mshr miss latency
-system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester1 84374.342831 # average ReadExReq mshr miss latency
-system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester0 87426.593156 # average ReadExReq mshr miss latency
-system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester1 86642.484963 # average ReadExReq mshr miss latency
-system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::total 86436.468426 # average ReadExReq mshr miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester0 88113.028045 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester1 85323.401914 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester0 87129.505983 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester1 87196.600441 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::total 86937.881965 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester0 87817.235875 # average overall mshr miss latency
-system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester1 84977.518562 # average overall mshr miss latency
-system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 87238.529773 # average overall mshr miss latency
-system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 86994.889935 # average overall mshr miss latency
-system.l2subsys0.cache1.demand_avg_mshr_miss_latency::total 86754.794512 # average overall mshr miss latency
-system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester0 87817.235875 # average overall mshr miss latency
-system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester1 84977.518562 # average overall mshr miss latency
-system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 87238.529773 # average overall mshr miss latency
-system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 86994.889935 # average overall mshr miss latency
-system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 86754.794512 # average overall mshr miss latency
-system.l2subsys0.cache2.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache2.tags.replacements 148896 # number of replacements
-system.l2subsys0.cache2.tags.tagsinuse 1523.034958 # Cycle average of tags in use
-system.l2subsys0.cache2.tags.total_refs 81242 # Total number of references to valid blocks.
-system.l2subsys0.cache2.tags.sampled_refs 150425 # Sample count of references to valid blocks.
-system.l2subsys0.cache2.tags.avg_refs 0.540083 # Average number of references to valid blocks.
-system.l2subsys0.cache2.tags.warmup_cycle 259670000 # Cycle when the warmup percentage was hit.
-system.l2subsys0.cache2.tags.occ_blocks::writebacks 189.526445 # Average occupied blocks per requestor
-system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester0 325.843379 # Average occupied blocks per requestor
-system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester1 331.240676 # Average occupied blocks per requestor
-system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester0 338.598926 # Average occupied blocks per requestor
-system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester1 337.825532 # Average occupied blocks per requestor
-system.l2subsys0.cache2.tags.occ_percent::writebacks 0.123390 # Average percentage of cache occupancy
-system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester0 0.212138 # Average percentage of cache occupancy
-system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester1 0.215651 # Average percentage of cache occupancy
-system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester0 0.220442 # Average percentage of cache occupancy
-system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester1 0.219938 # Average percentage of cache occupancy
-system.l2subsys0.cache2.tags.occ_percent::total 0.991559 # Average percentage of cache occupancy
-system.l2subsys0.cache2.tags.occ_task_id_blocks::1024 1529 # Occupied blocks per task id
-system.l2subsys0.cache2.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id
-system.l2subsys0.cache2.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id
-system.l2subsys0.cache2.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
-system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.995443 # Percentage of cache occupancy per task id
-system.l2subsys0.cache2.tags.tag_accesses 4107279 # Number of tag accesses
-system.l2subsys0.cache2.tags.data_accesses 4107279 # Number of data accesses
-system.l2subsys0.cache2.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45595 # number of WritebackDirty hits
-system.l2subsys0.cache2.WritebackDirty_hits::total 45595 # number of WritebackDirty hits
-system.l2subsys0.cache2.UpgradeReq_hits::l0subsys2.tester0 140 # number of UpgradeReq hits
-system.l2subsys0.cache2.UpgradeReq_hits::l0subsys2.tester1 149 # number of UpgradeReq hits
-system.l2subsys0.cache2.UpgradeReq_hits::l0subsys3.tester0 120 # number of UpgradeReq hits
-system.l2subsys0.cache2.UpgradeReq_hits::l0subsys3.tester1 184 # number of UpgradeReq hits
-system.l2subsys0.cache2.UpgradeReq_hits::total 593 # number of UpgradeReq hits
-system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 45 # number of ReadExReq hits
-system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester1 36 # number of ReadExReq hits
-system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester0 49 # number of ReadExReq hits
-system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester1 30 # number of ReadExReq hits
-system.l2subsys0.cache2.ReadExReq_hits::total 160 # number of ReadExReq hits
-system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester0 644 # number of ReadSharedReq hits
-system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester1 713 # number of ReadSharedReq hits
-system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester0 722 # number of ReadSharedReq hits
-system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester1 725 # number of ReadSharedReq hits
-system.l2subsys0.cache2.ReadSharedReq_hits::total 2804 # number of ReadSharedReq hits
-system.l2subsys0.cache2.demand_hits::l0subsys2.tester0 689 # number of demand (read+write) hits
-system.l2subsys0.cache2.demand_hits::l0subsys2.tester1 749 # number of demand (read+write) hits
-system.l2subsys0.cache2.demand_hits::l0subsys3.tester0 771 # number of demand (read+write) hits
-system.l2subsys0.cache2.demand_hits::l0subsys3.tester1 755 # number of demand (read+write) hits
-system.l2subsys0.cache2.demand_hits::total 2964 # number of demand (read+write) hits
-system.l2subsys0.cache2.overall_hits::l0subsys2.tester0 689 # number of overall hits
-system.l2subsys0.cache2.overall_hits::l0subsys2.tester1 749 # number of overall hits
-system.l2subsys0.cache2.overall_hits::l0subsys3.tester0 771 # number of overall hits
-system.l2subsys0.cache2.overall_hits::l0subsys3.tester1 755 # number of overall hits
-system.l2subsys0.cache2.overall_hits::total 2964 # number of overall hits
-system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester0 3731 # number of UpgradeReq misses
-system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester1 3588 # number of UpgradeReq misses
-system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester0 3374 # number of UpgradeReq misses
-system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester1 3500 # number of UpgradeReq misses
-system.l2subsys0.cache2.UpgradeReq_misses::total 14193 # number of UpgradeReq misses
-system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester0 16480 # number of ReadExReq misses
-system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester1 16325 # number of ReadExReq misses
-system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester0 16664 # number of ReadExReq misses
-system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester1 16716 # number of ReadExReq misses
-system.l2subsys0.cache2.ReadExReq_misses::total 66185 # number of ReadExReq misses
-system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester0 28695 # number of ReadSharedReq misses
-system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester1 28471 # number of ReadSharedReq misses
-system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester0 29046 # number of ReadSharedReq misses
-system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester1 28633 # number of ReadSharedReq misses
-system.l2subsys0.cache2.ReadSharedReq_misses::total 114845 # number of ReadSharedReq misses
-system.l2subsys0.cache2.demand_misses::l0subsys2.tester0 45175 # number of demand (read+write) misses
-system.l2subsys0.cache2.demand_misses::l0subsys2.tester1 44796 # number of demand (read+write) misses
-system.l2subsys0.cache2.demand_misses::l0subsys3.tester0 45710 # number of demand (read+write) misses
-system.l2subsys0.cache2.demand_misses::l0subsys3.tester1 45349 # number of demand (read+write) misses
-system.l2subsys0.cache2.demand_misses::total 181030 # number of demand (read+write) misses
-system.l2subsys0.cache2.overall_misses::l0subsys2.tester0 45175 # number of overall misses
-system.l2subsys0.cache2.overall_misses::l0subsys2.tester1 44796 # number of overall misses
-system.l2subsys0.cache2.overall_misses::l0subsys3.tester0 45710 # number of overall misses
-system.l2subsys0.cache2.overall_misses::l0subsys3.tester1 45349 # number of overall misses
-system.l2subsys0.cache2.overall_misses::total 181030 # number of overall misses
-system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester0 121091693 # number of UpgradeReq miss cycles
-system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester1 118634700 # number of UpgradeReq miss cycles
-system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester0 110743355 # number of UpgradeReq miss cycles
-system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester1 115936209 # number of UpgradeReq miss cycles
-system.l2subsys0.cache2.UpgradeReq_miss_latency::total 466405957 # number of UpgradeReq miss cycles
-system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester0 1562139697 # number of ReadExReq miss cycles
-system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester1 1549554832 # number of ReadExReq miss cycles
-system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester0 1596782082 # number of ReadExReq miss cycles
-system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester1 1559906979 # number of ReadExReq miss cycles
-system.l2subsys0.cache2.ReadExReq_miss_latency::total 6268383590 # number of ReadExReq miss cycles
-system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester0 2730087572 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester1 2753356756 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester0 2770847888 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester1 2694786136 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache2.ReadSharedReq_miss_latency::total 10949078352 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester0 4292227269 # number of demand (read+write) miss cycles
-system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester1 4302911588 # number of demand (read+write) miss cycles
-system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester0 4367629970 # number of demand (read+write) miss cycles
-system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester1 4254693115 # number of demand (read+write) miss cycles
-system.l2subsys0.cache2.demand_miss_latency::total 17217461942 # number of demand (read+write) miss cycles
-system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester0 4292227269 # number of overall miss cycles
-system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester1 4302911588 # number of overall miss cycles
-system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester0 4367629970 # number of overall miss cycles
-system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester1 4254693115 # number of overall miss cycles
-system.l2subsys0.cache2.overall_miss_latency::total 17217461942 # number of overall miss cycles
-system.l2subsys0.cache2.WritebackDirty_accesses::writebacks 45595 # number of WritebackDirty accesses(hits+misses)
-system.l2subsys0.cache2.WritebackDirty_accesses::total 45595 # number of WritebackDirty accesses(hits+misses)
-system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester0 3871 # number of UpgradeReq accesses(hits+misses)
-system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester1 3737 # number of UpgradeReq accesses(hits+misses)
-system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester0 3494 # number of UpgradeReq accesses(hits+misses)
-system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester1 3684 # number of UpgradeReq accesses(hits+misses)
-system.l2subsys0.cache2.UpgradeReq_accesses::total 14786 # number of UpgradeReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester0 16525 # number of ReadExReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester1 16361 # number of ReadExReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester0 16713 # number of ReadExReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester1 16746 # number of ReadExReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadExReq_accesses::total 66345 # number of ReadExReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester0 29339 # number of ReadSharedReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester1 29184 # number of ReadSharedReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester0 29768 # number of ReadSharedReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester1 29358 # number of ReadSharedReq accesses(hits+misses)
-system.l2subsys0.cache2.ReadSharedReq_accesses::total 117649 # number of ReadSharedReq accesses(hits+misses)
-system.l2subsys0.cache2.demand_accesses::l0subsys2.tester0 45864 # number of demand (read+write) accesses
-system.l2subsys0.cache2.demand_accesses::l0subsys2.tester1 45545 # number of demand (read+write) accesses
-system.l2subsys0.cache2.demand_accesses::l0subsys3.tester0 46481 # number of demand (read+write) accesses
-system.l2subsys0.cache2.demand_accesses::l0subsys3.tester1 46104 # number of demand (read+write) accesses
-system.l2subsys0.cache2.demand_accesses::total 183994 # number of demand (read+write) accesses
-system.l2subsys0.cache2.overall_accesses::l0subsys2.tester0 45864 # number of overall (read+write) accesses
-system.l2subsys0.cache2.overall_accesses::l0subsys2.tester1 45545 # number of overall (read+write) accesses
-system.l2subsys0.cache2.overall_accesses::l0subsys3.tester0 46481 # number of overall (read+write) accesses
-system.l2subsys0.cache2.overall_accesses::l0subsys3.tester1 46104 # number of overall (read+write) accesses
-system.l2subsys0.cache2.overall_accesses::total 183994 # number of overall (read+write) accesses
-system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester0 0.963834 # miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester1 0.960128 # miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester0 0.965655 # miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester1 0.950054 # miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_miss_rate::total 0.959894 # miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester0 0.997277 # miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester1 0.997800 # miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester0 0.997068 # miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester1 0.998209 # miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_miss_rate::total 0.997588 # miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester0 0.978050 # miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester1 0.975569 # miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester0 0.975746 # miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester1 0.975305 # miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_miss_rate::total 0.976166 # miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester0 0.984977 # miss rate for demand accesses
-system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester1 0.983555 # miss rate for demand accesses
-system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester0 0.983413 # miss rate for demand accesses
-system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester1 0.983624 # miss rate for demand accesses
-system.l2subsys0.cache2.demand_miss_rate::total 0.983891 # miss rate for demand accesses
-system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester0 0.984977 # miss rate for overall accesses
-system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester1 0.983555 # miss rate for overall accesses
-system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester0 0.983413 # miss rate for overall accesses
-system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester1 0.983624 # miss rate for overall accesses
-system.l2subsys0.cache2.overall_miss_rate::total 0.983891 # miss rate for overall accesses
-system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester0 32455.559635 # average UpgradeReq miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester1 33064.297659 # average UpgradeReq miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester0 32822.571132 # average UpgradeReq miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester1 33124.631143 # average UpgradeReq miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::total 32861.689354 # average UpgradeReq miss latency
-system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester0 94790.030158 # average ReadExReq miss latency
-system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester1 94919.132129 # average ReadExReq miss latency
-system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester0 95822.256481 # average ReadExReq miss latency
-system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester1 93318.196877 # average ReadExReq miss latency
-system.l2subsys0.cache2.ReadExReq_avg_miss_latency::total 94710.033845 # average ReadExReq miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester0 95141.577696 # average ReadSharedReq miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester1 96707.413017 # average ReadSharedReq miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester0 95395.162432 # average ReadSharedReq miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester1 94114.697587 # average ReadSharedReq miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::total 95337.875850 # average ReadSharedReq miss latency
-system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester0 95013.331909 # average overall miss latency
-system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester1 96055.710063 # average overall miss latency
-system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester0 95550.863487 # average overall miss latency
-system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester1 93821.101127 # average overall miss latency
-system.l2subsys0.cache2.demand_avg_miss_latency::total 95108.335315 # average overall miss latency
-system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester0 95013.331909 # average overall miss latency
-system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester1 96055.710063 # average overall miss latency
-system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester0 95550.863487 # average overall miss latency
-system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester1 93821.101127 # average overall miss latency
-system.l2subsys0.cache2.overall_avg_miss_latency::total 95108.335315 # average overall miss latency
-system.l2subsys0.cache2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2subsys0.cache2.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2subsys0.cache2.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2subsys0.cache2.blocked::no_targets 0 # number of cycles access was blocked
-system.l2subsys0.cache2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2subsys0.cache2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2subsys0.cache2.writebacks::writebacks 44893 # number of writebacks
-system.l2subsys0.cache2.writebacks::total 44893 # number of writebacks
-system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester0 353 # number of ReadExReq MSHR hits
-system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester1 327 # number of ReadExReq MSHR hits
-system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester0 327 # number of ReadExReq MSHR hits
-system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester1 345 # number of ReadExReq MSHR hits
-system.l2subsys0.cache2.ReadExReq_mshr_hits::total 1352 # number of ReadExReq MSHR hits
-system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester0 566 # number of ReadSharedReq MSHR hits
-system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester1 596 # number of ReadSharedReq MSHR hits
-system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester0 556 # number of ReadSharedReq MSHR hits
-system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester1 587 # number of ReadSharedReq MSHR hits
-system.l2subsys0.cache2.ReadSharedReq_mshr_hits::total 2305 # number of ReadSharedReq MSHR hits
-system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester0 919 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester1 923 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester0 883 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester1 932 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache2.demand_mshr_hits::total 3657 # number of demand (read+write) MSHR hits
-system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester0 919 # number of overall MSHR hits
-system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester1 923 # number of overall MSHR hits
-system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester0 883 # number of overall MSHR hits
-system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester1 932 # number of overall MSHR hits
-system.l2subsys0.cache2.overall_mshr_hits::total 3657 # number of overall MSHR hits
-system.l2subsys0.cache2.CleanEvict_mshr_misses::writebacks 41439 # number of CleanEvict MSHR misses
-system.l2subsys0.cache2.CleanEvict_mshr_misses::total 41439 # number of CleanEvict MSHR misses
-system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester0 3731 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester1 3588 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester0 3374 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester1 3500 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache2.UpgradeReq_mshr_misses::total 14193 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester0 16127 # number of ReadExReq MSHR misses
-system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester1 15998 # number of ReadExReq MSHR misses
-system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester0 16337 # number of ReadExReq MSHR misses
-system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester1 16371 # number of ReadExReq MSHR misses
-system.l2subsys0.cache2.ReadExReq_mshr_misses::total 64833 # number of ReadExReq MSHR misses
-system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester0 28129 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester1 27875 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester0 28490 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester1 28046 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache2.ReadSharedReq_mshr_misses::total 112540 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester0 44256 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester1 43873 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester0 44827 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester1 44417 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache2.demand_mshr_misses::total 177373 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester0 44256 # number of overall MSHR misses
-system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester1 43873 # number of overall MSHR misses
-system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester0 44827 # number of overall MSHR misses
-system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester1 44417 # number of overall MSHR misses
-system.l2subsys0.cache2.overall_mshr_misses::total 177373 # number of overall MSHR misses
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester0 86821804 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester1 85216922 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester0 79514942 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester1 83404063 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::total 334957731 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester0 1390062688 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester1 1380024742 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester0 1423675349 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester1 1385907063 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::total 5579669842 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester0 2433916719 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester1 2458901936 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester0 2472187719 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester1 2398872655 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::total 9763879029 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester0 3823979407 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester1 3838926678 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester0 3895863068 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester1 3784779718 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache2.demand_mshr_miss_latency::total 15343548871 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester0 3823979407 # number of overall MSHR miss cycles
-system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester1 3838926678 # number of overall MSHR miss cycles
-system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester0 3895863068 # number of overall MSHR miss cycles
-system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester1 3784779718 # number of overall MSHR miss cycles
-system.l2subsys0.cache2.overall_mshr_miss_latency::total 15343548871 # number of overall MSHR miss cycles
-system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester0 0.963834 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester1 0.960128 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester0 0.965655 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester1 0.950054 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::total 0.959894 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester0 0.975915 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester1 0.977813 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester0 0.977503 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester1 0.977607 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::total 0.977210 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester0 0.958758 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester1 0.955147 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester0 0.957068 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester1 0.955310 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::total 0.956574 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester0 0.964940 # mshr miss rate for demand accesses
-system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester1 0.963289 # mshr miss rate for demand accesses
-system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester0 0.964416 # mshr miss rate for demand accesses
-system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester1 0.963409 # mshr miss rate for demand accesses
-system.l2subsys0.cache2.demand_mshr_miss_rate::total 0.964015 # mshr miss rate for demand accesses
-system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester0 0.964940 # mshr miss rate for overall accesses
-system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester1 0.963289 # mshr miss rate for overall accesses
-system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester0 0.964416 # mshr miss rate for overall accesses
-system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester1 0.963409 # mshr miss rate for overall accesses
-system.l2subsys0.cache2.overall_mshr_miss_rate::total 0.964015 # mshr miss rate for overall accesses
-system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester0 23270.384347 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester1 23750.535674 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester0 23566.965619 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester1 23829.732286 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::total 23600.206510 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester0 86194.747194 # average ReadExReq mshr miss latency
-system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester1 86262.329166 # average ReadExReq mshr miss latency
-system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester0 87144.233886 # average ReadExReq mshr miss latency
-system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester1 84656.225215 # average ReadExReq mshr miss latency
-system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::total 86062.188114 # average ReadExReq mshr miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester0 86526.955064 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester1 88211.728646 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester0 86773.875711 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester1 85533.504065 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::total 86759.188102 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester0 86405.897664 # average overall mshr miss latency
-system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester1 87500.892987 # average overall mshr miss latency
-system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester0 86908.851094 # average overall mshr miss latency
-system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester1 85210.160929 # average overall mshr miss latency
-system.l2subsys0.cache2.demand_avg_mshr_miss_latency::total 86504.422156 # average overall mshr miss latency
-system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester0 86405.897664 # average overall mshr miss latency
-system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester1 87500.892987 # average overall mshr miss latency
-system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86908.851094 # average overall mshr miss latency
-system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 85210.160929 # average overall mshr miss latency
-system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 86504.422156 # average overall mshr miss latency
-system.l2subsys0.cache3.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.cache3.tags.replacements 154799 # number of replacements
-system.l2subsys0.cache3.tags.tagsinuse 1523.428503 # Cycle average of tags in use
-system.l2subsys0.cache3.tags.total_refs 83314 # Total number of references to valid blocks.
-system.l2subsys0.cache3.tags.sampled_refs 156330 # Sample count of references to valid blocks.
-system.l2subsys0.cache3.tags.avg_refs 0.532937 # Average number of references to valid blocks.
-system.l2subsys0.cache3.tags.warmup_cycle 238966000 # Cycle when the warmup percentage was hit.
-system.l2subsys0.cache3.tags.occ_blocks::writebacks 188.347514 # Average occupied blocks per requestor
-system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester0 343.217725 # Average occupied blocks per requestor
-system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester1 332.812126 # Average occupied blocks per requestor
-system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester0 334.052084 # Average occupied blocks per requestor
-system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester1 324.999055 # Average occupied blocks per requestor
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-system.l2subsys0.cache3.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id
-system.l2subsys0.cache3.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
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-system.l2subsys0.cache3.WritebackDirty_hits::total 46868 # number of WritebackDirty hits
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-system.l2subsys0.cache3.UpgradeReq_hits::l0subsys4.tester1 191 # number of UpgradeReq hits
-system.l2subsys0.cache3.UpgradeReq_hits::l0subsys5.tester0 147 # number of UpgradeReq hits
-system.l2subsys0.cache3.UpgradeReq_hits::l0subsys5.tester1 196 # number of UpgradeReq hits
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-system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester0 3449 # number of UpgradeReq misses
-system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester1 3509 # number of UpgradeReq misses
-system.l2subsys0.cache3.UpgradeReq_misses::total 13774 # number of UpgradeReq misses
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-system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester1 29836 # number of ReadSharedReq misses
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-system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester1 29435 # number of ReadSharedReq misses
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-system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester0 1612917211 # number of ReadExReq miss cycles
-system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester1 1594343846 # number of ReadExReq miss cycles
-system.l2subsys0.cache3.ReadExReq_miss_latency::total 6391002779 # number of ReadExReq miss cycles
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-system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester1 2832936908 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester0 2869238005 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester1 2817936974 # number of ReadSharedReq miss cycles
-system.l2subsys0.cache3.ReadSharedReq_miss_latency::total 11345132672 # number of ReadSharedReq miss cycles
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-system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester1 4412280820 # number of overall miss cycles
-system.l2subsys0.cache3.overall_miss_latency::total 17736135451 # number of overall miss cycles
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-system.l2subsys0.cache3.WritebackDirty_accesses::total 46868 # number of WritebackDirty accesses(hits+misses)
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-system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester1 0.947099 # miss rate for UpgradeReq accesses
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-system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester1 0.997615 # miss rate for ReadExReq accesses
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-system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester1 0.978134 # miss rate for ReadSharedReq accesses
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-system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester1 32505.708464 # average UpgradeReq miss latency
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-system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester1 95287.105307 # average ReadExReq miss latency
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-system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester1 94950.291862 # average ReadSharedReq miss latency
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-system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester1 95734.227077 # average ReadSharedReq miss latency
-system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::total 95796.104636 # average ReadSharedReq miss latency
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-system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester1 541 # number of ReadSharedReq MSHR hits
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-system.l2subsys0.cache3.overall_mshr_hits::l0subsys5.tester0 831 # number of overall MSHR hits
-system.l2subsys0.cache3.overall_mshr_hits::l0subsys5.tester1 832 # number of overall MSHR hits
-system.l2subsys0.cache3.overall_mshr_hits::total 3509 # number of overall MSHR hits
-system.l2subsys0.cache3.CleanEvict_mshr_misses::writebacks 43347 # number of CleanEvict MSHR misses
-system.l2subsys0.cache3.CleanEvict_mshr_misses::total 43347 # number of CleanEvict MSHR misses
-system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys4.tester0 3395 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys4.tester1 3421 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys5.tester0 3449 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys5.tester1 3509 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache3.UpgradeReq_mshr_misses::total 13774 # number of UpgradeReq MSHR misses
-system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys4.tester0 16071 # number of ReadExReq MSHR misses
-system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys4.tester1 16670 # number of ReadExReq MSHR misses
-system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester0 16723 # number of ReadExReq MSHR misses
-system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester1 16441 # number of ReadExReq MSHR misses
-system.l2subsys0.cache3.ReadExReq_mshr_misses::total 65905 # number of ReadExReq MSHR misses
-system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester0 28562 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester1 29144 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester0 29572 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester1 28894 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache3.ReadSharedReq_mshr_misses::total 116172 # number of ReadSharedReq MSHR misses
-system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester0 44633 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester1 45814 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester0 46295 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester1 45335 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache3.demand_mshr_misses::total 182077 # number of demand (read+write) MSHR misses
-system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester0 44633 # number of overall MSHR misses
-system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester1 45814 # number of overall MSHR misses
-system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester0 46295 # number of overall MSHR misses
-system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester1 45335 # number of overall MSHR misses
-system.l2subsys0.cache3.overall_mshr_misses::total 182077 # number of overall MSHR misses
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester0 81963023 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester1 80624239 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester0 80607785 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester1 81849121 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::total 325044168 # number of UpgradeReq MSHR miss cycles
-system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester0 1404906880 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester1 1431588330 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester0 1436530645 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester1 1420292171 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::total 5693318026 # number of ReadExReq MSHR miss cycles
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester0 2526781875 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester1 2523316581 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester0 2559586993 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester1 2514975762 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::total 10124661211 # number of ReadSharedReq MSHR miss cycles
-system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester0 3931688755 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester1 3954904911 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester0 3996117638 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester1 3935267933 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache3.demand_mshr_miss_latency::total 15817979237 # number of demand (read+write) MSHR miss cycles
-system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester0 3931688755 # number of overall MSHR miss cycles
-system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester1 3954904911 # number of overall MSHR miss cycles
-system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester0 3996117638 # number of overall MSHR miss cycles
-system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester1 3935267933 # number of overall MSHR miss cycles
-system.l2subsys0.cache3.overall_mshr_miss_latency::total 15817979237 # number of overall MSHR miss cycles
-system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester0 0.953652 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester1 0.947121 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester0 0.959121 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester1 0.947099 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::total 0.951703 # mshr miss rate for UpgradeReq accesses
-system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester0 0.981375 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester1 0.974284 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester0 0.980936 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester1 0.980265 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::total 0.979185 # mshr miss rate for ReadExReq accesses
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester0 0.964835 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester1 0.950865 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester0 0.961378 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester1 0.960157 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::total 0.959259 # mshr miss rate for ReadSharedReq accesses
-system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester0 0.970726 # mshr miss rate for demand accesses
-system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester1 0.959255 # mshr miss rate for demand accesses
-system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester0 0.968353 # mshr miss rate for demand accesses
-system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester1 0.967353 # mshr miss rate for demand accesses
-system.l2subsys0.cache3.demand_mshr_miss_rate::total 0.966377 # mshr miss rate for demand accesses
-system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester0 0.970726 # mshr miss rate for overall accesses
-system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester1 0.959255 # mshr miss rate for overall accesses
-system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester0 0.968353 # mshr miss rate for overall accesses
-system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester1 0.967353 # mshr miss rate for overall accesses
-system.l2subsys0.cache3.overall_mshr_miss_rate::total 0.966377 # mshr miss rate for overall accesses
-system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester0 24142.274816 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester1 23567.447822 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester0 23371.349667 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester1 23325.483329 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::total 23598.385945 # average UpgradeReq mshr miss latency
-system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester0 87418.759256 # average ReadExReq mshr miss latency
-system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester1 85878.124175 # average ReadExReq mshr miss latency
-system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester0 85901.491658 # average ReadExReq mshr miss latency
-system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester1 86387.213126 # average ReadExReq mshr miss latency
-system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::total 86386.738882 # average ReadExReq mshr miss latency
-system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester0 88466.559590 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester1 86580.997152 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester0 86554.409340 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester1 87041.453658 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::total 87152.336286 # average ReadSharedReq mshr miss latency
-system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester0 88089.278225 # average overall mshr miss latency
-system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester1 86325.247981 # average overall mshr miss latency
-system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester0 86318.557900 # average overall mshr miss latency
-system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester1 86804.189545 # average overall mshr miss latency
-system.l2subsys0.cache3.demand_avg_mshr_miss_latency::total 86875.218929 # average overall mshr miss latency
-system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester0 88089.278225 # average overall mshr miss latency
-system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester1 86325.247981 # average overall mshr miss latency
-system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86318.557900 # average overall mshr miss latency
-system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 86804.189545 # average overall mshr miss latency
-system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 86875.218929 # average overall mshr miss latency
-system.l2subsys0.checkers.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.tester.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.tester.numPackets 67448 # Number of packets generated
-system.l2subsys0.tester.numRetries 90 # Number of retries
-system.l2subsys0.tester.retryTicks 3855703 # Time spent waiting due to back-pressure (ticks)
-system.l2subsys0.xbar.snoop_filter.tot_requests 1069827 # Total number of requests made to the snoop filter.
-system.l2subsys0.xbar.snoop_filter.hit_single_requests 521153 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l2subsys0.xbar.snoop_filter.hit_multi_requests 129649 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l2subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l2subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
-system.l2subsys0.xbar.trans_dist::ReadResp 375461 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1760 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::WritebackDirty 148958 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::CleanEvict 268634 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::UpgradeReq 51775 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::UpgradeResp 28212 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::ReadExReq 223238 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::ReadExResp 218900 # Transaction distribution
-system.l2subsys0.xbar.trans_dist::ReadSharedReq 377222 # Transaction distribution
-system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache1.mem_side::system.physmem.port 454786 # Packet count per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache2.mem_side::system.physmem.port 447989 # Packet count per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache3.mem_side::system.physmem.port 462519 # Packet count per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache0.mem_side::system.physmem.port 127384 # Packet count per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_count::total 1492678 # Packet count per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache1.mem_side::system.physmem.port 11217984 # Cumulative packet size per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache2.mem_side::system.physmem.port 11005568 # Cumulative packet size per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache3.mem_side::system.physmem.port 11412416 # Cumulative packet size per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache0.mem_side::system.physmem.port 2959808 # Cumulative packet size per connected master and slave (bytes)
-system.l2subsys0.xbar.pkt_size::total 36595776 # Cumulative packet size per connected master and slave (bytes)
-system.l2subsys0.xbar.snoops 210714 # Total snoops (count)
-system.l2subsys0.xbar.snoopTraffic 11089280 # Total snoop traffic (bytes)
-system.l2subsys0.xbar.snoop_fanout::samples 652235 # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::mean 0.520105 # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::stdev 0.790254 # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::0 420662 64.50% 64.50% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::1 138520 21.24% 85.73% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::2 78448 12.03% 97.76% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::3 14605 2.24% 100.00% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::max_value 3 # Request fanout histogram
-system.l2subsys0.xbar.snoop_fanout::total 652235 # Request fanout histogram
-system.l2subsys0.xbar.reqLayer0.occupancy 1600277509 # Layer occupancy (ticks)
-system.l2subsys0.xbar.reqLayer0.utilization 16.0 # Layer utilization (%)
-system.l2subsys0.xbar.respLayer0.occupancy 643009360 # Layer occupancy (ticks)
-system.l2subsys0.xbar.respLayer0.utilization 6.4 # Layer utilization (%)
-system.l2subsys0.xbar.respLayer1.occupancy 635003682 # Layer occupancy (ticks)
-system.l2subsys0.xbar.respLayer1.utilization 6.4 # Layer utilization (%)
-system.l2subsys0.xbar.respLayer2.occupancy 652235888 # Layer occupancy (ticks)
-system.l2subsys0.xbar.respLayer2.utilization 6.5 # Layer utilization (%)
-system.l2subsys0.xbar.respLayer3.occupancy 189829895 # Layer occupancy (ticks)
-system.l2subsys0.xbar.respLayer3.utilization 1.9 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
projects / gem5.git / commitdiff