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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Oct 2023 10:26:18 +0000 (11:26 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 29 Oct 2023 08:54:37 +0000 (08:54 +0000)
openpower/isa/fixedloadshift.mdwn patch | blob | history

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index acdb940cd5f5c1e02d4036458a7e70377acb6aad..a82c7100521c990a78c123807b2ed94aa28dacf4 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -43,9 +43,8 @@ Description:
     Let the effective address (EA) be the sum of the contents of
     register RB shifted by (SH+1), and (RA|0).
 
-    The byte in storage addressed by EA is loaded into
-    RT[56:63]. RT[0:55] are set to 0.
-
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
 
 Special Registers Altered: