cris: Enable 32-bit shifts, clz, bswap, umin to set condition codes.

Enables dropping of compares with zero of the result, through
any CCmode substitution.

gcc:
	* config/cris/cris.md
	("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
	from "<shlr>si3".
	("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
	from "clzsi2".
	("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
	from "bswapsi2".
	("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 54073e2749d1d42b6e24d27d698adb7e4184890b..9aca1c3310ecf5b8f66008ce955aadcb0c529cef 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -145,6 +145,13 @@
        from "xorsi3".
        ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
        from "one_cmplsi2".
+       ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
+       from "<shlr>si3".
+       ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
+       from "clzsi2".
+       ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
+       from "bswapsi2".
+       ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
 
 2020-05-08  Vladimir Makarov  <vmakarov@redhat.com>
 

diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 6faef6cda0279fe6ddbc0140bbfbdea203eaed2c..c085e26602e6201bc85a5a94fd7ae23503c044f4 100644 (file)
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1758,7 +1758,7 @@
 \f
 ;; Arithmetic/Logical shift right (and SI left).
 
-(define_insn "<shlr>si3"
+(define_insn "<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (shift:SI (match_operand:SI 1 "register_operand" "0")
                  (match_operand:SI 2 "nonmemory_operand" "Kcr")))
@@ -1918,7 +1918,7 @@
   ""
   "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
 
-(define_insn "clzsi2"
+(define_insn "<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (clz:SI (match_operand:SI 1 "register_operand" "r")))
    (clobber (reg:CC CRIS_CC0_REGNUM))]
@@ -1926,7 +1926,7 @@
   "lz %1,%0"
   [(set_attr "slottable" "yes")])
 
-(define_insn "bswapsi2"
+(define_insn "<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (bswap:SI (match_operand:SI 1 "register_operand" "0")))
    (clobber (reg:CC CRIS_CC0_REGNUM))]
@@ -1979,7 +1979,7 @@
   ""
   "")
 
-(define_insn "*uminsi3"
+(define_insn "*uminsi3<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand"          "=r,r, r,r")
        (umin:SI  (match_operand:SI 1 "register_operand" "%0,0, 0,r")
                  (match_operand:SI 2 "general_operand"   "r,Q>,g,!To")))