cpu/mor1kx: Adding verilog include directory.

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 7428211e9c10fd2a3c421c6eb5013b20b65e989c..c53c6e5e58f5c54bd1c1d44417ecbe086aad7619 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -122,3 +122,4 @@ class MOR1KX(Module):
             os.path.abspath(os.path.dirname(__file__)),
             "verilog", "rtl", "verilog")
         platform.add_source_dir(vdir)
+        platform.add_verilog_include_path(vdir)