start on a new update

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+So many things happened since the last update they actually need to go
+in the main update, even in summary form.  One big thing: Raptor Engineering
+sponsored us with remote access to a TALOS II Workstation!
+
+# Introduction
+
+Here's the summary (if it can be called a summary):
+
+* [An announcement](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/004995.html)
+  that we got the funding (which is open to anyone - hint, hint) resulted in
+  at least three people reaching out to join the team.  "We don't need
+  permission to own our own hardware" got a *really* positive reaction.
+* New team member, Jock (hello Jock!) starts on the coriolis2 layout,
+  after Jean-Paul from LIP6.fr helped to dramatically improve how coriolis2
+  can be used.  This resulted in a
+  [tutoria](https://libre-riscv.org/HDL_workflow/coriolis2/) and a
+  [huge bugreport discussion](http://bugs.libre-riscv.org/show_bug.cgi?id=178)
+* Work has started on the
+  [POWER ISA decoder](http://bugs.libre-riscv.org/show_bug.cgi?id=186),
+  verified through
+  [calling GNU AS](https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/decoder/test/test_decoder_gas.py;h=9238d3878d964907c5569a3468d6895effb7dc02;hb=56d145e42ac75626423915af22d1493f1e7bb143) (yes, really!)
+  and on a mini-simulator
+  [calling qemu](https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/qemu.py;h=9eb103bae227e00a2a1d2ec4f43d7e39e4f44960;hb=56d145e42ac75626423915af22d1493f1e7bb143)
+  for verification.
+* Jacob's algorithmic library grows
+  [Power FP compatibility](http://bugs.libre-riscv.org/show_bug.cgi?id=258)
+  and python bindings. 
+* A Conference call with OpenPOWER Foundation Director, Hugh, and Timothy
+  Pearson from RaptorCS has been established every two weeks.
+* Tim sponsors our team with access to a Monster Talos II system with a
+  whopping 128 GB RAM.  htop lists a staggering 72 cores (18 real
+  with 4-way hyperthreading).
+* [Epic MegaGrants](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005262.html)
+  reached out (hello!) to say they're still considering our
+  request.
+* A marathon 3-hour session with [NLNet](http://nlnet.nl) resulted
+  in the completion of the
+  [Milestone tasks list(s)](http://bugs.libre-riscv.org/buglist.cgi?component=Milestones&list_id=567&resolution=---)
+  and a
+  [boat-load](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/thread.html)
+  of bugreports to the list.
+* Immanuel Yehowshua is participating in the Georgia Tech
+  [https://create-x.gatech.edu/](Create-X) Programme, and is establishing
+  a Public Benefit Corporation in Atlanta, as an ethical vehicle for VC
+  Funding.
+* A [Load/Store Buffer](http://bugs.libre-riscv.org/show_bug.cgi?id=216)
+  design and
+  [further discussion](http://bugs.libre-riscv.org/show_bug.cgi?id=257)
+  including on
+  [comp.arch](https://groups.google.com/forum/#!topic/comp.arch/cbGAlcCjiZE)
+  inspired additional writeup
+  on the
+  [6600 scoreboard](https://libre-riscv.org/3d_gpu/architecture/6600scoreboard/)
+  page.
+
+Well dang, as you can see, suddenly it just went ballistic.  There's
+almost certainly things left off the list.  For such a small team there's
+a heck of a lot going on.  We have an awful lot to do, in a short amount
+of time: the 180nm tape-out is in October 2020 - only 7 months away.
+
+# POWER ISA decoder and Simulator
+
+