Add new tests.

diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v
new file mode 100644 (file)
index 0000000..f82cc2e
--- /dev/null
+++ b/tests/ice40/alu.v
@@ -0,0 +1,19 @@
+module top (
+       input clock,
+       input [31:0] dinA, dinB,
+       input [2:0] opcode,
+       output reg [31:0] dout
+);
+       always @(posedge clock) begin
+               case (opcode)
+               0: dout <= dinA + dinB;
+               1: dout <= dinA - dinB;
+               2: dout <= dinA >> dinB;
+               3: dout <= $signed(dinA) >>> dinB;
+               4: dout <= dinA << dinB;
+               5: dout <= dinA & dinB;
+               6: dout <= dinA | dinB;
+               7: dout <= dinA ^ dinB;
+               endcase
+       end
+endmodule

diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys
new file mode 100644 (file)
index 0000000..bd859ef
--- /dev/null
+++ b/tests/ice40/alu.ys
@@ -0,0 +1,11 @@
+read_verilog alu.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 62 t:SB_CARRY
+select -assert-count 32 t:SB_DFF
+select -assert-count 655 t:SB_LUT4
+select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v
new file mode 100644 (file)
index 0000000..52852f8
--- /dev/null
+++ b/tests/ice40/counter.v
@@ -0,0 +1,17 @@
+module top    (\r
+out,\r
+clk,\r
+reset\r
+);\r
+    output [7:0] out;\r
+    input clk, reset;\r
+    reg [7:0] out;\r
+\r
+    always @(posedge clk, posedge reset)\r
+               if (reset) begin\r
+                       out <= 8'b0 ;\r
+               end else\r
+                       out <= out + 1;\r
+\r
+\r
+endmodule\r

diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys
new file mode 100644 (file)
index 0000000..fb32e67
--- /dev/null
+++ b/tests/ice40/counter.ys
@@ -0,0 +1,11 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 7 t:SB_CARRY
+select -assert-count 8 t:SB_DFFR
+select -assert-count 8 t:SB_LUT4
+select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/fsm.v b/tests/ice40/fsm.v
new file mode 100644 (file)
index 0000000..0605bd1
--- /dev/null
+++ b/tests/ice40/fsm.v
@@ -0,0 +1,73 @@
+ module fsm (\r
+ clock,\r
+ reset,\r
+ req_0,\r
+ req_1,\r
+ gnt_0,\r
+ gnt_1\r
+ );\r
+ input   clock,reset,req_0,req_1;\r
+ output  gnt_0,gnt_1;\r
+ wire    clock,reset,req_0,req_1;\r
+ reg     gnt_0,gnt_1;\r
+\r
+ parameter SIZE = 3           ;\r
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
+\r
+ reg [SIZE-1:0] state;\r
+ reg [SIZE-1:0] next_state;\r
+\r
+ always @ (posedge clock)\r
+ begin : FSM\r
+ if (reset == 1'b1) begin\r
+   state <=  #1  IDLE;\r
+   gnt_0 <= 0;\r
+   gnt_1 <= 0;\r
+ end else\r
+  case(state)\r
+    IDLE : if (req_0 == 1'b1) begin\r
+                 state <=  #1  GNT0;\r
+                 gnt_0 <= 1;\r
+               end else if (req_1 == 1'b1) begin\r
+                 gnt_1 <= 1;\r
+                 state <=  #1  GNT0;\r
+               end else begin\r
+                 state <=  #1  IDLE;\r
+               end\r
+    GNT0 : if (req_0 == 1'b1) begin\r
+                 state <=  #1  GNT0;\r
+               end else begin\r
+                 gnt_0 <= 0;\r
+                 state <=  #1  IDLE;\r
+               end\r
+    GNT1 : if (req_1 == 1'b1) begin\r
+                 state <=  #1  GNT2;\r
+                                gnt_1 <= req_0;\r
+               end\r
+    GNT2 : if (req_0 == 1'b1) begin\r
+                 state <=  #1  GNT1;\r
+                                gnt_1 <= req_1;\r
+               end\r
+    default : state <=  #1  IDLE;\r
+ endcase\r
+ end\r
+\r
+ endmodule\r
+\r
+ module top (\r
+input clk,\r
+input rst,\r
+input a,\r
+input b,\r
+output g0,\r
+output g1\r
+);\r
+\r
+fsm u_fsm ( .clock(clk),\r
+            .reset(rst),\r
+            .req_0(a),\r
+            .req_1(b),\r
+            .gnt_0(g0),\r
+            .gnt_1(g1));\r
+\r
+endmodule\r

diff --git a/tests/ice40/fsm.ys b/tests/ice40/fsm.ys
new file mode 100644 (file)
index 0000000..4cc8629
--- /dev/null
+++ b/tests/ice40/fsm.ys
@@ -0,0 +1,13 @@
+read_verilog fsm.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 2 t:SB_DFFESR
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 1 t:SB_DFFSS
+select -assert-count 13 t:SB_LUT4
+select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/logic.v b/tests/ice40/logic.v
new file mode 100644 (file)
index 0000000..e5343ca
--- /dev/null
+++ b/tests/ice40/logic.v
@@ -0,0 +1,18 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+   assign     B1 =  in[0] & in[1];
+   assign     B2 =  in[0] | in[1];
+   assign     B3 =  in[0] ~& in[1];
+   assign     B4 =  in[0] ~| in[1];
+   assign     B5 =  in[0] ^ in[1];
+   assign     B6 =  in[0] ~^ in[1];
+   assign     B7 =  ~in[0];
+   assign     B8 =  in[0];
+   assign     B9 =  in[0:1] && in [2:3];
+   assign     B10 =  in[0:1] || in [2:3];
+
+endmodule

diff --git a/tests/ice40/logic.ys b/tests/ice40/logic.ys
new file mode 100644 (file)
index 0000000..fc5e5b1
--- /dev/null
+++ b/tests/ice40/logic.ys
@@ -0,0 +1,7 @@
+read_verilog logic.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 9 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v
new file mode 100644 (file)
index 0000000..c556325
--- /dev/null
+++ b/tests/ice40/shifter.v
@@ -0,0 +1,22 @@
+module top    (\r
+out,\r
+clk,\r
+in\r
+);\r
+    output [7:0] out;\r
+    input signed clk, in;\r
+    reg signed [7:0] out = 0;\r
+\r
+    always @(posedge clk)\r
+       begin\r
+`ifndef BUG\r
+               out    <= out >> 1;\r
+               out[7] <= in;\r
+`else\r
+\r
+               out    <= out << 1;\r
+               out[7] <= in;\r
+`endif\r
+       end\r
+\r
+endmodule\r

diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys
new file mode 100644 (file)
index 0000000..47d95d2
--- /dev/null
+++ b/tests/ice40/shifter.ys
@@ -0,0 +1,9 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D