Fixed inserting of Q-inverters in dfflibmap

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 7e39040c47a97fbc0fccba305910ef318ab949b8..07993b868c2e925e09b8a4948fde5071d6cd2751 100644 (file)
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -409,6 +409,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
                        if ('A' <= port.second && port.second <= 'Z') {
                                sig = cell_connections[std::string("\\") + port.second];
                        } else
+                       if (port.second == 'q') {
+                               RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
+                               sig = module->addWire(NEW_ID, SIZE(old_sig));
+                               module->addNotGate(NEW_ID, sig, old_sig);
+                       } else
                        if ('a' <= port.second && port.second <= 'z') {
                                sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
                                sig = module->NotGate(NEW_ID, sig);