cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
}
- if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV) {
+ if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV ||
+ (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) {
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
}
S_0085F0_CB11_DEST_BASE_ENA(1);
}
- if (rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) {
+ if (rctx->b.chip_class >= R700 &&
+ rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) {
cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
S_0085F0_SO1_DEST_BASE_ENA(1) |
S_0085F0_SO2_DEST_BASE_ENA(1) |
}
/* Workaround for buggy flushing on some R6xx chipsets. */
- if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV &&
+ if ((rctx->b.flags & (R600_CONTEXT_FLUSH_AND_INV |
+ R600_CONTEXT_STREAMOUT_FLUSH)) &&
(rctx->b.family == CHIP_RV670 ||
rctx->b.family == CHIP_RS780 ||
rctx->b.family == CHIP_RS880)) {
}
rctx->streamout.begin_emitted = false;
-
- if (rctx->chip_class >= R700) {
- rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
- } else {
- rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
- }
+ rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
}
/* STREAMOUT CONFIG DERIVED STATE