--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright 2021 Google Inc.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+let {{
+
+class ArmInstObjParams(InstObjParams):
+ def __init__(self, *args, **kwargs):
+ super(ArmInstObjParams, self).__init__(*args, **kwargs)
+ self.padSrcRegIdx(self.operands.numDestRegs)
+
+}};
// The most basic instruction format...
def format BasicOp(code, *flags) {{
- iop = InstObjParams(name, Name, 'ArmStaticInst', code, flags)
+ iop = ArmInstObjParams(name, Name, 'ArmStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
shift, OptShiftRmCondCodesC);
op2 = op2;''' + code
- regIop = InstObjParams(name, Name, 'PredIntOp',
- {"code": regCode,
- "predicate_test": pickPredicate(regCode)})
- immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
- {"code": immCode,
- "predicate_test": pickPredicate(imm)})
- regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
- {"code": regCode + regCcCode,
- "predicate_test": pickPredicate(regCode + regCcCode)})
- immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
- {"code": immCode + immCcCode,
- "predicate_test": pickPredicate(immCode + immCcCode)})
+ regIop = ArmInstObjParams(name, Name, 'PredIntOp',
+ { "code" : regCode, "predicate_test" : pickPredicate(regCode) })
+ immIop = ArmInstObjParams(name, Name + "Imm", 'PredIntOp',
+ { "code" : immCode, "predicate_test" : pickPredicate(imm) })
+ regCcIop = ArmInstObjParams(name, Name + "Cc", 'PredIntOp',
+ { "code" : regCode + regCcCode,
+ "predicate_test" : pickPredicate(regCode + regCcCode) })
+ immCcIop = ArmInstObjParams(name, Name + "ImmCc", 'PredIntOp',
+ { "code" : immCode + immCcCode,
+ "predicate_test" : pickPredicate(immCode + immCcCode) })
header_output = BasicDeclare.subst(regIop) + \
BasicDeclare.subst(immIop) + \
BasicDeclare.subst(regCcIop) + \
def format DataImmOp(code, flagtype = logic) {{
code += "resTemp = resTemp;"
- iop = InstObjParams(name, Name, 'PredImmOp',
- {"code": code,
- "predicate_test": pickPredicate(code)})
- ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
- {"code": code + getImmCcCode(flagtype),
- "predicate_test": pickPredicate(code + getImmCcCode(flagtype))})
+ iop = ArmInstObjParams(name, Name, 'PredImmOp',
+ { "code" : code, "predicate_test" : pickPredicate(code) })
+ ccIop = ArmInstObjParams(name, Name + "Cc", 'PredImmOp',
+ { "code" : code + getImmCcCode(flagtype),
+ "predicate_test" :
+ pickPredicate(code + getImmCcCode(flagtype)) })
header_output = BasicDeclare.subst(iop) + \
BasicDeclare.subst(ccIop)
decoder_output = BasicConstructor.subst(iop) + \
}};
def format PredOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'PredOp',
- {"code": code,
- "predicate_test": pickPredicate(code)},
- opt_flags)
+ iop = ArmInstObjParams(name, Name, 'PredOp',
+ { "code" : code, "predicate_test" : pickPredicate(code) },
+ opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
def format PredImmOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'PredImmOp',
- {"code": code,
- "predicate_test": pickPredicate(code)},
- opt_flags)
+ iop = ArmInstObjParams(name, Name, 'PredImmOp',
+ { "code" : code, "predicate_test": pickPredicate(code) },
+ opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
//
def format FailUnimpl() {{
- iop = InstObjParams(name, 'FailUnimplemented')
+ iop = ArmInstObjParams(name, 'FailUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
def format WarnUnimpl() {{
- iop = InstObjParams(name, 'WarnUnimplemented')
+ iop = ArmInstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
let {{
movzCode = 'Dest64 = ((uint64_t)imm1) << imm2;'
- movzIop = InstObjParams("movz", "Movz", "RegImmImmOp", movzCode, [])
+ movzIop = ArmInstObjParams("movz", "Movz", "RegImmImmOp", movzCode, [])
header_output += RegImmImmOpDeclare.subst(movzIop)
decoder_output += RegImmImmOpConstructor.subst(movzIop)
exec_output += BasicExecute.subst(movzIop)
movkCode = 'Dest64 = insertBits(Dest64, imm2 + 15, imm2, imm1);'
- movkIop = InstObjParams("movk", "Movk", "RegImmImmOp", movkCode, [])
+ movkIop = ArmInstObjParams("movk", "Movk", "RegImmImmOp", movkCode, [])
header_output += RegImmImmOpDeclare.subst(movkIop)
decoder_output += RegImmImmOpConstructor.subst(movkIop)
exec_output += BasicExecute.subst(movkIop)
movnCode = 'Dest64 = ~(((uint64_t)imm1) << imm2);'
- movnIop = InstObjParams("movn", "Movn", "RegImmImmOp", movnCode, [])
+ movnIop = ArmInstObjParams("movn", "Movn", "RegImmImmOp", movnCode, [])
header_output += RegImmImmOpDeclare.subst(movnIop)
decoder_output += RegImmImmOpConstructor.subst(movnIop)
exec_output += BasicExecute.subst(movnIop)
instFlags += ["IsCall"]
- bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
- {"code": bCode, "predicate_test": predicateTest,
- "brTgtCode" : br_tgt_code}, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
+ { "code" : bCode, "predicate_test" : predicateTest,
+ "brTgtCode" : br_tgt_code }, instFlags)
header_output += BranchImmCondDeclare.subst(bIop)
decoder_output += BranchImmCondConstructor.subst(bIop) + \
BranchTarget.subst(bIop)
code = blxCode % {"link": linkStr,
"newPC": newPC,
"branch": branchStr}
- blxIop = InstObjParams(mnem, Name, base,
- {"code": code, "brTgtCode" : br_tgt_code,
- "predicate_test": predicateTest,
- "is_ras_pop" : isRasPop }, instFlags)
+ blxIop = ArmInstObjParams(mnem, Name, base,
+ { "code" : code, "brTgtCode" : br_tgt_code,
+ "predicate_test": predicateTest,
+ "is_ras_pop" : isRasPop }, instFlags)
header_output += declare.subst(blxIop)
decoder_output += constructor.subst(blxIop)
exec_output += PredOpExecute.subst(blxIop)
IWNPC = Op1;
'''
- bxjIop = InstObjParams("bxj", "BxjReg", "BranchRegCond",
- {"code": bxjcode,
- "predicate_test": predicateTest,
- "is_ras_pop": "op1 == INTREG_LR" },
- ["IsIndirectControl"])
+ bxjIop = ArmInstObjParams("bxj", "BxjReg", "BranchRegCond",
+ { "code": bxjcode,
+ "predicate_test": predicateTest,
+ "is_ras_pop": "op1 == INTREG_LR" },
+ ["IsIndirectControl"])
header_output += BranchRegCondDeclare.subst(bxjIop)
decoder_output += BranchRegCondConstructor.subst(bxjIop)
exec_output += PredOpExecute.subst(bxjIop)
code = 'NPC = (uint32_t)(PC + imm);\n'
br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));'''
predTest = "Op1 %(test)s 0" % {"test": test}
- iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
- {"code": code, "predicate_test": predTest,
- "brTgtCode" : br_tgt_code},
- ["IsDirectControl"])
+ iop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
+ { "code" : code, "predicate_test" : predTest,
+ "brTgtCode" : br_tgt_code},
+ ["IsDirectControl"])
header_output += BranchImmRegDeclare.subst(iop)
decoder_output += BranchImmRegConstructor.subst(iop) + \
BranchTarget.subst(iop)
'''
accCode = 'NPC = PC + 2 * (Mem_ub)'
mnem = "tbb"
- iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
- {'ea_code': eaCode,
- 'memacc_code': accCode,
- 'predicate_test': predicateTest},
- ["IsIndirectControl"])
+ iop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
+ { 'ea_code' : eaCode,
+ 'memacc_code' : accCode,
+ 'predicate_test' : predicateTest},
+ ["IsIndirectControl"])
header_output += BranchTableDeclare.subst(iop)
decoder_output += BranchRegRegConstructor.subst(iop)
exec_output += LoadExecute.subst(iop) + \
bCode += 'XLR = RawPC + 4;\n'
instFlags += ['IsCall']
- bIop = InstObjParams(mnem, mnem.capitalize() + "64",
- "BranchImm64", bCode, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize() + "64",
+ "BranchImm64", bCode, instFlags)
header_output += BranchImm64Declare.subst(bIop)
decoder_output += BranchImm64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += 'XLR = RawPC + 4;\n'
instFlags += ['IsCall']
- bIop = InstObjParams(mnem, mnem.capitalize() + "64",
- "BranchReg64", bCode, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize() + "64",
+ "BranchReg64", bCode, instFlags)
header_output += BranchReg64Declare.subst(bIop)
decoder_output += BranchReg64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += 'XLR = RawPC + 4;\n'
instFlags += ['IsCall']
- bIop = InstObjParams(mnem, mnem.capitalize(),
- "BranchRegReg64", bCode, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize(),
+ "BranchRegReg64", bCode, instFlags)
header_output += BranchRegReg64Declare.subst(bIop)
decoder_output += BranchRegReg64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += 'XLR = RawPC + 4;\n'
instFlags += ['IsCall']
- bIop = InstObjParams(mnem, mnem.capitalize(),
- "BranchReg64", bCode, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize(),
+ "BranchReg64", bCode, instFlags)
header_output += BranchReg64Declare.subst(bIop)
decoder_output += BranchReg64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += 'XLR = RawPC + 4;\n'
instFlags += ['IsCall']
- bIop = InstObjParams(mnem, mnem.capitalize(),
- "BranchRegReg64", bCode, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize(),
+ "BranchRegReg64", bCode, instFlags)
header_output += BranchRegReg64Declare.subst(bIop)
decoder_output += BranchRegReg64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += 'XLR = RawPC + 4;\n'
instFlags += ['IsCall']
- bIop = InstObjParams(mnem, mnem.capitalize(),
- "BranchReg64", bCode, instFlags)
+ bIop = ArmInstObjParams(mnem, mnem.capitalize(),
+ "BranchReg64", bCode, instFlags)
header_output += BranchReg64Declare.subst(bIop)
decoder_output += BranchReg64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
else
NPC = NPC;
'''
- bIop = InstObjParams("b", "BCond64", "BranchImmCond64", bCode,
- ['IsCondControl', 'IsDirectControl'])
+ bIop = ArmInstObjParams("b", "BCond64", "BranchImmCond64", bCode,
+ ['IsCondControl', 'IsDirectControl'])
header_output += BranchImmCond64Declare.subst(bIop)
decoder_output += BranchImmCond64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
'currEL(xc->tcBase()), true);\n')
instFlags = ['IsIndirectControl', 'IsUncondControl', 'IsReturn']
- bIop = InstObjParams('ret', 'Ret64', "BranchRet64", bCode, instFlags)
+ bIop = ArmInstObjParams('ret', 'Ret64', "BranchRet64", bCode, instFlags)
header_output += BranchReg64Declare.subst(bIop)
decoder_output += BranchReg64Constructor.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += (' if (fault == NoFault)\n'
' NPC = purifyTaggedAddr(XOp1, xc->tcBase(), '
'currEL(xc->tcBase()), true);\n')
- bIop = InstObjParams('retaa', 'Retaa', "BranchRetA64", bCode, instFlags)
+ bIop = ArmInstObjParams('retaa', 'Retaa', "BranchRetA64", bCode, instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
bCode += (' if (fault == NoFault)\n'
' NPC = purifyTaggedAddr(XOp1, xc->tcBase(), '
'currEL(xc->tcBase()), true);\n')
- bIop = InstObjParams('retab', 'Retab', "BranchRetA64", bCode, instFlags)
+ bIop = ArmInstObjParams('retab', 'Retab', "BranchRetA64", bCode, instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
}
'''
instFlags = ['IsSerializeAfter', 'IsNonSpeculative', 'IsSquashAfter']
- bIop = InstObjParams('eret', 'Eret64', "BranchEret64",
- bCode%{'op': ''}, instFlags)
+ bIop = ArmInstObjParams('eret', 'Eret64', "BranchEret64",
+ bCode%{'op': ''}, instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
pac_code = '''
fault = authIA(xc->tcBase(), newPc, XOp1, &newPc);
'''
- bIop = InstObjParams('eretaa', 'Eretaa', "BranchEretA64",
- bCode % {'op': pac_code} , instFlags)
+ bIop = ArmInstObjParams('eretaa', 'Eretaa', "BranchEretA64",
+ bCode % {'op': pac_code} , instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
pac_code = '''
fault = authIB(xc->tcBase(), newPc, XOp1, &newPc);
'''
- bIop = InstObjParams('eretab', 'Eretab', "BranchEretA64",
- bCode % {'op': pac_code} , instFlags)
+ bIop = ArmInstObjParams('eretab', 'Eretab', "BranchEretA64",
+ bCode % {'op': pac_code} , instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
'purifyTaggedAddr(RawPC + imm, xc->tcBase(), '
'currEL(xc->tcBase()), true) : NPC;\n')
code = code % {"test": test}
- iop = InstObjParams(mnem, mnem.capitalize() + "64",
- "BranchImmReg64", code,
- ['IsCondControl', 'IsDirectControl'])
+ iop = ArmInstObjParams(mnem, mnem.capitalize() + "64",
+ "BranchImmReg64", code,
+ ['IsCondControl', 'IsDirectControl'])
header_output += BranchImmReg64Declare.subst(iop)
decoder_output += BranchImmReg64Constructor.subst(iop)
exec_output += BasicExecute.subst(iop)
'purifyTaggedAddr(RawPC + imm2, xc->tcBase(), '
'currEL(xc->tcBase()), true) : NPC;\n')
code = code % {"test": test}
- iop = InstObjParams(mnem, mnem.capitalize() + "64",
- "BranchImmImmReg64", code,
- ['IsCondControl', 'IsDirectControl'])
+ iop = ArmInstObjParams(mnem, mnem.capitalize() + "64",
+ "BranchImmImmReg64", code,
+ ['IsCondControl', 'IsDirectControl'])
header_output += BranchImmImmReg64Declare.subst(iop)
decoder_output += BranchImmImmReg64Constructor.subst(iop)
exec_output += BasicExecute.subst(iop)
crypto_prefix = enable_check + cryptoRegRegRegPrefix
cryptocode = crypto_prefix + crypto_func + cryptoSuffix
- cryptoiop = InstObjParams(name, Name, "RegRegRegOp",
- { "code": cryptocode,
- "r_count": 4,
- "predicate_test": predicateTest,
- "op_class": opClass}, [])
+ cryptoiop = ArmInstObjParams(name, Name, "RegRegRegOp",
+ { "code": cryptocode,
+ "r_count": 4,
+ "predicate_test": predicateTest,
+ "op_class": opClass}, [])
header_output += RegRegRegOpDeclare.subst(cryptoiop)
decoder_output += RegRegRegOpConstructor.subst(cryptoiop)
exec_output += CryptoPredOpExecute.subst(cryptoiop)
crypto_prefix = enable_check + cryptoRegRegPrefix
cryptocode = crypto_prefix + crypto_func + cryptoSuffix
- cryptoiop = InstObjParams(name, Name, "RegRegOp",
- { "code": cryptocode,
- "r_count": 4,
- "predicate_test": predicateTest,
- "op_class": opClass}, [])
+ cryptoiop = ArmInstObjParams(name, Name, "RegRegOp",
+ { "code": cryptocode,
+ "r_count": 4,
+ "predicate_test": predicateTest,
+ "op_class": opClass}, [])
header_output += RegRegOpDeclare.subst(cryptoiop)
decoder_output += RegRegOpConstructor.subst(cryptoiop)
exec_output += CryptoPredOpExecute.subst(cryptoiop)
crypto_prefix = enable_check + cryptoRegRegPrefix
cryptocode = crypto_prefix + crypto_func + cryptoSuffix
- cryptoiop = InstObjParams(name, Name, "RegRegImmOp",
- { "code": cryptocode,
- "r_count": 4,
- "predicate_test": predicateTest,
- "op_class": opClass}, [])
+ cryptoiop = ArmInstObjParams(name, Name, "RegRegImmOp",
+ { "code": cryptocode,
+ "r_count": 4,
+ "predicate_test": predicateTest,
+ "op_class": opClass}, [])
header_output += RegRegImmOpDeclare.subst(cryptoiop)
decoder_output += RegRegImmOpConstructor.subst(cryptoiop)
exec_output += CryptoPredOpExecute.subst(cryptoiop)
crypto_prefix = enable_check + cryptoRegRegRegPrefix
cryptocode = crypto_prefix + crypto_func + cryptoSuffix
- cryptoiop = InstObjParams(name, Name, "RegRegRegOp",
- { "code": cryptocode,
- "r_count": 4,
- "predicate_test": predicateTest,
- "op_class": opClass}, [])
+ cryptoiop = ArmInstObjParams(name, Name, "RegRegRegOp",
+ { "code": cryptocode,
+ "r_count": 4,
+ "predicate_test": predicateTest,
+ "op_class": opClass}, [])
header_output += RegRegRegOpDeclare.subst(cryptoiop)
decoder_output += RegRegRegOpConstructor.subst(cryptoiop)
exec_output += CryptoPredOpExecute.subst(cryptoiop)
crypto_prefix = enable_check + cryptoRegRegPrefix
cryptocode = crypto_prefix + crypto_func + cryptoSuffix
- cryptoiop = InstObjParams(name, Name, "RegRegOp",
- { "code": cryptocode,
- "r_count": 4,
- "predicate_test": predicateTest,
- "op_class": opClass}, [])
+ cryptoiop = ArmInstObjParams(name, Name, "RegRegOp",
+ { "code": cryptocode,
+ "r_count": 4,
+ "predicate_test": predicateTest,
+ "op_class": opClass}, [])
header_output += RegRegOpDeclare.subst(cryptoiop)
decoder_output += RegRegOpConstructor.subst(cryptoiop)
exec_output += CryptoPredOpExecute.subst(cryptoiop)
secondOpRe.sub(immOp2, vCode))
immCode = secondOpRe.sub(immOp2, code)
- immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
+ immIop = ArmInstObjParams(mnem, mnem.capitalize() + suffix,
+ "DataImmOp",
{"code" : immCode,
"is_branch" : isBranch,
"predicate_test": pickPredicate(immCode)}, instFlags)
- immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
+ immIopCc = ArmInstObjParams(mnem + "s",
+ mnem.capitalize() + suffix + "Cc",
"DataImmOp",
{"code" : immCode + immCcCode,
"is_branch" : isBranch,
regCode = re.sub('OptShiftRmCondCodesC', 'CondCodesC', regCode)
regCcCode = re.sub('OptShiftRmCondCodesC', 'CondCodesC', regCcCode)
- regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
+ regIop = ArmInstObjParams(mnem, mnem.capitalize() + suffix,
+ "DataRegOp",
{"code" : regCode, "is_ras_pop" : isRasPop,
"is_branch" : isBranch,
"predicate_test": pickPredicate(regCode)}, instFlags)
- regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
+ regIopCc = ArmInstObjParams(mnem + "s",
+ mnem.capitalize() + suffix + "Cc",
"DataRegOp",
{"code" : regCode + regCcCode,
"predicate_test": pickPredicate(regCode + regCcCode),
secondOpRe.sub(regRegOp2, vCode))
regRegCode = secondOpRe.sub(regRegOp2, code)
- regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
+ regRegIop = ArmInstObjParams(mnem, mnem.capitalize() + suffix,
"DataRegRegOp",
{"code" : regRegCode,
"predicate_test": pickPredicate(regRegCode)})
- regRegIopCc = InstObjParams(mnem + "s",
+ regRegIopCc = ArmInstObjParams(mnem + "s",
mnem.capitalize() + suffix + "Cc",
"DataRegRegOp",
{"code" : regRegCode + regRegCcCode,
''' + code
ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
Name = mnem.capitalize() + suffix
- iop = InstObjParams(mnem, Name, base, code)
- iopCc = InstObjParams(mnem + "s", Name + "Cc", base, code + ccCode)
+ iop = ArmInstObjParams(mnem, Name, base, code)
+ iopCc = ArmInstObjParams(mnem + "s", Name + "Cc", base, code + ccCode)
def subst(iop):
global header_output, decoder_output, exec_output
global header_output, decoder_output, exec_output
classNamePrefix = mnem[0].upper() + mnem[1:]
templateBase = "DataXImm"
- iop = InstObjParams(mnem, classNamePrefix + "64",
- templateBase + "Op", code, optArgs)
+ iop = ArmInstObjParams(mnem, classNamePrefix + "64",
+ templateBase + "Op", code, optArgs)
header_output += eval(templateBase + "Declare").subst(iop)
decoder_output += eval(templateBase + "Constructor").subst(iop)
exec_output += BasicExecute.subst(iop)
templateBase = "DataX%dReg" % regOps
classNamePrefix = mnem[0].upper() + mnem[1:]
if overrideOpClass:
- iop = InstObjParams(mnem, classNamePrefix + "64",
- templateBase + "Op",
- { 'code': code, 'op_class': overrideOpClass},
- optArgs)
+ iop = ArmInstObjParams(mnem, classNamePrefix + "64",
+ templateBase + "Op",
+ { 'code': code,
+ 'op_class': overrideOpClass },
+ optArgs)
else:
- iop = InstObjParams(mnem, classNamePrefix + "64",
- templateBase + "Op", code, optArgs)
+ iop = ArmInstObjParams(mnem, classNamePrefix + "64",
+ templateBase + "Op", code, optArgs)
header_output += eval(templateBase + "Declare").subst(iop)
decoder_output += eval(templateBase + "Constructor").subst(iop)
exec_output += BasicExecute.subst(iop)
mrsCode = mrs_check_code + '''
XDest = MiscOp1_ud;
'''
- mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
- mrsCode,
- ["IsSerializeBefore"])
+ mrsIop = ArmInstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
+ mrsCode,
+ ["IsSerializeBefore"])
header_output += RegMiscRegOp64Declare.subst(mrsIop)
decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
exec_output += BasicExecute.subst(mrsIop)
msrCode = msr_check_code + '''
MiscDest_ud = XOp1;
'''
- msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
- msrCode,
- ["IsSerializeAfter", "IsNonSpeculative"])
+ msrIop = ArmInstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
+ msrCode,
+ ["IsSerializeAfter", "IsNonSpeculative"])
header_output += MiscRegRegOp64Declare.subst(msrIop)
decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
exec_output += BasicExecute.subst(msrIop)
'''
- msrDCZVAIop = InstObjParams("dc zva", "Dczva", "SysDC64",
- { "ea_code" : msrdczva_ea_code,
- "memacc_code" : ';',
- "use_uops" : 0,
- "op_wb" : ";",
- "fa_code" : ";"},
- ['IsStore']);
+ msrDCZVAIop = ArmInstObjParams("dc zva", "Dczva", "SysDC64",
+ { "ea_code" : msrdczva_ea_code,
+ "memacc_code" : ';',
+ "use_uops" : 0,
+ "op_wb" : ";",
+ "fa_code" : ";"},
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCZVAIop);
decoder_output += DCStore64Constructor.subst(msrDCZVAIop);
exec_output += DCStore64Execute.subst(msrDCZVAIop);
EA &= ~(op_size - 1);
'''
- msrDCCVAUIop = InstObjParams("dc cvau", "Dccvau", "SysDC64",
- { "ea_code" : msrdccvau_ea_code,
- "memacc_code" : ';',
- "use_uops" : 0,
- "op_wb" : ";",
- "fa_code" : cachem_fa},
- ['IsStore']);
+ msrDCCVAUIop = ArmInstObjParams("dc cvau", "Dccvau", "SysDC64",
+ { "ea_code" : msrdccvau_ea_code,
+ "memacc_code" : ';',
+ "use_uops" : 0,
+ "op_wb" : ";",
+ "fa_code" : cachem_fa},
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCCVAUIop);
decoder_output += DCStore64Constructor.subst(msrDCCVAUIop);
exec_output += DCStore64Execute.subst(msrDCCVAUIop);
EA &= ~(op_size - 1);
'''
- msrDCCVACIop = InstObjParams("dc cvac", "Dccvac", "SysDC64",
- { "ea_code" : msrdccvac_ea_code,
- "memacc_code" : ';',
- "use_uops" : 0,
- "op_wb" : ";",
- "fa_code" : cachem_fa},
- ['IsStore']);
+ msrDCCVACIop = ArmInstObjParams("dc cvac", "Dccvac", "SysDC64",
+ { "ea_code" : msrdccvac_ea_code,
+ "memacc_code" : ';',
+ "use_uops" : 0,
+ "op_wb" : ";",
+ "fa_code" : cachem_fa},
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCCVACIop);
decoder_output += DCStore64Constructor.subst(msrDCCVACIop);
exec_output += DCStore64Execute.subst(msrDCCVACIop);
EA &= ~(op_size - 1);
'''
- msrDCCIVACIop = InstObjParams("dc civac", "Dccivac", "SysDC64",
- { "ea_code" : msrdccivac_ea_code,
- "memacc_code" : ';',
- "use_uops" : 0,
- "op_wb" : ";",
- "fa_code" : cachem_fa},
- ['IsStore']);
+ msrDCCIVACIop = ArmInstObjParams("dc civac", "Dccivac", "SysDC64",
+ { "ea_code" : msrdccivac_ea_code,
+ "memacc_code" : ';',
+ "use_uops" : 0,
+ "op_wb" : ";",
+ "fa_code" : cachem_fa},
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCCIVACIop);
decoder_output += DCStore64Constructor.subst(msrDCCIVACIop);
exec_output += DCStore64Execute.subst(msrDCCIVACIop);
EA &= ~(op_size - 1);
'''
- msrDCIVACIop = InstObjParams("dc ivac", "Dcivac", "SysDC64",
- { "ea_code" : msrdcivac_ea_code,
- "memacc_code" : ';',
- "use_uops" : 0,
- "op_wb" : ";",
- "fa_code" : cachem_fa},
- ['IsStore']);
+ msrDCIVACIop = ArmInstObjParams("dc ivac", "Dcivac", "SysDC64",
+ { "ea_code" : msrdcivac_ea_code,
+ "memacc_code" : ';',
+ "use_uops" : 0,
+ "op_wb" : ";",
+ "fa_code" : cachem_fa},
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCIVACIop);
decoder_output += DCStore64Constructor.subst(msrDCIVACIop);
exec_output += DCStore64Execute.subst(msrDCIVACIop);
}
'''
- msrIop = InstObjParams("msr", inst_name, "MiscRegImmOp64",
- msrImmPermission + code,
- ["IsSerializeAfter", "IsNonSpeculative"])
+ msrIop = ArmInstObjParams("msr", inst_name, "MiscRegImmOp64",
+ msrImmPermission + code,
+ ["IsSerializeAfter", "IsNonSpeculative"])
header_output += MiscRegOp64Declare.subst(msrIop)
decoder_output += MiscRegOp64Constructor.subst(msrIop)
exec_output += BasicExecute.subst(msrIop)
def buildDataXCompInst(mnem, instType, suffix, code):
global header_output, decoder_output, exec_output
templateBase = "DataXCond%s" % instType
- iop = InstObjParams(mnem, mnem.capitalize() + suffix + "64",
- templateBase + "Op", code)
+ iop = ArmInstObjParams(mnem, mnem.capitalize() + suffix + "64",
+ templateBase + "Op", code)
header_output += eval(templateBase + "Declare").subst(iop)
decoder_output += eval(templateBase + "Constructor").subst(iop)
exec_output += BasicExecute.subst(iop)
Dest_sw = Op1_sw / Op2_sw;
}
'''
- sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
+ sdivIop = ArmInstObjParams("sdiv", "Sdiv", "RegRegRegOp",
{ "code": sdivCode,
"predicate_test": predicateTest,
"op_class": "IntDivOp"}, [])
Dest_uw = Op1_uw / Op2_uw;
}
'''
- udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
+ udivIop = ArmInstObjParams("udiv", "Udiv", "RegRegRegOp",
{ "code": udivCode,
"predicate_test": predicateTest,
"op_class": "IntDivOp"}, [])
MiscDest = Op1;
'''
- vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp",
- { "code": vmsrCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeAfter","IsNonSpeculative"])
+ vmsrIop = ArmInstObjParams("vmsr", "Vmsr", "FpRegRegImmOp",
+ { "code": vmsrCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += FpRegRegImmOpDeclare.subst(vmsrIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop);
exec_output += PredOpExecute.subst(vmsrIop);
Fpscr = Op1 & ~FpCondCodesMask;
FpCondCodes = Op1 & FpCondCodesMask;
'''
- vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp",
- { "code": vmsrFpscrCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeAfter","IsNonSpeculative",
- "IsSquashAfter"])
+ vmsrFpscrIop = ArmInstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp",
+ { "code": vmsrFpscrCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" },
+ ["IsSerializeAfter","IsNonSpeculative",
+ "IsSquashAfter"])
header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
exec_output += PredOpExecute.subst(vmsrFpscrIop);
Dest = MiscOp1;
'''
- vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp",
- { "code": vmrsCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeBefore"])
+ vmrsIop = ArmInstObjParams("vmrs", "Vmrs", "FpRegRegImmOp",
+ { "code": vmrsCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" },
+ ["IsSerializeBefore"])
header_output += FpRegRegImmOpDeclare.subst(vmrsIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop);
exec_output += PredOpExecute.subst(vmrsIop);
- vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp",
- { "code": vmrsEnabledCheckCode + \
- "Dest = Fpscr | FpCondCodes;",
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeBefore"])
+ vmrsFpscrIop = ArmInstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp",
+ { "code": vmrsEnabledCheckCode + \
+ "Dest = Fpscr | FpCondCodes;",
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" },
+ ["IsSerializeBefore"])
header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
exec_output += PredOpExecute.subst(vmrsFpscrIop);
CondCodesC = fpscr.c;
CondCodesV = fpscr.v;
'''
- vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp",
- { "code": vmrsApsrFpscrCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" })
+ vmrsApsrFpscrIop = ArmInstObjParams("vmrs", "VmrsApsrFpscr", "PredOp",
+ { "code": vmrsApsrFpscrCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" })
header_output += BasicDeclare.subst(vmrsApsrFpscrIop);
decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop);
exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
vmovImmSCode = vfpEnabledCheckCode + '''
FpDest_uw = bits(imm, 31, 0);
'''
- vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",
- { "code": vmovImmSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovImmSIop = ArmInstObjParams("vmov", "VmovImmS", "FpRegImmOp",
+ { "code": vmovImmSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegImmOpDeclare.subst(vmovImmSIop);
decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop);
exec_output += PredOpExecute.subst(vmovImmSIop);
FpDestP0_uw = bits(imm, 31, 0);
FpDestP1_uw = bits(imm, 63, 32);
'''
- vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",
- { "code": vmovImmDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovImmDIop = ArmInstObjParams("vmov", "VmovImmD", "FpRegImmOp",
+ { "code": vmovImmDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegImmOpDeclare.subst(vmovImmDIop);
decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop);
exec_output += PredOpExecute.subst(vmovImmDIop);
FpDestP2_uw = bits(imm, 31, 0);
FpDestP3_uw = bits(imm, 63, 32);
'''
- vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
- { "code": vmovImmQCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovImmQIop = ArmInstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
+ { "code": vmovImmQCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegImmOpDeclare.subst(vmovImmQIop);
decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop);
exec_output += PredOpExecute.subst(vmovImmQIop);
vmovRegSCode = vfpEnabledCheckCode + '''
FpDest_uw = FpOp1_uw;
'''
- vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",
- { "code": vmovRegSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegSIop = ArmInstObjParams("vmov", "VmovRegS", "FpRegRegOp",
+ { "code": vmovRegSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegSIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop);
exec_output += PredOpExecute.subst(vmovRegSIop);
FpDestP0_uw = FpOp1P0_uw;
FpDestP1_uw = FpOp1P1_uw;
'''
- vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",
- { "code": vmovRegDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegDIop = ArmInstObjParams("vmov", "VmovRegD", "FpRegRegOp",
+ { "code": vmovRegDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegDIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop);
exec_output += PredOpExecute.subst(vmovRegDIop);
FpDestP2_uw = FpOp1P2_uw;
FpDestP3_uw = FpOp1P3_uw;
'''
- vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
- { "code": vmovRegQCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegQIop = ArmInstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
+ { "code": vmovRegQCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegQIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop);
exec_output += PredOpExecute.subst(vmovRegQIop);
vmovCoreRegBCode = simdEnabledCheckCode + '''
FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub);
'''
- vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
- { "code": vmovCoreRegBCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovCoreRegBIop = ArmInstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
+ { "code": vmovCoreRegBCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop);
exec_output += PredOpExecute.subst(vmovCoreRegBIop);
vmovCoreRegHCode = simdEnabledCheckCode + '''
FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh);
'''
- vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
- { "code": vmovCoreRegHCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovCoreRegHIop = ArmInstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
+ { "code": vmovCoreRegHCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop);
exec_output += PredOpExecute.subst(vmovCoreRegHIop);
vmovCoreRegWCode = vfpEnabledCheckCode + '''
FpDest_uw = Op1_uw;
'''
- vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
- { "code": vmovCoreRegWCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovCoreRegWIop = ArmInstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
+ { "code": vmovCoreRegWCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop);
decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop);
exec_output += PredOpExecute.subst(vmovCoreRegWIop);
assert(imm < 4);
Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8);
'''
- vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
- { "code": vmovRegCoreUBCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegCoreUBIop = ArmInstObjParams(
+ "vmov", "VmovRegCoreUB", "FpRegRegImmOp",
+ { "code": vmovRegCoreUBCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);
exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
assert(imm < 2);
Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16);
'''
- vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
- { "code": vmovRegCoreUHCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegCoreUHIop = ArmInstObjParams(
+ "vmov", "VmovRegCoreUH", "FpRegRegImmOp",
+ { "code": vmovRegCoreUHCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);
exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
assert(imm < 4);
Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8));
'''
- vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
- { "code": vmovRegCoreSBCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegCoreSBIop = ArmInstObjParams(
+ "vmov", "VmovRegCoreSB", "FpRegRegImmOp",
+ { "code": vmovRegCoreSBCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);
exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
assert(imm < 2);
Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16));
'''
- vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
- { "code": vmovRegCoreSHCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegCoreSHIop = ArmInstObjParams(
+ "vmov", "VmovRegCoreSH", "FpRegRegImmOp",
+ { "code": vmovRegCoreSHCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);
exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
vmovRegCoreWCode = vfpEnabledCheckCode + '''
Dest = FpOp1_uw;
'''
- vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
- { "code": vmovRegCoreWCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmovRegCoreWIop = ArmInstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
+ { "code": vmovRegCoreWCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop);
exec_output += PredOpExecute.subst(vmovRegCoreWIop);
FpDestP0_uw = Op1_uw;
FpDestP1_uw = Op2_uw;
'''
- vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
- { "code": vmov2Reg2CoreCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmov2Reg2CoreIop = ArmInstObjParams(
+ "vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
+ { "code": vmov2Reg2CoreCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
Dest_uw = FpOp2P0_uw;
Op1_uw = FpOp2P1_uw;
'''
- vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
- { "code": vmov2Core2RegCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" }, [])
+ vmov2Core2RegIop = ArmInstObjParams(
+ "vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
+ { "code": vmov2Core2RegCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
exec_output += PredOpExecute.subst(vmov2Core2RegIop);
global header_output, decoder_output, exec_output
code = singleTernOp % { "op": singleOp, "palam": paramStr }
- sIop = InstObjParams(Name.lower() + "s", Name + "S", base,
+ sIop = ArmInstObjParams(Name.lower() + "s", Name + "S", base,
{ "code": code,
"predicate_test": predicateTest,
"op_class": opClass }, [])
code = doubleTernOp % { "op": doubleOp, "palam": paramStr }
- dIop = InstObjParams(Name.lower() + "d", Name + "D", base,
+ dIop = ArmInstObjParams(Name.lower() + "d", Name + "D", base,
{ "code": code,
"predicate_test": predicateTest,
"op_class": opClass }, [])
code = singleCode % { "op": singleBinOp }
code = code % { "func": singleOp }
- sIop = InstObjParams(name + "s", Name + "S", base,
+ sIop = ArmInstObjParams(name + "s", Name + "S", base,
{ "code": code,
"predicate_test": predicateTest,
"op_class": opClass }, [])
code = doubleCode % { "op": doubleBinOp }
code = code % { "func": doubleOp }
- dIop = InstObjParams(name + "d", Name + "D", base,
+ dIop = ArmInstObjParams(name + "d", Name + "D", base,
{ "code": code,
"predicate_test": predicateTest,
"op_class": opClass }, [])
FpscrExc = fpscr;
'''
)
- iop = InstObjParams(
+ iop = ArmInstObjParams(
name + size_suffix,
Name + size_suffix.upper(),
base,
code = singleCode % { "op": singleUnaryOp }
code = code % { "func": singleOp }
- sIop = InstObjParams(name + "s", Name + "S", base,
+ sIop = ArmInstObjParams(name + "s", Name + "S", base,
{ "code": code,
"predicate_test": predicateTest,
"op_class": opClass }, [])
code = doubleCode % { "op": doubleUnaryOp }
code = code % { "func": doubleOp }
- dIop = InstObjParams(name + "d", Name + "D", base,
+ dIop = ArmInstObjParams(name + "d", Name + "D", base,
{ "code": code,
"predicate_test": predicateTest,
"op_class": opClass }, [])
doubleOp = singleOp
global header_output, decoder_output, exec_output
- sIop = InstObjParams(name + "s", Name + "S", base,
+ sIop = ArmInstObjParams(name + "s", Name + "S", base,
{ "code": singleSimpleCode % { "op": singleOp },
"predicate_test": predicateTest,
"op_class": opClass }, [])
- dIop = InstObjParams(name + "d", Name + "D", base,
+ dIop = ArmInstObjParams(name + "d", Name + "D", base,
{ "code": doubleCode % { "op": doubleOp },
"predicate_test": predicateTest,
"op_class": opClass }, [])
fpscr.fz, fpscr.dn, fpscr.rMode);
FpscrExc = fpscr;
'''
- vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",
+ vmlaSIop = ArmInstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",
{ "code": vmlaSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultAccOp" }, [])
FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr;
'''
- vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
+ vmlaDIop = ArmInstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
{ "code": vmlaDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultAccOp" }, [])
fpscr.fz, fpscr.dn, fpscr.rMode);
FpscrExc = fpscr;
'''
- vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",
+ vmlsSIop = ArmInstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",
{ "code": vmlsSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultAccOp" }, [])
FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr;
'''
- vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
+ vmlsDIop = ArmInstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
{ "code": vmlsDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultAccOp" }, [])
fpscr.fz, fpscr.dn, fpscr.rMode);
FpscrExc = fpscr;
'''
- vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",
+ vnmlaSIop = ArmInstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",
{ "code": vnmlaSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultAccOp" }, [])
FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr;
'''
- vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
+ vnmlaDIop = ArmInstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
{ "code": vnmlaDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultAccOp" }, [])
fpscr.fz, fpscr.dn, fpscr.rMode);
FpscrExc = fpscr;
'''
- vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",
- { "code": vnmlsSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMultAccOp" }, [])
+ vnmlsSIop = ArmInstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",
+ { "code": vnmlsSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMultAccOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop);
decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop);
exec_output += PredOpExecute.subst(vnmlsSIop);
FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr;
'''
- vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
- { "code": vnmlsDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMultAccOp" }, [])
+ vnmlsDIop = ArmInstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
+ { "code": vnmlsDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMultAccOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop);
decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop);
exec_output += PredOpExecute.subst(vnmlsDIop);
fpscr.fz, fpscr.dn, fpscr.rMode);
FpscrExc = fpscr;
'''
- vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",
- { "code": vnmulSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMultOp" }, [])
+ vnmulSIop = ArmInstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",
+ { "code": vnmulSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMultOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vnmulSIop);
decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop);
exec_output += PredOpExecute.subst(vnmulSIop);
FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr;
'''
- vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp",
+ vnmulDIop = ArmInstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp",
{ "code": vnmulDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMultOp" }, [])
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
- { "code": vcvtUIntFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtUIntFpSIop = ArmInstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
+ { "code": vcvtUIntFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);
exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
- { "code": vcvtUIntFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtUIntFpDIop = ArmInstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
+ { "code": vcvtUIntFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);
exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
- { "code": vcvtSIntFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtSIntFpSIop = ArmInstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
+ { "code": vcvtSIntFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);
exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
- { "code": vcvtSIntFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtSIntFpDIop = ArmInstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
+ { "code": vcvtSIntFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vjcvtSFixedFpDIop = InstObjParams("vjcvt", "VjcvtSFixedFpD", "FpRegRegOp",
- { "code": vjcvtSFixedFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vjcvtSFixedFpDIop = ArmInstObjParams(
+ "vjcvt", "VjcvtSFixedFpD", "FpRegRegOp",
+ { "code": vjcvtSFixedFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vjcvtSFixedFpDIop);
decoder_output += FpRegRegOpConstructor.subst(vjcvtSFixedFpDIop);
exec_output += PredOpExecute.subst(vjcvtSFixedFpDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
- { "code": vcvtFpUIntSRCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpUIntSRIop = ArmInstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
+ { "code": vcvtFpUIntSRCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
FpDestP0_uw = result;
FpscrExc = fpscr;
'''
- vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
- { "code": vcvtFpUIntDRCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpUIntDRIop = ArmInstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
+ { "code": vcvtFpUIntDRCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
- { "code": vcvtFpSIntSRCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSIntSRIop = ArmInstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
+ { "code": vcvtFpSIntSRCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
FpDestP0_uw = result;
FpscrExc = fpscr;
'''
- vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
- { "code": vcvtFpSIntDRCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSIntDRIop = ArmInstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
+ { "code": vcvtFpSIntDRCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
full_code = vfpEnabledCheckCode + code.format(
round_mode=round_mode_suffix_to_mode[roundModeSuffix],
)
- iop = InstObjParams(
+ iop = ArmInstObjParams(
"vcvt{}".format(roundModeSuffix),
className.format(roundModeSuffix),
"FpRegRegOp",
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
+ vcvtFpSFpDIop = ArmInstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
{ "code": vcvtFpSFpDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCvtOp" }, [])
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
+ vcvtFpDFpSIop = ArmInstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
{ "code": vcvtFpDFpSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCvtOp" }, [])
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp",
- { "code": vcvtFpHTFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpHTFpSIop = ArmInstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp",
+ { "code": vcvtFpHTFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop);
exec_output += PredOpExecute.subst(vcvtFpHTFpSIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp",
- { "code": vcvtFpHBFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpHBFpSIop = ArmInstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp",
+ { "code": vcvtFpHBFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop);
exec_output += PredOpExecute.subst(vcvtFpHBFpSIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp",
- { "code": vcvtFpHTFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSFpHTIop = ArmInstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp",
+ { "code": vcvtFpHTFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop);
exec_output += PredOpExecute.subst(vcvtFpSFpHTIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp",
- { "code": vcvtFpSFpHBCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSFpHBIop = ArmInstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp",
+ { "code": vcvtFpSFpHBCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop);
decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop);
exec_output += PredOpExecute.subst(vcvtFpSFpHBIop);
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",
+ vcmpSIop = ArmInstObjParams("vcmps", "VcmpS", "FpRegRegOp",
{ "code": vcmpSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
+ vcmpDIop = ArmInstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
{ "code": vcmpDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
+ vcmpZeroSIop = ArmInstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
{ "code": vcmpZeroSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
+ vcmpZeroDIop = ArmInstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
{ "code": vcmpZeroDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
+ vcmpeSIop = ArmInstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
{ "code": vcmpeSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
+ vcmpeDIop = ArmInstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
{ "code": vcmpeDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
+ vcmpeZeroSIop = ArmInstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
{ "code": vcmpeZeroSCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpCondCodes = fpscr & FpCondCodesMask;
FpscrExc = fpscr;
'''
- vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp",
+ vcmpeZeroDIop = ArmInstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp",
{ "code": vcmpeZeroDCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatCmpOp" }, [])
FpDest = FpOp2;
} '''
- vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp",
- { "code" : vselSCode,
- "predicate_test" : predicateTest,
- "op_class" : "SimdFloatCmpOp" }, [] )
+ vselSIop = ArmInstObjParams("vsels", "VselS", "FpRegRegRegCondOp",
+ { "code" : vselSCode,
+ "predicate_test" : predicateTest,
+ "op_class" : "SimdFloatCmpOp" }, [] )
header_output += FpRegRegRegCondOpDeclare.subst(vselSIop);
decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop);
exec_output += PredOpExecute.subst(vselSIop);
FpDestP1_uw = FpOp2P1_uw;
} '''
- vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp",
- { "code" : vselDCode,
- "predicate_test" : predicateTest,
- "op_class" : "SimdFloatCmpOp" }, [] )
+ vselDIop = ArmInstObjParams("vseld", "VselD", "FpRegRegRegCondOp",
+ { "code" : vselDCode,
+ "predicate_test" : predicateTest,
+ "op_class" : "SimdFloatCmpOp" }, [] )
header_output += FpRegRegRegCondOpDeclare.subst(vselDIop);
decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop);
exec_output += PredOpExecute.subst(vselDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
- { "code": vcvtFpSFixedSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSFixedSIop = ArmInstObjParams(
+ "vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
+ { "code": vcvtFpSFixedSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
FpDestP1_uw = mid >> 32;
FpscrExc = fpscr;
'''
- vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
- { "code": vcvtFpSFixedDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSFixedDIop = ArmInstObjParams(
+ "vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
+ { "code": vcvtFpSFixedDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
- { "code": vcvtFpUFixedSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpUFixedSIop = ArmInstObjParams(
+ "vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
+ { "code": vcvtFpUFixedSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
FpDestP1_uw = mid >> 32;
FpscrExc = fpscr;
'''
- vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
- { "code": vcvtFpUFixedDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpUFixedDIop = ArmInstObjParams(
+ "vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
+ { "code": vcvtFpUFixedDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
- { "code": vcvtSFixedFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtSFixedFpSIop = ArmInstObjParams(
+ "vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
+ { "code": vcvtSFixedFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
- { "code": vcvtSFixedFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtSFixedFpDIop = ArmInstObjParams(
+ "vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
+ { "code": vcvtSFixedFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
- { "code": vcvtUFixedFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtUFixedFpSIop = ArmInstObjParams(
+ "vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
+ { "code": vcvtUFixedFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
- { "code": vcvtUFixedFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtUFixedFpDIop = ArmInstObjParams(
+ "vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
+ { "code": vcvtUFixedFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
- "FpRegRegImmOp",
- { "code": vcvtFpSHFixedSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSHFixedSIop = ArmInstObjParams("vcvt", "VcvtFpSHFixedS",
+ "FpRegRegImmOp",
+ { "code": vcvtFpSHFixedSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
FpDestP1_uw = result >> 32;
FpscrExc = fpscr;
'''
- vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
- "FpRegRegImmOp",
- { "code": vcvtFpSHFixedDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpSHFixedDIop = ArmInstObjParams("vcvt", "VcvtFpSHFixedD",
+ "FpRegRegImmOp",
+ { "code": vcvtFpSHFixedDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
- "FpRegRegImmOp",
- { "code": vcvtFpUHFixedSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpUHFixedSIop = ArmInstObjParams("vcvt", "VcvtFpUHFixedS",
+ "FpRegRegImmOp",
+ { "code": vcvtFpUHFixedSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
FpDestP1_uw = mid >> 32;
FpscrExc = fpscr;
'''
- vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
- "FpRegRegImmOp",
- { "code": vcvtFpUHFixedDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtFpUHFixedDIop = ArmInstObjParams("vcvt", "VcvtFpUHFixedD",
+ "FpRegRegImmOp",
+ { "code": vcvtFpUHFixedDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
- "FpRegRegImmOp",
- { "code": vcvtSHFixedFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtSHFixedFpSIop = ArmInstObjParams("vcvt", "VcvtSHFixedFpS",
+ "FpRegRegImmOp",
+ { "code": vcvtSHFixedFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
- "FpRegRegImmOp",
- { "code": vcvtSHFixedFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtSHFixedFpDIop = ArmInstObjParams("vcvt", "VcvtSHFixedFpD",
+ "FpRegRegImmOp",
+ { "code": vcvtSHFixedFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
- vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
- "FpRegRegImmOp",
- { "code": vcvtUHFixedFpSCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtUHFixedFpSIop = ArmInstObjParams("vcvt", "VcvtUHFixedFpS",
+ "FpRegRegImmOp",
+ { "code": vcvtUHFixedFpSCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr;
'''
- vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
- "FpRegRegImmOp",
- { "code": vcvtUHFixedFpDCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatCvtOp" }, [])
+ vcvtUHFixedFpDIop = ArmInstObjParams("vcvt", "VcvtUHFixedFpD",
+ "FpRegRegImmOp",
+ { "code": vcvtUHFixedFpDCode,
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
'''
- fmovImmSIop = InstObjParams("fmov", "FmovImmS", "FpRegImmOp",
- { "code": fmovImmSCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovImmSIop = ArmInstObjParams("fmov", "FmovImmS", "FpRegImmOp",
+ { "code": fmovImmSCode,
+ "op_class": "FloatMiscOp" }, [])
fmovImmSIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += FpRegImmOpDeclare.subst(fmovImmSIop);
decoder_output += FpRegImmOpConstructor.subst(fmovImmSIop);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
'''
- fmovImmDIop = InstObjParams("fmov", "FmovImmD", "FpRegImmOp",
- { "code": fmovImmDCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovImmDIop = ArmInstObjParams("fmov", "FmovImmD", "FpRegImmOp",
+ { "code": fmovImmDCode,
+ "op_class": "FloatMiscOp" }, [])
fmovImmDIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += FpRegImmOpDeclare.subst(fmovImmDIop);
decoder_output += AA64FpRegImmOpConstructor.subst(fmovImmDIop);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
'''
- fmovRegSIop = InstObjParams("fmov", "FmovRegS", "FpRegRegOp",
- { "code": fmovRegSCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovRegSIop = ArmInstObjParams("fmov", "FmovRegS", "FpRegRegOp",
+ { "code": fmovRegSCode,
+ "op_class": "FloatMiscOp" }, [])
fmovRegSIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fmovRegSIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegSIop);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
'''
- fmovRegDIop = InstObjParams("fmov", "FmovRegD", "FpRegRegOp",
- { "code": fmovRegDCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovRegDIop = ArmInstObjParams("fmov", "FmovRegD", "FpRegRegOp",
+ { "code": fmovRegDCode,
+ "op_class": "FloatMiscOp" }, [])
fmovRegDIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fmovRegDIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegDIop);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
'''
- fmovCoreRegWIop = InstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp",
- { "code": fmovCoreRegWCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovCoreRegWIop = ArmInstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp",
+ { "code": fmovCoreRegWCode,
+ "op_class": "FloatMiscOp" }, [])
fmovCoreRegWIop.snippets["code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fmovCoreRegWIop);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
'''
- fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp",
- { "code": fmovCoreRegXCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovCoreRegXIop = ArmInstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp",
+ { "code": fmovCoreRegXCode,
+ "op_class": "FloatMiscOp" }, [])
fmovCoreRegXIop.snippets["code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop);
AA64FpDestP1_uw = AA64FpDestP1_uw;
AA64FpDestP2_uw = XOp1_ud;
AA64FpDestP3_uw = XOp1_ud >> 32;'''
- fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
- { "code": fmovUCoreRegXCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovUCoreRegXIop = ArmInstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
+ { "code": fmovUCoreRegXCode,
+ "op_class": "FloatMiscOp" }, [])
fmovUCoreRegXIop.snippets["code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop);
fmovRegCoreWCode = vfp64EnabledCheckCode + '''
WDest = AA64FpOp1P0_uw;
'''
- fmovRegCoreWIop = InstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp",
- { "code": fmovRegCoreWCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovRegCoreWIop = ArmInstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp",
+ { "code": fmovRegCoreWCode,
+ "op_class": "FloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(fmovRegCoreWIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreWIop);
exec_output += BasicExecute.subst(fmovRegCoreWIop);
fmovRegCoreXCode = vfp64EnabledCheckCode + '''
XDest = ( ((uint64_t) AA64FpOp1P1_uw) << 32) | AA64FpOp1P0_uw;
'''
- fmovRegCoreXIop = InstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp",
- { "code": fmovRegCoreXCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovRegCoreXIop = ArmInstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp",
+ { "code": fmovRegCoreXCode,
+ "op_class": "FloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(fmovRegCoreXIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreXIop);
exec_output += BasicExecute.subst(fmovRegCoreXIop);
fmovURegCoreXCode = vfp64EnabledCheckCode + '''
XDest = ( ((uint64_t) AA64FpOp1P3_uw) << 32) | AA64FpOp1P2_uw;
'''
- fmovURegCoreXIop = InstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp",
- { "code": fmovURegCoreXCode,
- "op_class": "FloatMiscOp" }, [])
+ fmovURegCoreXIop = ArmInstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp",
+ { "code": fmovURegCoreXCode,
+ "op_class": "FloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(fmovURegCoreXIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fmovURegCoreXIop);
exec_output += BasicExecute.subst(fmovURegCoreXIop);
FpscrExc = fpscr;
'''
- iop = InstObjParams(name.lower(), name + suffix,
- "FpRegRegRegRegOp",
- { "code": code, "op_class": opClass }, [])
+ iop = ArmInstObjParams(name.lower(), name + suffix,
+ "FpRegRegRegRegOp",
+ { "code": code, "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += AA64FpRegRegRegRegOpDeclare.subst(iop)
global header_output, decoder_output, exec_output
code = halfIntConvCode2 % { "op": halfOp }
- hIop = InstObjParams(name, Name + "H", base,
+ hIop = ArmInstObjParams(name, Name + "H", base,
{ "code": code,
"op_class": opClass }, [])
hIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
code = singleIntConvCode2 % { "op": singleOp }
- sIop = InstObjParams(name, Name + "S", base,
+ sIop = ArmInstObjParams(name, Name + "S", base,
{ "code": code,
"op_class": opClass }, [])
sIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
code = doubleIntConvCode2 % { "op": doubleOp }
- dIop = InstObjParams(name, Name + "D", base,
+ dIop = ArmInstObjParams(name, Name + "D", base,
{ "code": code,
"op_class": opClass }, [])
dIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
global header_output, decoder_output, exec_output
code = halfIntConvCode % { "op": halfOp }
- hIop = InstObjParams(name, Name + "H", base,
+ hIop = ArmInstObjParams(name, Name + "H", base,
{ "code": code,
"op_class": opClass }, [])
hIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
code = singleIntConvCode % { "op": singleOp }
- sIop = InstObjParams(name, Name + "S", base,
+ sIop = ArmInstObjParams(name, Name + "S", base,
{ "code": code,
"op_class": opClass }, [])
sIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
code = doubleIntConvCode % { "op": doubleOp }
- dIop = InstObjParams(name, Name + "D", base,
+ dIop = ArmInstObjParams(name, Name + "D", base,
{ "code": code,
"op_class": opClass }, [])
dIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
for code, op, suffix in [[hCode, halfOp, "H"],
[sCode, singleOp, "S"],
[dCode, doubleOp, "D"]]:
- iop = InstObjParams(name, Name + suffix, base,
+ iop = ArmInstObjParams(name, Name + suffix, base,
{ "code": code % { "op": op },
"op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
instName = "Fcvt%s%sIntFp%s" %(regL, us, "D" if isDouble else "S")
mnem = "%scvtf" %(us.lower())
- fcvtIntFpDIop = InstObjParams(mnem, instName, "FpRegRegOp",
- { "code": fcvtIntFpDCode,
- "op_class": "FloatCvtOp" }, [])
+ fcvtIntFpDIop = ArmInstObjParams(mnem, instName, "FpRegRegOp",
+ { "code": fcvtIntFpDCode,
+ "op_class": "FloatCvtOp" },
+ [])
fcvtIntFpDIop.snippets["code"] += \
zeroSveVecRegUpperPartCode % "AA64FpDest"
"X" if isXReg else "W",
"D" if isDouble else "S", rmode)
mnem = "fcvt%s%s" %(rmode, "s" if isSigned else "u")
- fcvtFpIntIop = InstObjParams(mnem, instName, "FpRegRegOp",
- { "code": fcvtFpIntCode,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFpIntIop = ArmInstObjParams(mnem, instName, "FpRegRegOp",
+ { "code": fcvtFpIntCode,
+ "op_class": "FloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(fcvtFpIntIop);
decoder_output += FpRegRegOpConstructor.subst(fcvtFpIntIop);
exec_output += BasicExecute.subst(fcvtFpIntIop);
AA64FpDestP3_uw = 0;
FpscrExc = fpscr;
'''
- fcvtFpSFpDIop = InstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp",
+ fcvtFpSFpDIop = ArmInstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp",
{ "code": fcvtFpSFpDCode,
"op_class": "FloatCvtOp" }, [])
fcvtFpSFpDIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
AA64FpDestP3_uw = 0;
FpscrExc = fpscr;
'''
- fcvtFpDFpSIop = InstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp",
- {"code": fcvtFpDFpSCode,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFpDFpSIop = ArmInstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp",
+ {"code": fcvtFpDFpSCode,
+ "op_class": "FloatCvtOp" }, [])
fcvtFpDFpSIop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fcvtFpDFpSIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpDFpSIop);
'''
instName = "FcvtFpHFp%s" %("D" if isDouble else "S")
- fcvtFpHFpIop = InstObjParams("fcvt", instName, "FpRegRegOp",
- { "code": code,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFpHFpIop = ArmInstObjParams("fcvt", instName, "FpRegRegOp",
+ { "code": code,
+ "op_class": "FloatCvtOp" }, [])
fcvtFpHFpIop.snippets["code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fcvtFpHFpIop);
"64" if isDouble else "32")
instName = "FcvtFp%sFpH" %("D" if isDouble else "S")
- fcvtFpFpHIop = InstObjParams("fcvt", instName, "FpRegRegOp",
- { "code": code,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFpFpHIop = ArmInstObjParams("fcvt", instName, "FpRegRegOp",
+ { "code": code,
+ "op_class": "FloatCvtOp" }, [])
fcvtFpFpHIop.snippets["code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
header_output += FpRegRegOpDeclare.subst(fcvtFpFpHIop);
typeName = "Imm" if isImm else "Reg"
instName = "FCmp%s%s%s" %("" if isQuiet else "E", typeName,
"D" if isDouble else "S")
- fcmpIop = InstObjParams("fcmp%s" %("" if isQuiet else "e"), instName,
- "FpReg%sOp" %(typeName),
- {"code": fcmpCode,
- "op_class": "FloatCmpOp"}, [])
+ fcmpIop = ArmInstObjParams("fcmp%s" % ("" if isQuiet else "e"),
+ instName, "FpReg%sOp" % typeName,
+ { "code": fcmpCode,
+ "op_class": "FloatCmpOp"}, [])
- declareTemp = eval("FpReg%sOpDeclare" %(typeName));
+ declareTemp = eval("FpReg%sOpDeclare" %(typeName));
constructorTemp = eval("AA64FpReg%sOpConstructor" %(typeName));
header_output += declareTemp.subst(fcmpIop);
decoder_output += constructorTemp.subst(fcmpIop);
instName = "FCCmp%sReg%s" %("" if isQuiet else "E",
"D" if isDouble else "S")
- fccmpIop = InstObjParams("fccmp%s" %("" if isQuiet else "e"),
- instName, "FpCondCompRegOp",
- {"code": fccmpCode,
- "op_class": "FloatCmpOp"}, [])
+ fccmpIop = ArmInstObjParams("fccmp%s" % ("" if isQuiet else "e"),
+ instName, "FpCondCompRegOp",
+ { "code" : fccmpCode,
+ "op_class" : "FloatCmpOp"}, [])
header_output += DataXCondCompRegDeclare.subst(fccmpIop);
decoder_output += DataXCondCompRegConstructor.subst(fccmpIop);
exec_output += BasicExecute.subst(fccmpIop);
"D" if isDouble else "S",
"X" if isXReg else "W")
mnem = "fcvtz%s" %("s" if isSigned else "u")
- fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegImmOp",
- { "code": fcvtFpFixedCode,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFpFixedIop = ArmInstObjParams(mnem, instName, "FpRegRegImmOp",
+ { "code": fcvtFpFixedCode,
+ "op_class": "FloatCvtOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(fcvtFpFixedIop);
decoder_output += AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop);
exec_output += BasicExecute.subst(fcvtFpFixedIop);
instName = "FJcvtFpSFixedDW"
mnem = "fjcvtzs"
- fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegOp",
- { "code": fcvtFpFixedCode,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFpFixedIop = ArmInstObjParams(mnem, instName, "FpRegRegOp",
+ { "code": fcvtFpFixedCode,
+ "op_class": "FloatCvtOp" }, [])
header_output += FpRegRegOpDeclare.subst(fcvtFpFixedIop);
decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFixedIop);
exec_output += BasicExecute.subst(fcvtFpFixedIop);
"D" if isDouble else "S",
srcRegType)
mnem = "%scvtf" %("s" if isSigned else "u")
- fcvtFixedFpIop = InstObjParams(mnem, instName, "FpRegRegImmOp",
- { "code": fcvtFixedFpCode,
- "op_class": "FloatCvtOp" }, [])
+ fcvtFixedFpIop = ArmInstObjParams(mnem, instName, "FpRegRegImmOp",
+ { "code": fcvtFixedFpCode,
+ "op_class": "FloatCvtOp" }, [])
fcvtFixedFpIop.snippets["code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
header_output += FpRegRegImmOpDeclare.subst(fcvtFixedFpIop);
AA64FpDestP3_uw = 0;
'''
- iop = InstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"),
- "FpCondSelOp", { "code": code,
- "op_class": "FloatCvtOp" })
+ iop = ArmInstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"),
+ "FpCondSelOp", { "code": code,
+ "op_class": "FloatCvtOp" })
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += DataXCondSelDeclare.subst(iop)
decoder_output += DataXCondSelConstructor.subst(iop)
if (!recognized)
fault = std::make_shared<UndefinedInstruction>(machInst, true);
'''
- gem5OpIop = InstObjParams("gem5op", "Gem5Op64", "PredOp",
- { "code": gem5OpCode + 'X0 = ret;',
- "predicate_test": predicateTest },
- [ "IsNonSpeculative", "IsUnverifiable" ]);
+ gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op64", "PredOp",
+ { "code": gem5OpCode + 'X0 = ret;',
+ "predicate_test": predicateTest },
+ [ "IsNonSpeculative", "IsUnverifiable" ]);
header_output += BasicDeclare.subst(gem5OpIop)
decoder_output += BasicConstructor.subst(gem5OpIop)
exec_output += PredOpExecute.subst(gem5OpIop)
- gem5OpIop = InstObjParams("gem5op", "Gem5Op", "PredOp",
- { "code": gem5OpCode + \
- 'R0 = bits(ret, 31, 0);\n' + \
- 'R1 = bits(ret, 63, 32);',
- "predicate_test": predicateTest },
- [ "IsNonSpeculative", "IsUnverifiable" ]);
+ gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op", "PredOp",
+ { "code": gem5OpCode + \
+ 'R0 = bits(ret, 31, 0);\n' + \
+ 'R1 = bits(ret, 63, 32);',
+ "predicate_test": predicateTest },
+ [ "IsNonSpeculative", "IsUnverifiable" ]);
header_output += BasicDeclare.subst(gem5OpIop)
decoder_output += BasicConstructor.subst(gem5OpIop)
exec_output += PredOpExecute.subst(gem5OpIop)
let {{
microLdrUopCode = "IWRa = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
- microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
- 'MicroMemOp',
- {'memacc_code': microLdrUopCode,
- 'ea_code': 'EA = URb + (up ? imm : -imm);',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microLdrUopIop = ArmInstObjParams('ldr_uop', 'MicroLdrUop', 'MicroMemOp',
+ { 'memacc_code' : microLdrUopCode,
+ 'ea_code' : 'EA = URb + (up ? imm : -imm);',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
microLdr2UopCode = '''
uint64_t data = Mem_ud;
IWDest2 = cSwap((uint32_t) (data >> 32),
((CPSR)Cpsr).e);
'''
- microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop',
- 'MicroMemPairOp',
- {'memacc_code': microLdr2UopCode,
- 'ea_code': 'EA = URb + (up ? imm : -imm);',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microLdr2UopIop = ArmInstObjParams('ldr2_uop', 'MicroLdr2Uop',
+ 'MicroMemPairOp',
+ { 'memacc_code' : microLdr2UopCode,
+ 'ea_code' : 'EA = URb + (up ? imm : -imm);',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
- microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
- 'MicroMemOp',
- {'memacc_code': microLdrFpUopCode,
- 'ea_code': vfpEnabledCheckCode +
- 'EA = URb + (up ? imm : -imm);',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microLdrFpUopIop = ArmInstObjParams('ldrfp_uop', 'MicroLdrFpUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microLdrFpUopCode,
+ 'ea_code' : vfpEnabledCheckCode +
+ 'EA = URb + (up ? imm : -imm);',
+ 'predicate_test': predicateTest },
+ ['IsMicroop'])
microLdrDBFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
- microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
- 'MicroMemOp',
- {'memacc_code': microLdrFpUopCode,
- 'ea_code': vfpEnabledCheckCode + '''
- EA = URb + (up ? imm : -imm) +
- (((CPSR)Cpsr).e ? 4 : 0);
- ''',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microLdrDBFpUopIop = ArmInstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microLdrFpUopCode,
+ 'ea_code' : vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0);
+ ''',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
microLdrDTFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
- microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
- 'MicroMemOp',
- {'memacc_code': microLdrFpUopCode,
- 'ea_code': vfpEnabledCheckCode + '''
- EA = URb + (up ? imm : -imm) -
- (((CPSR)Cpsr).e ? 4 : 0);
- ''',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microLdrDTFpUopIop = ArmInstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microLdrFpUopCode,
+ 'ea_code' : vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0);
+ ''',
+ 'predicate_test': predicateTest },
+ ['IsMicroop'])
microRetUopCode = '''
CPSR old_cpsr = Cpsr;
SevMailbox = 1;
'''
- microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
- 'MicroMemOp',
- {'memacc_code':
- microRetUopCode % 'Mem_uw',
- 'ea_code':
- 'EA = URb + (up ? imm : -imm);',
- 'predicate_test': condPredicateTest},
- ['IsMicroop','IsNonSpeculative',
- 'IsSerializeAfter', 'IsSquashAfter'])
+ microLdrRetUopIop = ArmInstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microRetUopCode % 'Mem_uw',
+ 'ea_code' : 'EA = URb + (up ? imm : -imm);',
+ 'predicate_test' : condPredicateTest },
+ ['IsMicroop','IsNonSpeculative',
+ 'IsSerializeAfter', 'IsSquashAfter'])
microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
- microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
- 'MicroMemOp',
- {'memacc_code': microStrUopCode,
- 'postacc_code': "",
- 'ea_code': 'EA = URb + (up ? imm : -imm);',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microStrUopIop = ArmInstObjParams('str_uop', 'MicroStrUop', 'MicroMemOp',
+ { 'memacc_code' : microStrUopCode,
+ 'postacc_code' : "",
+ 'ea_code' : 'EA = URb + (up ? imm : -imm);',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
microStrFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
- microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
- 'MicroMemOp',
- {'memacc_code': microStrFpUopCode,
- 'postacc_code': "",
- 'ea_code': vfpEnabledCheckCode +
- 'EA = URb + (up ? imm : -imm);',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microStrFpUopIop = ArmInstObjParams('strfp_uop', 'MicroStrFpUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microStrFpUopCode,
+ 'postacc_code' : "",
+ 'ea_code' : vfpEnabledCheckCode +
+ 'EA = URb + (up ? imm : -imm);',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
microStrDBFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
- microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
- 'MicroMemOp',
- {'memacc_code': microStrFpUopCode,
- 'postacc_code': "",
- 'ea_code': vfpEnabledCheckCode + '''
- EA = URb + (up ? imm : -imm) +
- (((CPSR)Cpsr).e ? 4 : 0);
- ''',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microStrDBFpUopIop = ArmInstObjParams('strfp_uop', 'MicroStrDBFpUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microStrFpUopCode,
+ 'postacc_code' : "",
+ 'ea_code': vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0);
+ ''',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
microStrDTFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
- microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
- 'MicroMemOp',
- {'memacc_code': microStrFpUopCode,
- 'postacc_code': "",
- 'ea_code': vfpEnabledCheckCode + '''
- EA = URb + (up ? imm : -imm) -
- (((CPSR)Cpsr).e ? 4 : 0);
- ''',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microStrDTFpUopIop = ArmInstObjParams('strfp_uop', 'MicroStrDTFpUop',
+ 'MicroMemOp',
+ { 'memacc_code' : microStrFpUopCode,
+ 'postacc_code' : "",
+ 'ea_code' : vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0);
+ ''',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
header_output = decoder_output = exec_output = ''
loadMemAccCode = convCode + regSetCode
storeMemAccCode = regGetCode + convCode
- loadIop = InstObjParams('ldrneon%(size)d_uop' % subst,
- 'MicroLdrNeon%(size)dUop' % subst,
- 'MicroNeonMemOp',
- { 'mem_decl' : memDecl,
- 'size' : size,
- 'memacc_code' : loadMemAccCode,
- 'ea_code' : simdEnabledCheckCode + eaCode,
- 'predicate_test' : predicateTest },
- [ 'IsMicroop', 'IsLoad' ])
- storeIop = InstObjParams('strneon%(size)d_uop' % subst,
- 'MicroStrNeon%(size)dUop' % subst,
- 'MicroNeonMemOp',
- { 'mem_decl' : memDecl,
- 'size' : size,
- 'memacc_code' : storeMemAccCode,
- 'ea_code' : simdEnabledCheckCode + eaCode,
- 'predicate_test' : predicateTest },
- [ 'IsMicroop', 'IsStore' ])
+ loadIop = ArmInstObjParams('ldrneon%(size)d_uop' % subst,
+ 'MicroLdrNeon%(size)dUop' % subst, 'MicroNeonMemOp',
+ { 'mem_decl' : memDecl,
+ 'size' : size,
+ 'memacc_code' : loadMemAccCode,
+ 'ea_code' : simdEnabledCheckCode + eaCode,
+ 'predicate_test' : predicateTest },
+ [ 'IsMicroop', 'IsLoad' ])
+ storeIop = ArmInstObjParams('strneon%(size)d_uop' % subst,
+ 'MicroStrNeon%(size)dUop' % subst, 'MicroNeonMemOp',
+ { 'mem_decl' : memDecl,
+ 'size' : size,
+ 'memacc_code' : storeMemAccCode,
+ 'ea_code' : simdEnabledCheckCode + eaCode,
+ 'predicate_test' : predicateTest },
+ [ 'IsMicroop', 'IsStore' ])
exec_output += NeonLoadExecute.subst(loadIop) + \
NeonLoadInitiateAcc.subst(loadIop) + \
"loadConv" : loadConv,
"unloadConv" : unloadConv }
microDeintNeonIop = \
- InstObjParams('deintneon%duop' % (dRegs * 2),
- 'MicroDeintNeon%dUop' % (dRegs * 2),
- 'MicroNeonMixOp',
- { 'predicate_test': predicateTest,
- 'code' : microDeintNeonCode },
- ['IsMicroop'])
+ ArmInstObjParams('deintneon%duop' % (dRegs * 2),
+ 'MicroDeintNeon%dUop' % (dRegs * 2),
+ 'MicroNeonMixOp',
+ { 'predicate_test': predicateTest,
+ 'code' : microDeintNeonCode },
+ ['IsMicroop'])
header_output += MicroNeonMixDeclare.subst(microDeintNeonIop)
exec_output += MicroNeonMixExecute.subst(microDeintNeonIop)
"loadConv" : loadConv,
"unloadConv" : unloadConv }
microInterNeonIop = \
- InstObjParams('interneon%duop' % (dRegs * 2),
- 'MicroInterNeon%dUop' % (dRegs * 2),
- 'MicroNeonMixOp',
- { 'predicate_test': predicateTest,
- 'code' : microInterNeonCode },
- ['IsMicroop'])
+ ArmInstObjParams('interneon%duop' % (dRegs * 2),
+ 'MicroInterNeon%dUop' % (dRegs * 2),
+ 'MicroNeonMixOp',
+ { 'predicate_test': predicateTest,
+ 'code' : microInterNeonCode },
+ ['IsMicroop'])
header_output += MicroNeonMixDeclare.subst(microInterNeonIop)
exec_output += MicroNeonMixExecute.subst(microInterNeonIop)
}};
''' % { "sRegs" : sRegs, "dRegs" : dRegs,
"loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
- microUnpackNeonIop = \
- InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2),
- 'MicroUnpackNeon%dto%dUop' %
- (sRegs * 2, dRegs * 2),
- 'MicroNeonMixLaneOp',
- { 'predicate_test': predicateTest,
- 'code' : microUnpackNeonCode },
- ['IsMicroop'])
+ microUnpackNeonIop = ArmInstObjParams(
+ 'unpackneon%dto%duop' % (sRegs * 2, dRegs * 2),
+ 'MicroUnpackNeon%dto%dUop' % (sRegs * 2, dRegs * 2),
+ 'MicroNeonMixLaneOp',
+ { 'predicate_test' : predicateTest,
+ 'code' : microUnpackNeonCode },
+ ['IsMicroop'])
header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop)
exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop)
''' % { "sRegs" : sRegs, "dRegs" : dRegs,
"loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
- microUnpackAllNeonIop = \
- InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2),
- 'MicroUnpackAllNeon%dto%dUop' %
- (sRegs * 2, dRegs * 2),
- 'MicroNeonMixOp',
- { 'predicate_test': predicateTest,
- 'code' : microUnpackAllNeonCode },
- ['IsMicroop'])
+ microUnpackAllNeonIop = ArmInstObjParams(
+ 'unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2),
+ 'MicroUnpackAllNeon%dto%dUop' % (sRegs * 2, dRegs * 2),
+ 'MicroNeonMixOp',
+ { 'predicate_test' : predicateTest,
+ 'code' : microUnpackAllNeonCode },
+ ['IsMicroop'])
header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop)
exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop)
''' % { "sRegs" : sRegs, "dRegs" : dRegs,
"loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
- microPackNeonIop = \
- InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2),
- 'MicroPackNeon%dto%dUop' %
- (sRegs * 2, dRegs * 2),
- 'MicroNeonMixLaneOp',
- { 'predicate_test': predicateTest,
- 'code' : microPackNeonCode },
- ['IsMicroop'])
+ microPackNeonIop = ArmInstObjParams(
+ 'packneon%dto%duop' % (sRegs * 2, dRegs * 2),
+ 'MicroPackNeon%dto%dUop' % (sRegs * 2, dRegs * 2),
+ 'MicroNeonMixLaneOp',
+ { 'predicate_test': predicateTest,
+ 'code' : microPackNeonCode },
+ ['IsMicroop'])
header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop)
exec_output += MicroNeonMixExecute.subst(microPackNeonIop)
}};
//
let {{
- microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
- 'MicroIntImmOp',
- {'code': 'URa = URb + imm;',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microAddiUopIop = ArmInstObjParams('addi_uop', 'MicroAddiUop',
+ 'MicroIntImmOp',
+ {'code': 'URa = URb + imm;',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
microAddUopCode = '''
URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
'''
- microAddXiUopIop = InstObjParams('addxi_uop', 'MicroAddXiUop',
- 'MicroIntImmXOp',
- 'XURa = XURb + imm;',
- ['IsMicroop'])
+ microAddXiUopIop = ArmInstObjParams('addxi_uop', 'MicroAddXiUop',
+ 'MicroIntImmXOp',
+ 'XURa = XURb + imm;',
+ ['IsMicroop'])
- microAddXiSpAlignUopIop = InstObjParams('addxi_uop', 'MicroAddXiSpAlignUop',
- 'MicroIntImmXOp', '''
+ microAddXiSpAlignUopIop = ArmInstObjParams('addxi_uop',
+ 'MicroAddXiSpAlignUop', 'MicroIntImmXOp', '''
if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) &&
SPAlignmentCheckEnabled(xc->tcBase())) {
return std::make_shared<SPAlignmentFault>();
XURa = XURb + imm;
''', ['IsMicroop'])
- microAddXERegUopIop = InstObjParams('addxr_uop', 'MicroAddXERegUop',
- 'MicroIntRegXOp',
- 'XURa = XURb + ' + \
- 'extendReg64(XURc, type, shiftAmt, 64);',
- ['IsMicroop'])
+ microAddXERegUopIop = ArmInstObjParams('addxr_uop',
+ 'MicroAddXERegUop', 'MicroIntRegXOp',
+ 'XURa = XURb + extendReg64(XURc, type, shiftAmt, 64);',
+ ['IsMicroop'])
- microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
- 'MicroIntRegOp',
- {'code': microAddUopCode,
- 'predicate_test': pickPredicate(microAddUopCode)},
- ['IsMicroop'])
+ microAddUopIop = ArmInstObjParams('add_uop', 'MicroAddUop',
+ 'MicroIntRegOp',
+ { 'code' : microAddUopCode,
+ 'predicate_test': pickPredicate(microAddUopCode)},
+ ['IsMicroop'])
- microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
- 'MicroIntImmOp',
- {'code': 'URa = URb - imm;',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
+ microSubiUopIop = ArmInstObjParams('subi_uop', 'MicroSubiUop',
+ 'MicroIntImmOp',
+ { 'code' : 'URa = URb - imm;',
+ 'predicate_test' : predicateTest},
+ ['IsMicroop'])
- microSubXiUopIop = InstObjParams('subxi_uop', 'MicroSubXiUop',
- 'MicroIntImmXOp',
- 'XURa = XURb - imm;',
- ['IsMicroop'])
+ microSubXiUopIop = ArmInstObjParams('subxi_uop', 'MicroSubXiUop',
+ 'MicroIntImmXOp', 'XURa = XURb - imm;', ['IsMicroop'])
microSubUopCode = '''
URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
'''
- microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
- 'MicroIntRegOp',
- {'code': microSubUopCode,
- 'predicate_test': pickPredicate(microSubUopCode)},
- ['IsMicroop'])
-
- microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
- 'MicroIntMov',
- {'code': 'IWRa = URb;',
- 'predicate_test': predicateTest},
- ['IsMicroop'])
-
- microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
- 'MicroIntMov',
- {'code': microRetUopCode % 'URb',
- 'predicate_test': predicateTest},
- ['IsMicroop', 'IsNonSpeculative',
- 'IsSerializeAfter', 'IsSquashAfter'])
+ microSubUopIop = ArmInstObjParams('sub_uop', 'MicroSubUop',
+ 'MicroIntRegOp',
+ { 'code' : microSubUopCode,
+ 'predicate_test' : pickPredicate(microSubUopCode) },
+ ['IsMicroop'])
+
+ microUopRegMovIop = ArmInstObjParams('uopReg_uop', 'MicroUopRegMov',
+ 'MicroIntMov',
+ { 'code' : 'IWRa = URb;',
+ 'predicate_test' : predicateTest },
+ ['IsMicroop'])
+
+ microUopRegMovRetIop = ArmInstObjParams('movret_uop', 'MicroUopRegMovRet',
+ 'MicroIntMov',
+ { 'code': microRetUopCode % 'URb',
+ 'predicate_test': predicateTest},
+ [ 'IsMicroop', 'IsNonSpeculative',
+ 'IsSerializeAfter', 'IsSquashAfter'])
setPCCPSRDecl = '''
CPSR cpsrOrCondCodes = URc;
CondCodesGE = new_cpsr.ge;
'''
- microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
- 'MicroSetPCCPSR',
- {'code': setPCCPSRDecl,
- 'predicate_test': predicateTest},
- ['IsMicroop', 'IsSerializeAfter'])
+ microUopSetPCCPSRIop = ArmInstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
+ 'MicroSetPCCPSR',
+ { 'code' : setPCCPSRDecl,
+ 'predicate_test' : predicateTest },
+ ['IsMicroop', 'IsSerializeAfter'])
header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
MicroIntImmDeclare.subst(microAddXiUopIop) + \
}};
let {{
- iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
+ iop = ArmInstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
header_output = MacroMemDeclare.subst(iop)
decoder_output = MacroMemConstructor.subst(iop)
- iop = InstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", [])
+ iop = ArmInstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", [])
header_output += PairMemDeclare.subst(iop)
decoder_output += PairMemConstructor.subst(iop)
- iopImm = InstObjParams("bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "")
- iopPre = InstObjParams("bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "")
- iopPost = InstObjParams("bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "")
+ iopImm = ArmInstObjParams(
+ "bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "")
+ iopPre = ArmInstObjParams(
+ "bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "")
+ iopPost = ArmInstObjParams(
+ "bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "")
for iop in (iopImm, iopPre, iopPost):
header_output += BigFpMemImmDeclare.subst(iop)
decoder_output += BigFpMemImmConstructor.subst(iop)
- iop = InstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "")
+ iop = ArmInstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "")
header_output += BigFpMemRegDeclare.subst(iop)
decoder_output += BigFpMemRegConstructor.subst(iop)
- iop = InstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "")
+ iop = ArmInstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "")
header_output += BigFpMemLitDeclare.subst(iop)
decoder_output += BigFpMemLitConstructor.subst(iop)
- iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
+ iop = ArmInstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
header_output += VMemMultDeclare.subst(iop)
decoder_output += VMemMultConstructor.subst(iop)
- iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
+ iop = ArmInstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
header_output += VMemSingleDeclare.subst(iop)
decoder_output += VMemSingleConstructor.subst(iop)
- iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", [])
+ iop = ArmInstObjParams("vstmult", "VstMult", 'VstMultOp', "", [])
header_output += VMemMultDeclare.subst(iop)
decoder_output += VMemMultConstructor.subst(iop)
- iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", [])
+ iop = ArmInstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", [])
header_output += VMemSingleDeclare.subst(iop)
decoder_output += VMemSingleConstructor.subst(iop)
- vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
+ vfpIop = ArmInstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
header_output += MacroVFPMemDeclare.subst(vfpIop)
decoder_output += MacroVFPMemConstructor.subst(vfpIop)
}};
if 'memacc_epilog_code' in codeBlobsCopy:
del codeBlobsCopy['memacc_epilog_code']
- iop = InstObjParams(name, Name, base,
- codeBlobsCopy, instFlagsCopy)
+ iop = ArmInstObjParams(name, Name, base,
+ codeBlobsCopy, instFlagsCopy)
if 'memacc_epilog_code' in codeBlobs:
iop.snippets['memacc_code'] += codeBlobs['memacc_epilog_code']
header_output = self.declareTemplate.subst(iop)
self.completeAccTemplate.subst(iop)
if wbDecl is not None or pcDecl is not None:
- iop = InstObjParams(name, macroName, base,
- { "wb_decl" : wbDecl,
- "pc_decl" : pcDecl,
- "acc_name" : Name,
- "use_uops" : use_uops,
- "use_pc" : use_pc,
- "use_wb" : use_wb,
- "fa_code" : '',
- "is_ras_pop" : is_ras_pop },
- ['IsMacroop'])
+ iop = ArmInstObjParams(name, macroName, base,
+ { "wb_decl" : wbDecl,
+ "pc_decl" : pcDecl,
+ "acc_name" : Name,
+ "use_uops" : use_uops,
+ "use_pc" : use_pc,
+ "use_wb" : use_wb,
+ "fa_code" : '',
+ "is_ras_pop" : is_ras_pop },
+ ['IsMacroop'])
header_output += self.declareTemplate.subst(iop)
decoder_output += self.constructTemplate.subst(iop)
exec_output += PanicExecute.subst(iop) + \
}
'''
- svcIop = InstObjParams("svc", "Svc", "ImmOp",
- { "code": svcCode,
- "predicate_test": predicateTest,
- "thumb_semihost": '0xAB',
- "arm_semihost": '0x123456' },
- ["IsSyscall", "IsNonSpeculative",
- "IsSerializeAfter"])
+ svcIop = ArmInstObjParams("svc", "Svc", "ImmOp",
+ { "code": svcCode,
+ "predicate_test": predicateTest,
+ "thumb_semihost": '0xAB',
+ "arm_semihost": '0x123456' },
+ ["IsSyscall", "IsNonSpeculative",
+ "IsSerializeAfter"])
header_output = ImmOpDeclare.subst(svcIop)
decoder_output = SemihostConstructor.subst(svcIop)
exec_output = PredOpExecute.subst(svcIop)
}
'''
- hltIop = InstObjParams("hlt", "Hlt", "ImmOp",
- { "code": hltCode,
- "predicate_test": predicateTest,
- "thumb_semihost": '0x3C',
- "arm_semihost": '0xF000' },
- ["IsNonSpeculative", "IsSerializeAfter"])
+ hltIop = ArmInstObjParams("hlt", "Hlt", "ImmOp",
+ { "code": hltCode,
+ "predicate_test": predicateTest,
+ "thumb_semihost": '0x3C',
+ "arm_semihost": '0xF000' },
+ ["IsNonSpeculative", "IsSerializeAfter"])
header_output += ImmOpDeclare.subst(hltIop)
decoder_output += SemihostConstructor.subst(hltIop)
exec_output += PredOpExecute.subst(hltIop)
}
'''
- smcIop = InstObjParams("smc", "Smc", "PredOp",
- { "code": smcCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsSerializeAfter"])
+ smcIop = ArmInstObjParams("smc", "Smc", "PredOp",
+ { "code": smcCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsSerializeAfter"])
header_output += BasicDeclare.subst(smcIop)
decoder_output += BasicConstructor.subst(smcIop)
exec_output += PredOpExecute.subst(smcIop)
}
'''
- hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
- { "code": hvcCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsSerializeAfter"])
+ hvcIop = ArmInstObjParams("hvc", "Hvc", "ImmOp",
+ { "code": hvcCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsSerializeAfter"])
header_output += ImmOpDeclare.subst(hvcIop)
decoder_output += ImmOpConstructor.subst(hvcIop)
exec_output += PredOpExecute.subst(hvcIop)
NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
'''
- eretIop = InstObjParams("eret", "Eret", "PredOp",
- { "code": eretCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsSerializeAfter",
- "IsSquashAfter"])
+ eretIop = ArmInstObjParams("eret", "Eret", "PredOp",
+ { "code": eretCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsSerializeAfter",
+ "IsSquashAfter"])
header_output += BasicDeclare.subst(eretIop)
decoder_output += BasicConstructor.subst(eretIop)
exec_output += PredOpExecute.subst(eretIop)
instCode = implCode % data
- crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
- { "code": instCode,
- "predicate_test": predicateTest }, [])
+ crcIop = ArmInstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
+ { "code": instCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(crcIop)
decoder_output += RegRegRegOpConstructor.subst(crcIop)
exec_output += PredOpExecute.subst(crcIop)
Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
'''
- mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
- { "code": mrsCpsrCode,
- "predicate_test": condPredicateTest },
- ["IsSerializeBefore"])
+ mrsCpsrIop = ArmInstObjParams("mrs", "MrsCpsr", "MrsOp",
+ { "code": mrsCpsrCode,
+ "predicate_test": condPredicateTest },
+ ["IsSerializeBefore"])
header_output += MrsDeclare.subst(mrsCpsrIop)
decoder_output += MrsConstructor.subst(mrsCpsrIop)
exec_output += PredOpExecute.subst(mrsCpsrIop)
mrsSpsrCode = "Dest = Spsr"
- mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
- { "code": mrsSpsrCode,
- "predicate_test": predicateTest },
- ["IsSerializeBefore"])
+ mrsSpsrIop = ArmInstObjParams("mrs", "MrsSpsr", "MrsOp",
+ { "code": mrsSpsrCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeBefore"])
header_output += MrsDeclare.subst(mrsSpsrIop)
decoder_output += MrsConstructor.subst(mrsSpsrIop)
exec_output += PredOpExecute.subst(mrsSpsrIop)
mnemonic);
}
'''
- mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
- { "code": mrsBankedRegCode,
- "predicate_test": predicateTest },
- ["IsSerializeBefore"])
+ mrsBankedRegIop = ArmInstObjParams("mrs", "MrsBankedReg", "MrsOp",
+ { "code": mrsBankedRegCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeBefore"])
header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
exec_output += PredOpExecute.subst(mrsBankedRegIop)
mnemonic);
}
'''
- msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
- { "code": msrBankedRegCode,
- "predicate_test": predicateTest },
- ["IsSerializeAfter", "IsNonSpeculative"])
+ msrBankedRegIop = ArmInstObjParams("msr", "MsrBankedReg", "MsrRegOp",
+ { "code": msrBankedRegCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter",
+ "IsNonSpeculative"])
header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
exec_output += PredOpExecute.subst(msrBankedRegIop)
CondCodesV = new_cpsr.v;
CondCodesGE = new_cpsr.ge;
'''
- msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
- { "code": msrCpsrRegCode,
- "predicate_test": condPredicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ msrCpsrRegIop = ArmInstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
+ { "code": msrCpsrRegCode,
+ "predicate_test": condPredicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrRegDeclare.subst(msrCpsrRegIop)
decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
exec_output += PredOpExecute.subst(msrCpsrRegIop)
msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
- msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
- { "code": msrSpsrRegCode,
- "predicate_test": predicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ msrSpsrRegIop = ArmInstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
+ { "code": msrSpsrRegCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrRegDeclare.subst(msrSpsrRegIop)
decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
exec_output += PredOpExecute.subst(msrSpsrRegIop)
CondCodesV = new_cpsr.v;
CondCodesGE = new_cpsr.ge;
'''
- msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
- { "code": msrCpsrImmCode,
- "predicate_test": condPredicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ msrCpsrImmIop = ArmInstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
+ { "code": msrCpsrImmCode,
+ "predicate_test": condPredicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrImmDeclare.subst(msrCpsrImmIop)
decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
exec_output += PredOpExecute.subst(msrCpsrImmIop)
msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
- msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
- { "code": msrSpsrImmCode,
- "predicate_test": predicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ msrSpsrImmIop = ArmInstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
+ { "code": msrSpsrImmCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrImmDeclare.subst(msrSpsrImmIop)
decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
exec_output += PredOpExecute.subst(msrSpsrImmIop)
uint32_t val = Op1;
Dest = swap_byte(val);
'''
- revIop = InstObjParams("rev", "Rev", "RegRegOp",
- { "code": revCode,
- "predicate_test": predicateTest }, [])
+ revIop = ArmInstObjParams("rev", "Rev", "RegRegOp",
+ { "code": revCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(revIop)
decoder_output += RegRegOpConstructor.subst(revIop)
exec_output += PredOpExecute.subst(revIop)
(bits(val, 31, 24) << 16) |
(bits(val, 23, 16) << 24);
'''
- rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
- { "code": rev16Code,
- "predicate_test": predicateTest }, [])
+ rev16Iop = ArmInstObjParams("rev16", "Rev16", "RegRegOp",
+ { "code": rev16Code,
+ "predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(rev16Iop)
decoder_output += RegRegOpConstructor.subst(rev16Iop)
exec_output += PredOpExecute.subst(rev16Iop)
uint16_t val = Op1;
Dest = sext<16>(swap_byte(val));
'''
- revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
- { "code": revshCode,
- "predicate_test": predicateTest }, [])
+ revshIop = ArmInstObjParams("revsh", "Revsh", "RegRegOp",
+ { "code": revshCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(revshIop)
decoder_output += RegRegOpConstructor.subst(revshIop)
exec_output += PredOpExecute.subst(revshIop)
rbitCode = '''
Dest = reverseBits(Op1);
'''
- rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
- { "code": rbitCode,
- "predicate_test": predicateTest }, [])
+ rbitIop = ArmInstObjParams("rbit", "Rbit", "RegRegOp",
+ { "code": rbitCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(rbitIop)
decoder_output += RegRegOpConstructor.subst(rbitIop)
exec_output += PredOpExecute.subst(rbitIop)
clzCode = '''
Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
'''
- clzIop = InstObjParams("clz", "Clz", "RegRegOp",
- { "code": clzCode,
- "predicate_test": predicateTest }, [])
+ clzIop = ArmInstObjParams("clz", "Clz", "RegRegOp",
+ { "code": clzCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(clzIop)
decoder_output += RegRegOpConstructor.subst(clzIop)
exec_output += PredOpExecute.subst(clzIop)
CpsrQ = 1 << 27;
Dest = res;
'''
- ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
- { "code": ssatCode,
- "predicate_test": pickPredicate(ssatCode) }, [])
+ ssatIop = ArmInstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
+ { "code": ssatCode,
+ "predicate_test": pickPredicate(ssatCode) },
+ [])
header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
exec_output += PredOpExecute.subst(ssatIop)
CpsrQ = 1 << 27;
Dest = res;
'''
- usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
- { "code": usatCode,
- "predicate_test": pickPredicate(usatCode) }, [])
+ usatIop = ArmInstObjParams("usat", "Usat", "RegImmRegShiftOp",
+ { "code": usatCode,
+ "predicate_test": pickPredicate(usatCode) },
+ [])
header_output += RegImmRegShiftOpDeclare.subst(usatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
exec_output += PredOpExecute.subst(usatIop)
replaceBits(resTemp, 31, 16, res);
Dest = resTemp;
'''
- ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
- { "code": ssat16Code,
- "predicate_test": pickPredicate(ssat16Code) }, [])
+ ssat16Iop = ArmInstObjParams("ssat16", "Ssat16", "RegImmRegOp",
+ { "code": ssat16Code,
+ "predicate_test":
+ pickPredicate(ssat16Code) }, [])
header_output += RegImmRegOpDeclare.subst(ssat16Iop)
decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
exec_output += PredOpExecute.subst(ssat16Iop)
replaceBits(resTemp, 31, 16, res);
Dest = resTemp;
'''
- usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
- { "code": usat16Code,
- "predicate_test": pickPredicate(usat16Code) }, [])
+ usat16Iop = ArmInstObjParams("usat16", "Usat16", "RegImmRegOp",
+ { "code": usat16Code,
+ "predicate_test":
+ pickPredicate(usat16Code) }, [])
header_output += RegImmRegOpDeclare.subst(usat16Iop)
decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
exec_output += PredOpExecute.subst(usat16Iop)
- sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
- { "code":
- "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
- "predicate_test": predicateTest }, [])
+ sxtbIop = ArmInstObjParams("sxtb", "Sxtb", "RegImmRegOp",
+ { "code":
+ "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
+ "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(sxtbIop)
decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
exec_output += PredOpExecute.subst(sxtbIop)
- sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
- { "code":
- '''
- Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
- Op1;
- ''',
- "predicate_test": predicateTest }, [])
+ sxtabIop = ArmInstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
+ { "code":
+ '''
+ Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
+ Op1;
+ ''',
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
exec_output += PredOpExecute.subst(sxtabIop)
sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
Dest = resTemp;
'''
- sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
- { "code": sxtb16Code,
- "predicate_test": predicateTest }, [])
+ sxtb16Iop = ArmInstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
+ { "code": sxtb16Code,
+ "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
exec_output += PredOpExecute.subst(sxtb16Iop)
bits(Op1, 31, 16));
Dest = resTemp;
'''
- sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
- { "code": sxtab16Code,
- "predicate_test": predicateTest }, [])
+ sxtab16Iop = ArmInstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
+ { "code": sxtab16Code,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
exec_output += PredOpExecute.subst(sxtab16Iop)
rotated = (rotated | (rotated << 32)) >> imm;
Dest = sext<16>((uint16_t)rotated);
'''
- sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
- { "code": sxthCode,
- "predicate_test": predicateTest }, [])
+ sxthIop = ArmInstObjParams("sxth", "Sxth", "RegImmRegOp",
+ { "code": sxthCode,
+ "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(sxthIop)
decoder_output += RegImmRegOpConstructor.subst(sxthIop)
exec_output += PredOpExecute.subst(sxthIop)
rotated = (rotated | (rotated << 32)) >> imm;
Dest = sext<16>((uint16_t)rotated) + Op1;
'''
- sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
- { "code": sxtahCode,
- "predicate_test": predicateTest }, [])
+ sxtahIop = ArmInstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
+ { "code": sxtahCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
exec_output += PredOpExecute.subst(sxtahIop)
- uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
- { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
- "predicate_test": predicateTest }, [])
+ uxtbIop = ArmInstObjParams("uxtb", "Uxtb", "RegImmRegOp",
+ { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
+ "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(uxtbIop)
decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
exec_output += PredOpExecute.subst(uxtbIop)
- uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
- { "code":
- "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
- "predicate_test": predicateTest }, [])
+ uxtabIop = ArmInstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
+ { "code":
+ "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
exec_output += PredOpExecute.subst(uxtabIop)
(uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
Dest = resTemp;
'''
- uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
- { "code": uxtb16Code,
- "predicate_test": predicateTest }, [])
+ uxtb16Iop = ArmInstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
+ { "code": uxtb16Code,
+ "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
exec_output += PredOpExecute.subst(uxtb16Iop)
bits(Op1, 31, 16));
Dest = resTemp;
'''
- uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
- { "code": uxtab16Code,
- "predicate_test": predicateTest }, [])
+ uxtab16Iop = ArmInstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
+ { "code": uxtab16Code,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
exec_output += PredOpExecute.subst(uxtab16Iop)
rotated = (rotated | (rotated << 32)) >> imm;
Dest = (uint16_t)rotated;
'''
- uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
- { "code": uxthCode,
- "predicate_test": predicateTest }, [])
+ uxthIop = ArmInstObjParams("uxth", "Uxth", "RegImmRegOp",
+ { "code": uxthCode,
+ "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(uxthIop)
decoder_output += RegImmRegOpConstructor.subst(uxthIop)
exec_output += PredOpExecute.subst(uxthIop)
rotated = (rotated | (rotated << 32)) >> imm;
Dest = (uint16_t)rotated + Op1;
'''
- uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
- { "code": uxtahCode,
- "predicate_test": predicateTest }, [])
+ uxtahIop = ArmInstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
+ { "code": uxtahCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
exec_output += PredOpExecute.subst(uxtahIop)
}
Dest = resTemp;
'''
- selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
- { "code": selCode,
- "predicate_test": predicateTest }, [])
+ selIop = ArmInstObjParams("sel", "Sel", "RegRegRegOp",
+ { "code": selCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(selIop)
decoder_output += RegRegRegOpConstructor.subst(selIop)
exec_output += PredOpExecute.subst(selIop)
}
Dest = resTemp;
'''
- usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
- { "code": usad8Code,
- "predicate_test": predicateTest }, [])
+ usad8Iop = ArmInstObjParams("usad8", "Usad8", "RegRegRegOp",
+ { "code": usad8Code,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(usad8Iop)
decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
exec_output += PredOpExecute.subst(usad8Iop)
}
Dest = Op3 + resTemp;
'''
- usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
- { "code": usada8Code,
- "predicate_test": predicateTest }, [])
+ usada8Iop = ArmInstObjParams("usada8", "Usada8", "RegRegRegRegOp",
+ { "code": usada8Code,
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
exec_output += PredOpExecute.subst(usada8Iop)
return softwareBreakpoint32(xc, imm16);
'''
- bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
+ bkptIop = ArmInstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
header_output += BasicDeclare.subst(bkptIop)
decoder_output += BasicConstructor.subst(bkptIop)
exec_output += BasicExecute.subst(bkptIop)
- nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
+ nopIop = ArmInstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
header_output += BasicDeclare.subst(nopIop)
decoder_output += BasicConstructor64.subst(nopIop)
exec_output += BasicExecute.subst(nopIop)
- yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
+ yieldIop = ArmInstObjParams("yield", "YieldInst", "PredOp", \
{ "code" : "", "predicate_test" : predicateTest })
header_output += BasicDeclare.subst(yieldIop)
decoder_output += BasicConstructor.subst(yieldIop)
// and SEV interrupts
SevMailbox = 1;
'''
- wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
+ wfeIop = ArmInstObjParams("wfe", "WfeInst", "PredOp", \
{ "code" : wfeCode,
"pred_fixup" : wfePredFixUpCode,
"predicate_test" : predicateTest },
}
tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
'''
- wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
+ wfiIop = ArmInstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
["IsNonSpeculative", "IsQuiesce",
"IsSerializeAfter", "IsUnverifiable"])
sendEvent(oc);
}
'''
- sevIop = InstObjParams("sev", "SevInst", "PredOp", \
+ sevIop = ArmInstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
header_output += BasicDeclare.subst(sevIop)
sevlCode = '''
SevMailbox = 1;
'''
- sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
+ sevlIop = ArmInstObjParams("sevl", "SevlInst", "PredOp", \
{ "code" : sevlCode, "predicate_test" : predicateTest },
["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
header_output += BasicDeclare.subst(sevlIop)
decoder_output += BasicConstructor.subst(sevlIop)
exec_output += BasicExecute.subst(sevlIop)
- itIop = InstObjParams("it", "ItInst", "PredOp", \
+ itIop = ArmInstObjParams("it", "ItInst", "PredOp", \
{ "code" : ";",
"predicate_test" : predicateTest }, [])
header_output += BasicDeclare.subst(itIop)
unknownCode = '''
return std::make_shared<UndefinedInstruction>(machInst, true);
'''
- unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
- { "code": unknownCode,
- "predicate_test": predicateTest })
+ unknownIop = ArmInstObjParams("unknown", "Unknown", "UnknownOp", \
+ { "code": unknownCode,
+ "predicate_test": predicateTest })
header_output += BasicDeclare.subst(unknownIop)
decoder_output += BasicConstructor.subst(unknownIop)
exec_output += PredOpExecute.subst(unknownIop)
ubfxCode = '''
Dest = bits(Op1, imm2, imm1);
'''
- ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
- { "code": ubfxCode,
- "predicate_test": predicateTest }, [])
+ ubfxIop = ArmInstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
+ { "code": ubfxCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
exec_output += PredOpExecute.subst(ubfxIop)
int32_t resTemp = bits(Op1, imm2, imm1);
Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
'''
- sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
- { "code": sbfxCode,
- "predicate_test": predicateTest }, [])
+ sbfxIop = ArmInstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
+ { "code": sbfxCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
exec_output += PredOpExecute.subst(sbfxIop)
bfcCode = '''
Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
'''
- bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
- { "code": bfcCode,
- "predicate_test": predicateTest }, [])
+ bfcIop = ArmInstObjParams("bfc", "Bfc", "RegRegImmImmOp",
+ { "code": bfcCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegImmImmOpDeclare.subst(bfcIop)
decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
exec_output += PredOpExecute.subst(bfcIop)
uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
'''
- bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
- { "code": bfiCode,
- "predicate_test": predicateTest }, [])
+ bfiIop = ArmInstObjParams("bfi", "Bfi", "RegRegImmImmOp",
+ { "code": bfiCode,
+ "predicate_test": predicateTest }, [])
header_output += RegRegImmImmOpDeclare.subst(bfiIop)
decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
exec_output += PredOpExecute.subst(bfiIop)
Dest = MiscOp1;
'''
- mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
- { "code": mrc14code,
- "predicate_test": predicateTest }, [])
+ mrc14Iop = ArmInstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
+ { "code": mrc14code,
+ "predicate_test": predicateTest }, [])
header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
exec_output += PredOpExecute.subst(mrc14Iop)
}
MiscDest = Op1;
'''
- mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
- { "code": mcr14code,
- "predicate_test": predicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ mcr14Iop = ArmInstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
+ { "code": mcr14code,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
exec_output += PredOpExecute.subst(mcr14Iop)
Dest = MiscNsBankedOp1;
'''
- mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
- { "code": mrc15code,
- "predicate_test": predicateTest }, [])
+ mrc15Iop = ArmInstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
+ { "code": mrc15code,
+ "predicate_test": predicateTest }, [])
header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
exec_output += PredOpExecute.subst(mrc15Iop)
}
MiscNsBankedDest = Op1;
'''
- mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
- { "code": mcr15code,
- "predicate_test": predicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ mcr15Iop = ArmInstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
+ { "code": mcr15code,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
exec_output += PredOpExecute.subst(mcr15Iop)
Dest = bits(MiscNsBankedOp164, 63, 32);
Dest2 = bits(MiscNsBankedOp164, 31, 0);
'''
- mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
- { "code": mrrc15code,
- "predicate_test": predicateTest }, [])
+ mrrc15Iop = ArmInstObjParams("mrrc", "Mrrc15", "MrrcOp",
+ { "code": mrrc15code,
+ "predicate_test": predicateTest }, [])
header_output += MrrcOpDeclare.subst(mrrc15Iop)
decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
exec_output += PredOpExecute.subst(mrrc15Iop)
}
MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
'''
- mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
- { "code": mcrr15code,
- "predicate_test": predicateTest }, [])
+ mcrr15Iop = ArmInstObjParams("mcrr", "Mcrr15", "McrrOp",
+ { "code": mcrr15code,
+ "predicate_test": predicateTest }, [])
header_output += McrrOpDeclare.subst(mcrr15Iop)
decoder_output += McrrOpConstructor.subst(mcrr15Iop)
exec_output += PredOpExecute.subst(mcrr15Iop)
NextThumb = true;
NextJazelle = true;
'''
- enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
- { "code": enterxCode,
- "predicate_test": predicateTest }, [])
+ enterxIop = ArmInstObjParams("enterx", "Enterx", "PredOp",
+ { "code": enterxCode,
+ "predicate_test": predicateTest }, [])
header_output += BasicDeclare.subst(enterxIop)
decoder_output += BasicConstructor.subst(enterxIop)
exec_output += PredOpExecute.subst(enterxIop)
NextThumb = true;
NextJazelle = false;
'''
- leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
- { "code": leavexCode,
- "predicate_test": predicateTest }, [])
+ leavexIop = ArmInstObjParams("leavex", "Leavex", "PredOp",
+ { "code": leavexCode,
+ "predicate_test": predicateTest }, [])
header_output += BasicDeclare.subst(leavexIop)
decoder_output += BasicConstructor.subst(leavexIop)
exec_output += PredOpExecute.subst(leavexIop)
Cpsr = cpsr;
fault = checkSETENDEnabled(xc->tcBase(), cpsr);
'''
- setendIop = InstObjParams("setend", "Setend", "ImmOp",
- { "code": setendCode,
- "predicate_test": predicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ setendIop = ArmInstObjParams("setend", "Setend", "ImmOp",
+ { "code": setendCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += ImmOpDeclare.subst(setendIop)
decoder_output += ImmOpConstructor.subst(setendIop)
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
LLSCLock = 0;
'''
- clrexIop = InstObjParams("clrex", "Clrex","PredOp",
- { "code": clrexCode,
- "predicate_test": predicateTest },[])
+ clrexIop = ArmInstObjParams("clrex", "Clrex","PredOp",
+ { "code": clrexCode,
+ "predicate_test": predicateTest },[])
header_output += BasicDeclare.subst(clrexIop)
decoder_output += BasicConstructor.subst(clrexIop)
exec_output += PredOpExecute.subst(clrexIop)
Request::DST_POC);
EA = Op1;
'''
- McrDcimvacIop = InstObjParams("mcr", "McrDcimvac",
- "MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
- "postacc_code": "",
- "ea_code": McrDcimvacCode,
- "predicate_test": predicateTest},
- ['IsStore'])
+ McrDcimvacIop = ArmInstObjParams("mcr", "McrDcimvac",
+ "MiscRegRegImmOp",
+ {"memacc_code": McrDcCheckCode,
+ "postacc_code": "",
+ "ea_code": McrDcimvacCode,
+ "predicate_test": predicateTest},
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
Request::DST_POC);
EA = Op1;
'''
- McrDccmvacIop = InstObjParams("mcr", "McrDccmvac",
- "MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
- "postacc_code": "",
- "ea_code": McrDccmvacCode,
- "predicate_test": predicateTest},
- ['IsStore'])
+ McrDccmvacIop = ArmInstObjParams("mcr", "McrDccmvac",
+ "MiscRegRegImmOp",
+ {"memacc_code": McrDcCheckCode,
+ "postacc_code": "",
+ "ea_code": McrDccmvacCode,
+ "predicate_test": predicateTest},
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
Request::DST_POU);
EA = Op1;
'''
- McrDccmvauIop = InstObjParams("mcr", "McrDccmvau",
- "MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
- "postacc_code": "",
- "ea_code": McrDccmvauCode,
- "predicate_test": predicateTest},
- ['IsStore'])
+ McrDccmvauIop = ArmInstObjParams("mcr", "McrDccmvau",
+ "MiscRegRegImmOp",
+ {"memacc_code": McrDcCheckCode,
+ "postacc_code": "",
+ "ea_code": McrDccmvauCode,
+ "predicate_test": predicateTest},
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
Request::DST_POC);
EA = Op1;
'''
- McrDccimvacIop = InstObjParams("mcr", "McrDccimvac",
- "MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
- "postacc_code": "",
- "ea_code": McrDccimvacCode,
- "predicate_test": predicateTest},
- ['IsStore'])
+ McrDccimvacIop = ArmInstObjParams("mcr", "McrDccimvac",
+ "MiscRegRegImmOp",
+ {"memacc_code": McrDcCheckCode,
+ "postacc_code": "",
+ "ea_code": McrDccimvacCode,
+ "predicate_test": predicateTest},
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
EC_TRAPPED_CP15_MCR_MRC);
}
'''
- isbIop = InstObjParams("isb", "Isb", "ImmOp",
- {"code": isbCode,
- "predicate_test": predicateTest},
- ['IsSquashAfter'])
+ isbIop = ArmInstObjParams("isb", "Isb", "ImmOp",
+ { "code": isbCode,
+ "predicate_test": predicateTest},
+ ['IsSquashAfter'])
header_output += ImmOpDeclare.subst(isbIop)
decoder_output += ImmOpConstructor.subst(isbIop)
exec_output += PredOpExecute.subst(isbIop)
EC_TRAPPED_CP15_MCR_MRC);
}
'''
- dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
- {"code": dsbCode,
+ dsbIop = ArmInstObjParams("dsb", "Dsb", "ImmOp",
+ {"code": dsbCode,
"predicate_test": predicateTest},
['IsReadBarrier', 'IsWriteBarrier',
'IsSerializeAfter'])
EC_TRAPPED_CP15_MCR_MRC);
}
'''
- dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
- {"code": dmbCode,
+ dmbIop = ArmInstObjParams("dmb", "Dmb", "ImmOp",
+ {"code": dmbCode,
"predicate_test": predicateTest},
- ['IsReadBarrier', 'IsWriteBarrier'])
+ ['IsReadBarrier', 'IsWriteBarrier'])
header_output += ImmOpDeclare.subst(dmbIop)
decoder_output += ImmOpConstructor.subst(dmbIop)
exec_output += PredOpExecute.subst(dmbIop)
dbgCode = '''
'''
- dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
- {"code": dbgCode,
+ dbgIop = ArmInstObjParams("dbg", "Dbg", "PredOp",
+ {"code": dbgCode,
"predicate_test": predicateTest})
header_output += BasicDeclare.subst(dbgIop)
decoder_output += BasicConstructor.subst(dbgIop)
}
Cpsr = cpsr;
'''
- cpsIop = InstObjParams("cps", "Cps", "ImmOp",
- { "code": cpsCode,
- "predicate_test": predicateTest },
- ["IsSerializeAfter","IsNonSpeculative"])
+ cpsIop = ArmInstObjParams("cps", "Cps", "ImmOp",
+ { "code": cpsCode,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
header_output += ImmOpDeclare.subst(cpsIop)
decoder_output += ImmOpConstructor.subst(cpsIop)
exec_output += PredOpExecute.subst(cpsIop)
fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5));
'''
- svcIop = InstObjParams("svc", "Svc64", "ImmOp64",
- svcCode, ["IsSyscall", "IsNonSpeculative",
- "IsSerializeAfter"])
+ svcIop = ArmInstObjParams("svc", "Svc64", "ImmOp64",
+ svcCode, ["IsSyscall", "IsNonSpeculative",
+ "IsSerializeAfter"])
header_output = ImmOp64Declare.subst(svcIop)
decoder_output = ImmOp64Constructor.subst(svcIop)
exec_output = BasicExecute.subst(svcIop)
}
'''
- hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64",
- hvcCode, ["IsSyscall", "IsNonSpeculative",
- "IsSerializeAfter"])
+ hvcIop = ArmInstObjParams("hvc", "Hvc64", "ImmOp64",
+ hvcCode, ["IsSyscall", "IsNonSpeculative",
+ "IsSerializeAfter"])
header_output += ImmOp64Declare.subst(hvcIop)
decoder_output += ImmOp64Constructor.subst(hvcIop)
exec_output += BasicExecute.subst(hvcIop)
}
'''
- smcIop = InstObjParams("smc", "Smc64", "ImmOp64",
- smcCode, ["IsNonSpeculative", "IsSerializeAfter"])
+ smcIop = ArmInstObjParams("smc", "Smc64", "ImmOp64",
+ smcCode, ["IsNonSpeculative", "IsSerializeAfter"])
header_output += ImmOp64Declare.subst(smcIop)
decoder_output += ImmOp64Constructor.subst(smcIop)
exec_output += BasicExecute.subst(smcIop)
'''
bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);'
- bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode);
+ bfmIop = ArmInstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode);
subst("RegRegImmImmOp64", bfmIop)
ubfmCode = bfmMaskCode + 'Dest64 = result;'
- ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode);
+ ubfmIop = ArmInstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode);
subst("RegRegImmImmOp64", ubfmIop)
sbfmCode = bfmMaskCode + \
'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);'
- sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode);
+ sbfmIop = ArmInstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode);
subst("RegRegImmImmOp64", sbfmIop)
extrCode = '''
Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm);
}
'''
- extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode);
+ extrIop = ArmInstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode);
subst("RegRegRegImmOp64", extrIop);
unknownCode = '''
return std::make_shared<UndefinedInstruction>(machInst, true);
'''
- unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64",
- unknownCode)
+ unknown64Iop = ArmInstObjParams("unknown", "Unknown64", "UnknownOp64",
+ unknownCode)
header_output += BasicDeclare.subst(unknown64Iop)
decoder_output += BasicConstructor64.subst(unknown64Iop)
exec_output += BasicExecute.subst(unknown64Iop)
- isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "",
- ['IsSquashAfter'])
+ isbIop = ArmInstObjParams("isb", "Isb64", "ArmStaticInst", "",
+ ['IsSquashAfter'])
header_output += BasicDeclare.subst(isbIop)
decoder_output += BasicConstructor64.subst(isbIop)
exec_output += BasicExecute.subst(isbIop)
- dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
- ['IsReadBarrier', 'IsWriteBarrier',
- 'IsSerializeAfter'])
+ dsbIop = ArmInstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
header_output += BasicDeclare.subst(dsbIop)
decoder_output += BasicConstructor64.subst(dsbIop)
exec_output += BasicExecute.subst(dsbIop)
- dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
- ['IsReadBarrier', 'IsWriteBarrier'])
+ dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
+ ['IsReadBarrier', 'IsWriteBarrier'])
header_output += BasicDeclare.subst(dmbIop)
decoder_output += BasicConstructor64.subst(dmbIop)
exec_output += BasicExecute.subst(dmbIop)
- clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst",
- "LLSCLock = 0;")
+ clrexIop = ArmInstObjParams("clrex", "Clrex64", "ArmStaticInst",
+ "LLSCLock = 0;")
header_output += BasicDeclare.subst(clrexIop)
decoder_output += BasicConstructor64.subst(clrexIop)
exec_output += BasicExecute.subst(clrexIop)
bits(machInst, 20, 5));
'''
- brkIop = InstObjParams("brk", "Brk64", "ImmOp64",
- brkCode, ["IsSerializeAfter"])
+ brkIop = ArmInstObjParams("brk", "Brk64", "ImmOp64",
+ brkCode, ["IsSerializeAfter"])
header_output += ImmOp64Declare.subst(brkIop)
decoder_output += ImmOp64Constructor.subst(brkIop)
exec_output += BasicExecute.subst(brkIop)
'''
- hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64",
- hltCode, ["IsNonSpeculative", "IsSerializeAfter"])
+ hltIop = ArmInstObjParams("hlt", "Hlt64", "ImmOp64", hltCode,
+ ["IsNonSpeculative", "IsSerializeAfter"])
header_output += ImmOp64Declare.subst(hltIop)
decoder_output += SemihostConstructor64.subst(hltIop)
exec_output += BasicExecute.subst(hltIop)
Name = mnem.capitalize()
if unCc:
- iop = InstObjParams(mnem, Name, base,
- {"code" : code,
- "predicate_test": pickPredicate(code),
- "op_class": "IntMultOp" })
+ iop = ArmInstObjParams(mnem, Name, base,
+ { "code" : code, "predicate_test": pickPredicate(code),
+ "op_class": "IntMultOp" })
if doCc:
- iopCc = InstObjParams(mnem + "s", Name + "Cc", base,
- {"code" : code + ccCode,
- "predicate_test": pickPredicate(code + ccCode),
- "op_class": "IntMultOp" })
+ iopCc = ArmInstObjParams(mnem + "s", Name + "Cc", base,
+ { "code" : code + ccCode,
+ "predicate_test": pickPredicate(code + ccCode),
+ "op_class": "IntMultOp" })
if regs == 3:
declare = Mult3Declare
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegRegImmOp" if byElem else "RegRegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegRegImmOp" if byElem else "RegRegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
if byElem:
header_output += NeonRegRegRegImmOpDeclare.subst(iop)
else:
eWalkCode += '''
FpDestP%(reg)d = destRegs[%(reg)d];
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "FpRegRegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "FpRegRegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegRegOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegRegOp",
- { "code": eWalkCode,
- "r_count": 2,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegRegOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegRegOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegRegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegRegImmOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegRegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegRegImmOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d = destRegs[%(reg)d];
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "FpRegRegRegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "FpRegRegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegRegImmOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destRegs.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegImmOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegImmOp",
- { "code": eWalkCode,
- "r_count": 2,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegImmOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegImmOp",
- { "code": eWalkCode,
- "r_count": 2,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegImmOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegImmOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
FpOp1P%(reg)d_uw = letoh(srcReg1.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d = destRegs[%(reg)d];
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "FpRegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "FpRegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegOp",
- { "code": eWalkCode,
- "r_count": 2,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegImmOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegOp",
- { "code": eWalkCode,
- "r_count": 2,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonUnequalRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
eWalkCode += '''
FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "RegRegRegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegRegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += NeonRegRegRegImmOpDeclare.subst(iop)
exec_output += NeonEqualRegExecute.subst(iop)
for type in types:
FpDestP0_uw = letoh(destReg.regs[0]);
FpDestP1_uw = letoh(destReg.regs[1]);
'''
- iop = InstObjParams(name, Name,
- "RegRegRegOp",
- { "code": code,
- "predicate_test": predicateTest,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "RegRegRegOp",
+ { "code": code,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
header_output += RegRegRegOpDeclare.subst(iop)
decoder_output += RegRegRegOpConstructor.subst(iop)
exec_output += PredOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX2RegImmOp" if byElem else "DataX2RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "DataX2RegImmOp" if byElem else "DataX2RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
if byElem:
header_output += NeonX2RegImmOpDeclare.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX2RegImmOp" if byElem else "DataX2RegOp",
- { "code": eWalkCode,
- "r_count": 2,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "DataX2RegImmOp" if byElem else "DataX2RegOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
if byElem:
header_output += NeonX2RegImmOpDeclare.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegImmOp" if hasImm else "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "DataX1RegImmOp" if hasImm else "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
if hasImm:
header_output += NeonX1RegImmOpDeclare.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegImmOp" if hasImm else "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": 2,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "DataX1RegImmOp" if hasImm else "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
if hasImm:
header_output += NeonX1RegImmOpDeclare.subst(iop)
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegImmOp" if hasImm else "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": 2,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name,
+ "DataX1RegImmOp" if hasImm else "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": 2,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
if hasImm:
header_output += NeonX1RegImmOpDeclare.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX2RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX2RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX2RegOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1Reg2ImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1Reg2ImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1Reg2ImmOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1RegOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1RegOpDeclare.subst(iop)
if long:
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1RegOpDeclare.subst(iop)
exec_output += NeonXUnequalRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataXImmOnlyOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataXImmOnlyOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1RegImmOnlyOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1RegOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1RegOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX2RegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX2RegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX2RegImmOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX1RegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1RegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX1RegImmOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
eWalkCode += '''
%sDest = srcReg.elements[imm];
''' % gprSpec
- iop = InstObjParams(name, Name,
- "DataX1RegImmOp",
- { "code": eWalkCode,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX1RegImmOp",
+ { "code": eWalkCode,
+ "r_count": rCount,
+ "op_class": opClass }, [])
header_output += NeonX1RegImmOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
for type in types:
code += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
- iop = InstObjParams(name, Name,
- "DataX2RegOp",
- { "code": code,
- "r_count": rCount,
- "op_class": opClass }, [])
+ iop = ArmInstObjParams(name, Name, "DataX2RegOp",
+ { "code": code,
+ "r_count": rCount,
+ "op_class": opClass }, [])
iop.snippets["code"] += zeroSveVecRegUpperPartCode % "AA64FpDest"
header_output += NeonX2RegOpDeclare.subst(iop)
exec_output += NeonXEqualRegOpExecute.subst(iop)
loadMemAccCode = convCode + regSetCode
storeMemAccCode = regGetCode + convCode
- loadIop = InstObjParams(name + 'ld',
+ loadIop = ArmInstObjParams(name + 'ld',
'MicroNeonLoad64',
'MicroNeonMemOp',
{ 'mem_decl' : memDecl,
[ 'IsMicroop', 'IsLoad' ])
loadIop.snippets["memacc_code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
- storeIop = InstObjParams(name + 'st',
+ storeIop = ArmInstObjParams(name + 'st',
'MicroNeonStore64',
'MicroNeonMemOp',
{ 'mem_decl' : memDecl,
}
'''
- iop = InstObjParams(name, Name, 'MicroNeonMixOp64',
- { 'code' : eCode, 'op_class' : 'No_OpClass' },
- ['IsMicroop'])
+ iop = ArmInstObjParams(name, Name, 'MicroNeonMixOp64',
+ { 'code' : eCode, 'op_class' : 'No_OpClass' },
+ ['IsMicroop'])
header_output += MicroNeonMixDeclare64.subst(iop)
exec_output += MicroNeonMixExecute64.subst(iop)
output[%(v)d], %(p)d, 0x2);
''' % { 'v': v, 'p': p}
- iop = InstObjParams(name, Name, 'MicroNeonMixOp64',
- { 'code' : eCode, 'op_class' : 'No_OpClass' },
- ['IsMicroop'])
+ iop = ArmInstObjParams(name, Name, 'MicroNeonMixOp64',
+ { 'code' : eCode, 'op_class' : 'No_OpClass' },
+ ['IsMicroop'])
header_output += MicroNeonMixDeclare64.subst(iop)
exec_output += MicroNeonMixExecute64.subst(iop)
output[%(v)d], %(p)d, 0x2);
''' % { 'v' : v, 'p' : p }
- iop = InstObjParams(name, Name, 'MicroNeonMixLaneOp64',
- { 'code' : eCode }, ['IsMicroop'])
+ iop = ArmInstObjParams(name, Name, 'MicroNeonMixLaneOp64',
+ { 'code' : eCode }, ['IsMicroop'])
header_output += MicroNeonMixLaneDeclare64.subst(iop)
exec_output += MicroNeonMixExecute64.subst(iop)
output[%(v)d], %(p)d, 0x2);
''' % { 'v' : v, 'p' : p }
- iop = InstObjParams(name, Name, 'MicroNeonMixLaneOp64',
- { 'code' : eCode }, ['IsMicroop'])
+ iop = ArmInstObjParams(name, Name, 'MicroNeonMixLaneOp64',
+ { 'code' : eCode }, ['IsMicroop'])
header_output += MicroNeonMixLaneDeclare64.subst(iop)
exec_output += MicroNeonMixExecute64.subst(iop)
let {{
- iop = InstObjParams('vldmult64', 'VldMult64', 'VldMultOp64', '', [])
+ iop = ArmInstObjParams('vldmult64', 'VldMult64', 'VldMultOp64', '', [])
header_output += VMemMultDeclare64.subst(iop)
decoder_output += VMemMultConstructor64.subst(iop)
- iop = InstObjParams('vstmult64', 'VstMult64', 'VstMultOp64', '', [])
+ iop = ArmInstObjParams('vstmult64', 'VstMult64', 'VstMultOp64', '', [])
header_output += VMemMultDeclare64.subst(iop)
decoder_output += VMemMultConstructor64.subst(iop)
- iop = InstObjParams('vldsingle64', 'VldSingle64', 'VldSingleOp64', '', [])
+ iop = ArmInstObjParams(
+ 'vldsingle64', 'VldSingle64', 'VldSingleOp64', '', [])
header_output += VMemSingleDeclare64.subst(iop)
decoder_output += VMemSingleConstructor64.subst(iop)
- iop = InstObjParams('vstsingle64', 'VstSingle64', 'VstSingleOp64', '', [])
+ iop = ArmInstObjParams(
+ 'vstsingle64', 'VstSingle64', 'VstSingleOp64', '', [])
header_output += VMemSingleDeclare64.subst(iop)
decoder_output += VMemSingleConstructor64.subst(iop)
"op2": 'Op164',
"op": opcode }
- iop = InstObjParams(mnem, mnem, templateBase+"Op", code, optArgs)
+ iop = ArmInstObjParams(mnem, mnem, templateBase+"Op", code, optArgs)
header_output += eval(templateBase + "Declare").subst(iop)
decoder_output += eval(templateBase + "Constructor").subst(iop)
exec_output += BasicExecute.subst(iop)
"""
regoptype = 'RegOp'
- iop = InstObjParams(mnem, mnem, regoptype, code, optArgs)
+ iop = ArmInstObjParams(mnem, mnem, regoptype, code, optArgs)
header_output += eval(templateBase + "Declare").subst(iop)
decoder_output += eval(templateBase + "Constructor").subst(iop)
exec_output += BasicExecute.subst(iop)
%(op)s
AA64FpDest_x[i] = destElem;
}''' % {'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveAdrOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveAdrOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveAdrOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
CondCodesC = !last;
CondCodesV = false;
'''%{'op': op, 'stype': srcType}
- iop = InstObjParams(name, 'Sve' + Name, 'SveWhileOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveWhileOp',
{'code': code, 'op_class': opClass, 'srcIs32b': srcSize}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SveWhileOpDeclare.subst(iop)
CondCodesV = !CondCodesC;
}
''' % {'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveCompTermOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveCompTermOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveCompTermOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
else:
code += '''
%(op)s''' % {'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SvePredCountOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredCountOp',
{'code': code, 'op_class': opClass, 'srcIs32b': srcSize,
'destIsVec': destType}, [])
header_output += SvePredCountOpDeclare.subst(iop)
}
XDest = count;
'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePredCountPredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredCountPredOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SvePredCountPredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
for (unsigned i = 0; i < eCount; i++) {
AA64FpDest_x[i] = srcElem1 + i * srcElem2;
}'''
- iop = InstObjParams('index', 'SveIndex'+fmt, 'SveIndex'+fmt+'Op',
+ iop = ArmInstObjParams('index', 'SveIndex'+fmt, 'SveIndex'+fmt+'Op',
{'code': code, 'op_class': 'SimdAluOp'})
if fmt == IndexFormat.ImmImm:
header_output += SveIndexIIOpDeclare.subst(iop)
code += '''
AA64FpDest_xd[i] = destElem;
}'''
- iop = InstObjParams(name, 'Sve' + Name,
- 'SveUnaryPredOp' if predType != PredType.NONE
- else 'SveUnaryUnpredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name,
+ 'SveUnaryPredOp' if predType != PredType.NONE
+ else 'SveUnaryUnpredOp',
+ {'code': code, 'op_class': opClass}, [])
if predType != PredType.NONE:
header_output += SveWideningUnaryPredOpDeclare.subst(iop)
else:
code += '''
AA64FpDest_x[i] = destElem;
}'''
- iop = InstObjParams(name, 'Sve' + Name,
- 'SveUnaryPredOp' if predType != PredType.NONE
- else 'SveUnaryUnpredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name,
+ 'SveUnaryPredOp' if predType != PredType.NONE
+ else 'SveUnaryUnpredOp',
+ {'code': code, 'op_class': opClass}, [])
if predType != PredType.NONE:
header_output += SveUnaryPredOpDeclare.subst(iop)
else:
'assign': assign_code
}
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveWideningUnaryPredOpDeclare.subst(iop)
exec_output += SveWideningOpExecute.subst(iop)
for type in types:
}
AA64FpDest_x[0] = destElem;
''' % {'op': op, 'identity': identity}
- iop = InstObjParams(name, 'Sve' + Name, 'SveReducOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveReducOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveReducOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
AA64FpDest_xd[i] = 0;
}
''' % {'op': op, 'identity': identity}
- iop = InstObjParams(name, 'Sve' + Name, 'SveReducOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveReducOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveWideningReducOpDeclare.subst(iop)
exec_output += SveWideningOpExecute.subst(iop)
for type in types:
AA64FpDest_x[i] = 0; // zero upper part
}
''' % {'op': op, 'identity': identity}
- iop = InstObjParams(name, 'Sve' + Name, 'SveReducOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveReducOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveReducOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
code += '''
AA64FpDest_x[i] = destElem;
}'''
- iop = InstObjParams(name, 'Sve' + Name,
+ iop = ArmInstObjParams(name, 'Sve' + Name,
'SveBinImmPredOp' if predType != PredType.NONE
else 'SveBinImmUnpredConstrOp',
{'code': code, 'op_class': opClass}, [])
code += '''
AA64FpDest_x[i] = destElem;
}'''
- iop = InstObjParams(name, 'Sve' + Name,
+ iop = ArmInstObjParams(name, 'Sve' + Name,
'Sve%sWideImm%sOp' % (
'Unary' if isUnary else 'Bin',
'Unpred' if predType == PredType.NONE else 'Pred'),
code += '''
AA64FpDest_x[i] = destElem;
}'''
- iop = InstObjParams(name, 'Sve' + Name,
- 'SveBinDestrPredOp' if predType != PredType.NONE
- else 'SveBinUnpredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name,
+ 'SveBinDestrPredOp' if predType != PredType.NONE
+ else 'SveBinUnpredOp',
+ {'code': code, 'op_class': opClass}, [])
if predType != PredType.NONE:
header_output += SveBinDestrPredOpDeclare.subst(iop)
else:
baseClass = 'SveBinIdxUnpredOp'
- iop = InstObjParams(name, 'Sve' + Name, baseClass,
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, baseClass,
+ {'code': code, 'op_class': opClass}, [])
header_output += SveBinIdxUnpredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
baseClass = 'SveBinDestrPredOp'
else:
baseClass = 'SveBinConstrPredOp'
- iop = InstObjParams(name, 'Sve' + Name, baseClass,
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, baseClass,
+ {'code': code, 'op_class': opClass}, [])
if predType == PredType.NONE:
header_output += SveBinUnpredOpDeclare.subst(iop)
elif isDestructive:
CondCodesV = 0;'''
extraPrologCode += '''
auto& destPred = PDest;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePredLogicalOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredLogicalOp',
+ {'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SvePredLogicalOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());'''
code += iterCode
- iop = InstObjParams(name, 'Sve' + Name, 'SvePredBinPermOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredBinPermOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveBinUnpredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
}''' % {'op': op,
'src_elem_2_ty': 'Element' if isImm else 'const Element&',
'src_elem_2': 'imm' if isImm else 'AA64FpOp2_x[i]'}
- iop = InstObjParams(name, 'Sve' + Name,
- 'SveCmpImmOp' if isImm else 'SveCmpOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name,
+ 'SveCmpImmOp' if isImm else 'SveCmpOp',
+ {'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
if isImm:
header_output += SveCmpImmOpDeclare.subst(iop)
}
AA64FpDest_x[i] = destElem;
}''' % {'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveTerPredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveTerPredOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveTerPredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
AA64FpDest_x[i] = auxDest[i];
}''' % {'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveBinIdxUnpredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
%(op)s
AA64FpDest_x[i] = destElem;
}''' % {'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveTerImmUnpredOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveTerImmUnpredOp',
+ {'code': code, 'op_class': opClass}, [])
header_output += SveTerImmUnpredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
destPred.noneActive(destPred, eCount);
CondCodesC = !destPred.lastActive(destPred, eCount);
CondCodesV = 0;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePtrueOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePtrueOp',
+ {'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SvePtrueOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
'op2Suffix': op2Suffix,
'op2Index': '(i * sizeof(Element)) / 8' if wideop else 'i'
}
- iop = InstObjParams(name, 'Sve' + Name, 'SveIntCmpOp',
- {
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveIntCmpOp',
+ {
'code': code,
'op_class': opClass,
'op2IsWide': 'true' if wideop else 'false',
destPred.noneActive(tmpPred, eCount);
CondCodesC = !destPred.lastActive(tmpPred, eCount);
CondCodesV = 0;'''%{'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveIntCmpImmOp',
- {'code': code, 'op_class': opClass,}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveIntCmpImmOp',
+ {'code': code, 'op_class': opClass,}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SveIntCmpImmOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
%(op)s;
XDest = destElem;
'''%{'op': op, 'dstType': dstType}
- iop = InstObjParams(name, 'Sve' + Name, 'SveElemCountOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveElemCountOp',
{'code': code, 'op_class': opClass, 'dstIsVec': destType,
'dstIs32b': 'true' if dstIs32b else 'false'}, [])
header_output += SveElemCountOpDeclare.subst(iop)
CondCodesV = 0;'''
extraPrologCode += '''
auto& destPred = PDest;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePartBrkOp',
- {'code': code, 'op_class': opClass,
- 'isMerging': 'true' if predType == PredType.MERGE
- else 'false'}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePartBrkOp',
+ {'code': code, 'op_class': opClass,
+ 'isMerging':
+ 'true' if predType == PredType.MERGE
+ else 'false'}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SvePartBrkOpDeclare.subst(iop)
exec_output += SveNonTemplatedOpExecute.subst(iop)
CondCodesV = 0;'''
extraPrologCode += '''
auto& destPred = PDest;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp',
+ {'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SvePartBrkPropOpDeclare.subst(iop)
exec_output += SveNonTemplatedOpExecute.subst(iop)
CondCodesV = 0;'''
extraPrologCode += '''
auto& destPred = PDest;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp',
- {'code': code, 'op_class': opClass}, [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePartBrkPropOp',
+ {'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SvePartBrkPropOpDeclare.subst(iop)
exec_output += SveNonTemplatedOpExecute.subst(iop)
AA64FpDest_x[i] = (Element)0x0;
}
'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp',
- {'code': code, 'op_class': opClass,
- 'isCond': 'true' if isCond else 'false',
- 'isScalar': 'true'
- if destType == DstRegType.Scalar else 'false',
- 'isSimdFp': 'true'
- if destType == DstRegType.SimdFpScalar
- else 'false'},
- [])
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveSelectOp',
+ {'code': code, 'op_class': opClass,
+ 'isCond': 'true' if isCond else 'false',
+ 'isScalar': 'true'
+ if destType == DstRegType.Scalar else 'false',
+ 'isSimdFp': 'true'
+ if destType == DstRegType.SimdFpScalar
+ else 'false'},
+ [])
header_output += SveSelectOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
CondCodesV = 0;'''
extraPrologCode = '''
auto& destPred = PDest;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp',
{'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SveUnaryPredOpDeclare.subst(iop)
CondCodesV = 0;'''
extraPrologCode = '''
auto& destPred = PDest;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredPredOp',
{'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
header_output += SveUnaryPredOpDeclare.subst(iop)
}
AA64FpDest_x[i] = val;
}'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveTblOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveTblOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveBinUnpredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
code += '''
}
'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnpackOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnpackOp',
{'code': code, 'op_class': opClass}, [])
if regType == SrcRegType.Predicate:
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
POp1_ub.noneActive(GpOp_ub, eCount);
CondCodesC = !POp1_ub.lastActive(GpOp_ub, eCount);
CondCodesV = 0;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SvePredTestOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SvePredTestOp',
{'code': code, 'op_class': opClass}, [])
header_output += SvePredicateTestOpDeclare.subst(iop)
exec_output += SveNonTemplatedOpExecute.subst(iop)
x++;
}
}'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveUnaryPredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
M5_VAR_USED auto& destPred = PDest;'''
baseClass = ('SvePredUnaryWImplicitSrcOp' if predType == PredType.NONE
else 'SvePredUnaryWImplicitSrcPredOp')
- iop = InstObjParams(name, 'Sve' + Name, baseClass,
+ iop = ArmInstObjParams(name, 'Sve' + Name, baseClass,
{'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
if predType == PredType.NONE:
M5_VAR_USED auto& destPred = Ffr;'''
baseClass = ('SveWImplicitSrcDstOp' if isSetFfr
else 'SvePredUnaryWImplicitDstOp')
- iop = InstObjParams(name, 'Sve' + Name, baseClass,
+ iop = ArmInstObjParams(name, 'Sve' + Name, baseClass,
{'code': code, 'op_class': opClass}, [])
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
if isSetFfr:
AA64FpDest_x[i] = auxOp1[pos-eCount];
}
'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveBinImmUnpredDestrOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinImmUnpredDestrOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveBinImmUnpredOpDeclare.subst(iop);
exec_output += SveOpExecute.subst(iop)
AA64FpDest_x[i] = auxDest[i];
}
'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveBinDestrPredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinDestrPredOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveBinDestrPredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for (int i = 0; i < eCount; ++i) {
AA64FpDest_x[i] = srcElem1;
}'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveBinImmIdxUnpredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveBinImmIdxUnpredOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveBinImmUnpredOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
destPred.set_raw(i, auxPOp1.get_raw(eCount - i - 1));'''
code += '''
}'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryUnpredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryUnpredOp',
{'code': code, 'op_class': opClass}, [])
if srcType == SrcRegType.Predicate:
iop.snippets['code'] = extraPrologCode + iop.snippets['code']
AA64FpDest_x[i] = AA64FpDestMerge_x[i-1];
}
AA64FpDest_x[0] = srcElem1;'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveUnarySca2VecUnpredOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnarySca2VecUnpredOp',
{'code': code, 'op_class': opClass,
'isSimdFp': 'true' if srcType == SrcRegType.SimdFpScalar
else 'false'}, [])
}
AA64FpDestMerge_xd[i] = res;
}'''
- iop = InstObjParams(name, 'Sve' + Name,
+ iop = ArmInstObjParams(name, 'Sve' + Name,
'SveDotProdIdxOp' if isIndexed else
'SveDotProdOp',
{'code': code, 'op_class': opClass}, [])
AA64FpDest_x[i] = 0;
}
AA64FpDest_x[0] = destElem;'''%{'op': op}
- iop = InstObjParams(name, 'Sve' + Name, 'SveOrdReducOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveOrdReducOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveReducOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
AA64FpDest_x[2 * i + 1] = acc_i;
}
'''
- iop = InstObjParams(name, 'Sve' + Name, 'SveComplexOp',
+ iop = ArmInstObjParams(name, 'Sve' + Name, 'SveComplexOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveComplexOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
AA64FpDest_x[i] = auxDest[i];
}
'''
- iop = InstObjParams(name, 'Sve' + Name,
+ iop = ArmInstObjParams(name, 'Sve' + Name,
'SveComplexIdxOp' if predType == PredType.NONE
else 'SveComplexOp',
{'code': code, 'op_class': opClass}, [])
xc->tcBase());
XDest = eCount * (int64_t) imm;
'''
- rdvlIop = InstObjParams('rdvl', 'SveRdvl', 'RegImmOp', rdvlCode, [])
+ rdvlIop = ArmInstObjParams('rdvl', 'SveRdvl', 'RegImmOp', rdvlCode, [])
header_output += RegImmOpDeclare.subst(rdvlIop)
decoder_output += RegImmOpConstructor.subst(rdvlIop)
exec_output += BasicExecute.subst(rdvlIop)
storeWrEnableCode = '''
auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true);
'''
- loadIop = InstObjParams('ldr',
+ loadIop = ArmInstObjParams('ldr',
'SveLdrPred' if isPred else 'SveLdrVec',
'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill',
{'tpl_header': '',
'fault_code' : '',
'fa_code' : ''},
['IsLoad'])
- storeIop = InstObjParams('str',
+ storeIop = ArmInstObjParams('str',
'SveStrPred' if isPred else 'SveStrVec',
'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill',
{'tpl_header': '',
}
''' % ('' if firstFaulting else nonFaultingCode)
- loadIop = InstObjParams('ld1',
+ loadIop = ArmInstObjParams('ld1',
'SveContigLoadSI' if offsetIsImm else 'SveContigLoadSS',
'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
{'tpl_header': tplHeader,
'fault_code' : '',
'fa_code' : ''},
['IsLoad'])
- storeIop = InstObjParams('st1',
+ storeIop = ArmInstObjParams('st1',
'SveContigStoreSI' if offsetIsImm else 'SveContigStoreSS',
'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
{'tpl_header': tplHeader,
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
['IsStore'])
- faultIop = InstObjParams('ldff1' if firstFaulting else 'ldnf1',
+ faultIop = ArmInstObjParams('ldff1' if firstFaulting else 'ldnf1',
'SveContigFFLoadSS' if firstFaulting else 'SveContigNFLoadSI',
'SveContigMemSS' if firstFaulting else 'SveContigMemSI',
{'tpl_header': tplHeader,
}
}
'''
- iop = InstObjParams('ld1r',
+ iop = ArmInstObjParams('ld1r',
'SveLoadAndRepl',
'SveContigMemSI',
{'tpl_header': tplHeader,
predCheckCode = 'GpOp_x[index]'
faultStatusSetCode = 'PUreg0_x[elemIndex] = 1;'
faultStatusResetCode = 'PUreg0_x[elemIndex] = 0;'
- loadIop = InstObjParams('ld1',
+ loadIop = ArmInstObjParams('ld1',
('SveGatherLoadVIMicroop'
if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM
else 'SveGatherLoadSVMicroop'),
'pred_check_code' : predCheckCode,
'fa_code' : ''},
['IsMicroop', 'IsLoad'])
- storeIop = InstObjParams('st1',
+ storeIop = ArmInstObjParams('st1',
('SveScatterStoreVIMicroop'
if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM
else 'SveScatterStoreSVMicroop'),
Ffr_ub[index * sizeof(RegElemType) + j] = FfrAux_x[index];
}
'''
- iop = InstObjParams('ldff1',
+ iop = ArmInstObjParams('ldff1',
'SveFirstFaultWritebackMicroop',
'MicroOp',
{'tpl_header': tplHeader,
for (unsigned i = 0; i < eCount; i++) {
AA64FpUreg0_ub[i] = AA64FpOp1_ub[i];
}'''
- iop = InstObjParams('ld1',
+ iop = ArmInstObjParams('ld1',
'SveGatherLoadCpySrcVecMicroop',
'MicroOp',
{'code': code},
AA64FpDest_x[i] = AA64FpOp1V3S_x[srcIdx];
}'''
- iop2 = InstObjParams('intrlv',
+ iop2 = ArmInstObjParams('intrlv',
'SveIntrlv2Microop',
'MicroOp',
{'code': code2},
['IsMicroop'])
- iop3 = InstObjParams('intrlv',
+ iop3 = ArmInstObjParams('intrlv',
'SveIntrlv3Microop',
'MicroOp',
{'code': code3},
['IsMicroop'])
- iop4 = InstObjParams('intrlv',
+ iop4 = ArmInstObjParams('intrlv',
'SveIntrlv4Microop',
'MicroOp',
{'code': code4},
AA64FpDest_x[i] = AA64IntrlvReg3_x[srcIdx];
}'''
- iop2 = InstObjParams('deintrlv',
+ iop2 = ArmInstObjParams('deintrlv',
'SveDeIntrlv2Microop',
'MicroOp',
{'code': code2},
['IsMicroop'])
- iop3 = InstObjParams('deintrlv',
+ iop3 = ArmInstObjParams('deintrlv',
'SveDeIntrlv3Microop',
'MicroOp',
{'code': code3},
['IsMicroop'])
- iop4 = InstObjParams('deintrlv',
+ iop4 = ArmInstObjParams('deintrlv',
'SveDeIntrlv4Microop',
'MicroOp',
{'code': code4},
storeWrEnableCode = '''
auto wrEn = std::vector<bool>(sizeof(Element) * eCount, true);
'''
- loadIop = InstObjParams('ldxx',
+ loadIop = ArmInstObjParams('ldxx',
'SveLoadRegImmMicroop' if offsetIsImm else 'SveLoadRegRegMicroop',
'MicroOp',
{'targs': 'Element',
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
['IsLoad', 'IsMicroop'])
- storeIop = InstObjParams('stxx',
+ storeIop = ArmInstObjParams('stxx',
'SveStoreRegImmMicroop' if offsetIsImm
else 'SveStoreRegRegMicroop',
'MicroOp',
AA64FpDest_uq[i] = qword;
}
'''
- iop = InstObjParams('ld1rq',
+ iop = ArmInstObjParams('ld1rq',
'SveLd1RqSI' if offsetIsImm else 'SveLd1RqSS',
'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
{'tpl_header': tplHeader,
//
namespace ArmISA;
+##include "arminstobjparams.isa"
+
//Include the bitfield definitions
##include "bitfields.isa"
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
%(class_name)s::%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(class_name)s::%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BranchImmCondDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t _imm,
ConditionCode _condCode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _condCode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template BranchRegCondDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
ConditionCode _condCode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _condCode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template BranchTableDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2);
IntRegIndex _op1, IntRegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template BranchImmRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1);
IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
flags[IsCondControl] = true;
}
def template BranchImm64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm);
%(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BranchImmCond64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm,
ExtMachInst machInst, int64_t _imm, ConditionCode _condCode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _condCode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BranchReg64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BranchRegReg64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2);
IntRegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BranchImmReg64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t imm, IntRegIndex _op1);
IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BranchImmImmReg64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_imm1, _imm2, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataXImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataXSRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _shiftAmt, _shiftType)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataXERegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _extendType, _shiftAmt)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataX1RegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1);
IntRegIndex _dest, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataX2RegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataX2RegImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataX3RegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataXCondCompImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_op1, _imm, _condCode, _defCc)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataXCondCompRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_op1, _op2, _condCode, _defCc)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template DataXCondSelDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _condCode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MicroMemDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, bool _up,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _up, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MicroMemPairDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dreg1, _dreg2, _base, _up, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) :
%(op_class)s, _dest, _ura, _imm)
{
memAccessFlags |= extraMemFlags;
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MicroSetPCCPSRDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
IntRegIndex _ura,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _urc)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
flags[IsCondControl] = true;
template <class Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint8_t _step) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _step)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint8_t _step, unsigned _lane) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _step, _lane)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MicroIntMovDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb);
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MicroIntImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MicroIntRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _urc, _type, _shiftAmt)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MicroIntXERegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _urc, _shiftAmt, _shiftType)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex rn, bool index, bool up,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
index, up, user, writeback, load, reglist)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template BigFpMemImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) :
%(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BigFpMemRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
%(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base,
offset, type, imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template BigFpMemLitDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
IntRegIndex dest, int64_t imm) :
%(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template PairMemDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
fp, load, noAlloc, signExt, exclusive, acrel,
imm, mode, rn, rt, rt2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template VMemMultDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, unsigned width,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
rn, vd, regs, inc, size, align, rm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template VMemSingleDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
rn, vd, regs, inc, size, align, rm, lane)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
vd, single, up, writeback, load, offset)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb);
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _regMode, int _mode, bool _wb);
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base);
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _result, uint32_t _dest, uint32_t _dest2,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _result, uint32_t _dest, uint32_t _base,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_base, (AddrMode)_mode, _wb)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(OperatingMode)_regMode, (AddrMode)_mode, _wb)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
(IntRegIndex)_dest, (IntRegIndex)_dest2,
(IntRegIndex)_base, _add, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
(IntRegIndex)_result, (IntRegIndex)_dest, (IntRegIndex)_dest2,
(IntRegIndex)_base, _add, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
(IntRegIndex)_result, (IntRegIndex)_dest,
(IntRegIndex)_base, _add, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_shiftAmt, (ArmShiftType)_shiftType,
(IntRegIndex)_index)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_shiftAmt, (ArmShiftType)_shiftType,
(IntRegIndex)_index)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_shiftAmt, (ArmShiftType)_shiftType,
(IntRegIndex)_index)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_shiftAmt, (ArmShiftType)_shiftType,
(IntRegIndex)_index)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
M5_VAR_USED bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
M5_VAR_USED bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
def template DCStore64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _base,
MiscRegIndex _dest, uint64_t _imm);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_base, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
assert(!%(use_uops)d);
}
def template LoadStoreImm64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _base, int64_t _imm);
def template LoadStoreImmU64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _base, int64_t _imm,
def template LoadStoreImmDU64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
def template LoadStoreReg64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
def template LoadStoreRegU64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
def template LoadStoreRaw64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _base);
def template LoadStoreEx64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _base, IntRegIndex _result);
def template LoadStoreLit64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm);
def template LoadStoreLitU64Declare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm,
bool noAlloc = false, bool exclusive = false,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
#if %(use_uops)d
assert(numMicroops >= 2);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
assert(!%(use_uops)d);
setExcAcRel(exclusive, acrel);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _dest2, _base, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
assert(!%(use_uops)d);
setExcAcRel(exclusive, acrel);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_result, _dest, _dest2, _base, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
assert(!%(use_uops)d);
}
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _offset, _type, _shiftAmt)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
#if %(use_uops)d
assert(numMicroops >= 2);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _offset, _type, _shiftAmt)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
assert(!%(use_uops)d);
setExcAcRel(exclusive, acrel);
IntRegIndex _dest, IntRegIndex _base) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
#if %(use_uops)d
assert(numMicroops >= 2);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
assert(!%(use_uops)d);
setExcAcRel(exclusive, acrel);
def template AmoOpDeclare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _base, IntRegIndex _result);
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
flags[IsStore] = false;
flags[IsLoad] = false;
def template AmoPairOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
uint32_t d2_src ;
uint32_t r2_src ;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ;
def template AmoArithmeticOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
bool isXZR ;
/// Constructor.
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
isXZR = false;
uint32_t r2 = RegId(IntRegClass, dest).index() ;
def template MrsDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MrsBankedRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
uint8_t byteMask;
bool r;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest),
byteMask(_sysM), r(_r)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MsrBankedRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
bool r;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM),
r(_r)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MsrRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
uint8_t mask) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MsrImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
uint8_t mask) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MrrcOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest,
dest2, imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template McrrOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2,
dest, imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template ImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint64_t _imm);
%(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
IntRegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1);
IntRegIndex _dest, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MiscRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegMiscRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegImmImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm1, _imm2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegRegImmImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template RegImmRegShiftOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _op1, _shiftAmt, _shiftType)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template MiscRegRegImmMemOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
def template ImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,uint64_t _imm);
%(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template RegRegImmImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template RegRegRegImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MiscRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, uint64_t _imm);
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MiscRegRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template RegMiscRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
{
private:
bool data;
+ %(reg_idx_arr_decl)s;
public:
// Constructor
%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
+ %(set_reg_idx_arr)s;
data = bits(machInst, 10);
%(constructor)s;
}
def template RegNoneDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template Mult3Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_reg0, _reg1, _reg2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template Mult4Declare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_reg0, _reg1, _reg2, _reg3)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template MicroNeonMemDeclare64 {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
// True if the base register is SP (used for SP alignment checking)
bool baseIsSP;
_ura, _imm),
baseIsSP(_baseIsSP), accSize(_accSize), eSize(_eSize)
{
+ %(set_reg_idx_arr)s;
memAccessFlags |= extraMemFlags;
%(constructor)s;
}
def template VMemMultDeclare64 {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd,
def template VMemSingleDeclare64 {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd,
"%(mnemonic)s", machInst, %(op_class)s, rn, vd, rm,
_eSize, _dataSize, _numStructElems, _numRegs, _wb)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
_eSize, _dataSize, _numStructElems, _index, _wb,
_replicate)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MicroNeonMixDeclare64 {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint8_t _eSize, uint8_t _dataSize,
_dest, _op1, _eSize, _dataSize, _numStructElems,
_numRegs, _step)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template MicroNeonMixLaneDeclare64 {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint8_t _eSize, uint8_t _dataSize,
_dest, _op1, _eSize, _dataSize, _numStructElems,
_lane, _step, _replicate)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template DataImmDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, _rotC)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template DataRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _shiftAmt, _shiftType)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template DataRegRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _shift, _shiftType)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
%(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
// In AArch64 there is only one instruction for issuing
template <class _SElement, class _DElement>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _SElement Element;
typedef _SElement SElement;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, %(isSimdFp)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _gp, _isMerging)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op2, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, _predType)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _index)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, _isSel)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, %(op2IsWide)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _SElement, class _DElement>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _SElement Element;
typedef _SElement SElement;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class SveIndexII : public SveIndexIIOp
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
SveIndexIIOp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm1, _imm2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class SveIndexIR : public SveIndexIROp
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
SveIndexIROp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _op)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class SveIndexRI : public SveIndexRIOp
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
SveIndexRIOp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class SveIndexRR : public SveIndexRROp
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
SveIndexRROp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, %(srcIs32b)s, %(destIsVec)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _offset, _mult, _offsetFormat)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, %(srcIs32b)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1,
_op2, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_pattern, _imm, %(dstIsVec)s, %(dstIs32b)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
esize = sizeof(Element);
}
def template SvePartBrkOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _gp,
IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_gp, _op1, %(isMerging)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
// instantiating with uint8_t
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_op1, _op2, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_op1, _gp, %(isCond)s, %(isScalar)s, %(isSimdFp)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
scalar_width = (sizeof(Element) == 8) ? 64 : 32;
}
template <class _SElement, class _DElement>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _SElement Element;
typedef _SElement SElement;
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SvePredicateTestOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SvePredUnaryOpWImplicitSrcDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SvePredUnaryPredOpWImplicitSrcDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _gp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SvePredUnaryOpWImplicitDstDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SveOpWImplicitSrcDstDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _SElement, class _DElement>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _DElement Element;
typedef _SElement SElement;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
esize = sizeof(Element);
}
template <class _SElement, class _DElement>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _DElement Element;
typedef _SElement SElement;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
esize = sizeof(Element);
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, _rot)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _rot, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SveMemFillSpillOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef uint8_t TPElem;
typedef uint8_t RegElemType;
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
%(tpl_header)s
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef RegElemType TPElem;
%(base_class)s(mnem, machInst, %(op_class)s,
_dest, _gp, _base, _offset)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
%(tpl_header)s
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef RegElemType TPElem;
%(base_class)s(mnem, machInst, %(op_class)s,
_dest, _gp, _base, _imm)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
%(tpl_header)s
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef RegElemType TPElem;
firstFault(_firstFault),
memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (_opClass == MemReadOp && elemIndex == 0) {
// The first micro-op is responsible for pinning the
%(tpl_header)s
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef RegElemType TPElem;
numElems(_numElems), firstFault(_firstFault),
memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (_opClass == MemReadOp && elemIndex == 0) {
// The first micro-op is responsible for pinning the
StaticInst *macroOp;
public:
+ %(reg_idx_arr_decl)s;
+
SveFirstFaultWritebackMicroop(const char* mnem, ExtMachInst machInst,
OpClass __opClass, int _numElems, StaticInst *_macroOp) :
MicroOp(mnem, machInst, __opClass),
numElems(_numElems), macroOp(_macroOp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template SveGatherLoadCpySrcVecMicroopDeclare {{
class SveGatherLoadCpySrcVecMicroop : public MicroOp
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
IntRegIndex op1;
IntRegIndex _op1, StaticInst *_macroOp) :
MicroOp(mnem, machInst, SimdAluOp), op1(_op1), macroOp(_macroOp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template<class _Element>
class %(class_name)s : public %(base_class)s
{
+ public:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
numRegs(_numRegs), regIndex(_regIndex),
memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
baseIsSP = isSP(_base);
}
template <class _Element>
class %(class_name)s: public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
MicroOp(mnem, machInst, SimdAluOp), dest(_dest), op1(_op1),
numRegs(_numRegs), regIndex(_regIndex), macroOp(_macroOp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
template <class _Element>
class %(class_name)s : public %(base_class)s
{
+ public:
+ %(reg_idx_arr_decl)s;
+
protected:
typedef _Element Element;
typedef _Element TPElem;
MicroOp(mnem, machInst, SimdAluOp), dest(_dest),
numRegs(_numRegs), regIndex(_regIndex), macroOp(_macroOp)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
def template FpRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template FpRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template FpRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template FpRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
def template FpRegRegRegCondOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _cond, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template AA64FpRegRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3, mode)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
projects / gem5.git / commitdiff