i965/gen9: Allow fast clear for MSRT formats matching render

Previously fast clear was disallowed on Gen9 for MSRTs with the claim
that some formats don't work but we didn't understand why. On further
investigation it seems the formats that don't work are the ones where
the render surface format is being overriden to a different format
than the one used for texturing. The one used for texturing is not
actually a renderable format. It arguably makes sense that the sampler
hardware doesn't handle the fast color correctly in these cases
because it shouldn't be possible to end up with a fast cleared surface
that is non-renderable.

This patch changes the limitation to prevent fast clear for surfaces
where the format for rendering is overriden.

Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index f1920b2edce40d19e076c25ab734163e57976d07..cf0e56b52441abc1c26e3d89ee064e4839be02f4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -50,6 +50,7 @@
 #include "brw_defines.h"
 #include "brw_context.h"
 #include "brw_draw.h"
+#include "brw_state.h"
 #include "intel_fbo.h"
 #include "intel_batchbuffer.h"
 
@@ -573,11 +574,17 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
       if (brw->gen < 7)
          clear_type = REP_CLEAR;
 
-      /* Certain formats have unresolved issues with sampling from the MCS
-       * buffer on Gen9. This disables fast clears altogether for MSRTs until
-       * we can figure out what's going on.
+      /* If we're mapping the render format to a different format than the
+       * format we use for texturing then it is a bit questionable whether it
+       * should be possible to use a fast clear. Although we only actually
+       * render using a renderable format, without the override workaround it
+       * wouldn't be possible to have a non-renderable surface in a fast clear
+       * state so the hardware probably legitimately doesn't need to support
+       * this case. At least on Gen9 this really does seem to cause problems.
        */
-      if (brw->gen >= 9 && irb->mt->num_samples > 1)
+      if (brw->gen >= 9 &&
+          brw_format_for_mesa_format(irb->mt->format) !=
+          brw->render_target_format[irb->mt->format])
          clear_type = REP_CLEAR;
 
       if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS)