Committed on behalf of Sudi Das

2017-10-06  Sudakshina Das  <sudi.das@arm.com>

	PR target/82440
	* config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Only call
	aarch64_simd_valid_immediate on CONST_VECTORs.
	(aarch64_reg_or_bic_imm): Likewise.

*** gcc/testsuite/ChangeLog ***

2017-10-06  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/bic_imm_1.c: New test.
	* gcc.target/aarch64/orr_imm_1.c: Likewise.

From-SVN: r253490

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f7c9967394bb26f836b5feb571d137809b13b20b..ecc6e5ba0c9760ce8bb9eb427f7ad5092bc016a0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2017-10-06  Sudakshina Das  <sudi.das@arm.com>
+
+       PR target/82440
+       * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Only call
+       aarch64_simd_valid_immediate on CONST_VECTORs.
+       (aarch64_reg_or_bic_imm): Likewise.
+
 2017-10-06  Wilco Dijkstra  <wdijkstr@arm.com>
 
        PR rtl-optimization/82396

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 887a13ee4f1be504317c0857d8ad135523cbaec0..bf23b88cb596a6374250e2bba08fc58ea420e5c0 100644 (file)
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -71,13 +71,15 @@
 
 (define_predicate "aarch64_reg_or_orr_imm"
    (ior (match_operand 0 "register_operand")
-       (match_test "aarch64_simd_valid_immediate (op, mode, false,
-                                                  NULL, AARCH64_CHECK_ORR)")))
+       (and (match_code "const_vector")
+            (match_test "aarch64_simd_valid_immediate (op, mode, false,
+                                               NULL, AARCH64_CHECK_ORR)"))))
 
 (define_predicate "aarch64_reg_or_bic_imm"
    (ior (match_operand 0 "register_operand")
-       (match_test "aarch64_simd_valid_immediate (op, mode, false,
-                                                  NULL, AARCH64_CHECK_BIC)")))
+       (and (match_code "const_vector")
+            (match_test "aarch64_simd_valid_immediate (op, mode, false,
+                                               NULL, AARCH64_CHECK_BIC)"))))
 
 (define_predicate "aarch64_fp_compare_operand"
   (ior (match_operand 0 "register_operand")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c25c0189fc19bbee7e95ff3cc5db63b65fb30e7f..2e6ca4f4bb62efbae565e8ec7d1f65286530dcf4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-10-06  Sudakshina Das  <sudi.das@arm.com>
+
+       * gcc.target/aarch64/bic_imm_1.c: New test.
+       * gcc.target/aarch64/orr_imm_1.c: Likewise.
+
 2017-10-06  Paolo Carlini  <paolo.carlini@oracle.com>
 
        PR c++/60153

diff --git a/gcc/testsuite/gcc.target/aarch64/bic_imm_1.c b/gcc/testsuite/gcc.target/aarch64/bic_imm_1.c
new file mode 100644 (file)
index 0000000..b14f009
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/bic_imm_1.c
@@ -0,0 +1,56 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps -ftree-vectorize" } */
+
+/* Each function uses the correspoding 'CLASS' in
+   Marco CHECK (aarch64_simd_valid_immediate).  */
+
+void
+bic_6 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] &= ~(0xab);
+}
+
+void
+bic_7 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] &= ~(0xcd00);
+}
+
+void
+bic_8 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] &= ~(0xef0000);
+}
+
+void
+bic_9 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] &= ~(0x12000000);
+}
+
+void
+bic_10 (short *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] &= ~(0x34);
+}
+
+
+void
+bic_11 (short *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] &= ~(0x5600);
+}
+
+
+/* { dg-final { scan-assembler "bic\\tv\[0-9\]+.4s, #171" } } */
+/* { dg-final { scan-assembler "bic\\tv\[0-9\]+.4s, #205, lsl #8" } } */
+/* { dg-final { scan-assembler "bic\\tv\[0-9\]+.4s, #239, lsl #16" } } */
+/* { dg-final { scan-assembler "bic\\tv\[0-9\]+.4s, #18, lsl #24" } } */
+/* { dg-final { scan-assembler "bic\\tv\[0-9\]+.8h, #52" } } */
+/* { dg-final { scan-assembler "bic\\tv\[0-9\]+.8h, #86, lsl #8" } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/orr_imm_1.c b/gcc/testsuite/gcc.target/aarch64/orr_imm_1.c
new file mode 100644 (file)
index 0000000..ff6f683
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/orr_imm_1.c
@@ -0,0 +1,54 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps -ftree-vectorize" } */
+
+/* Each function uses the correspoding 'CLASS' in
+   Marco CHECK (aarch64_simd_valid_immediate).  */
+
+void
+orr_0 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] |= 0xab;
+}
+
+void
+orr_1 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] |= 0x0000cd00;
+}
+
+void
+orr_2 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] |= 0x00ef0000;
+}
+
+void
+orr_3 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] |= 0x12000000;
+}
+
+void
+orr_4 (short *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] |= 0x00340034;
+}
+
+void
+orr_5 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] |= 0x56005600;
+}
+
+/* { dg-final { scan-assembler "orr\\tv\[0-9\]+.4s, #171" } } */
+/* { dg-final { scan-assembler "orr\\tv\[0-9\]+.4s, #205, lsl #8" } } */
+/* { dg-final { scan-assembler "orr\\tv\[0-9\]+.4s, #239, lsl #16" } } */
+/* { dg-final { scan-assembler "orr\\tv\[0-9\]+.4s, #18, lsl #24" } } */
+/* { dg-final { scan-assembler "orr\\tv\[0-9\]+.8h, #52" } } */
+/* { dg-final { scan-assembler "orr\\tv\[0-9\]+.8h, #86, lsl #8" } } */