radeonsi: remove duplicated register definitions and instruction definitions
authorMarek Olšák <marek.olsak@amd.com>
Sat, 15 Aug 2015 16:48:06 +0000 (18:48 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 26 Aug 2015 17:25:19 +0000 (19:25 +0200)
Instruction encoding isn't needed in Mesa.

The border color address registers were duplicated.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
src/gallium/drivers/radeonsi/sid.h

index 05d20dbf10f7135657b6e23a3130d711e7b75414..66660e328242f88241a349c39292bd302c0ebcad 100644 (file)
 #define   S_008C0C_RNG(x)                                             (((x) & 0x7FF) << 10)
 #define   G_008C0C_RNG(x)                                             (((x) >> 10) & 0x7FF)
 #define   C_008C0C_RNG                                                0xFFE003FF
-#if 0
-/* CIK */
-#define R_008DFC_SQ_FLAT_1                                              0x008DFC
-#define   S_008DFC_ADDR(x)                                            (((x) & 0xFF) << 0)
-#define   G_008DFC_ADDR(x)                                            (((x) >> 0) & 0xFF)
-#define   C_008DFC_ADDR                                               0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_DATA(x)                                            (((x) & 0xFF) << 8)
-#define   G_008DFC_DATA(x)                                            (((x) >> 8) & 0xFF)
-#define   C_008DFC_DATA                                               0xFFFF00FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 23)
-#define   G_008DFC_TFE(x)                                             (((x) >> 23) & 0x1)
-#define   C_008DFC_TFE                                                0xFF7FFFFF
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 24)
-#define   G_008DFC_VDST(x)                                            (((x) >> 24) & 0xFF)
-#define   C_008DFC_VDST                                               0x00FFFFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-/*     */
-#define R_008DFC_SQ_INST                                                0x008DFC
-#define R_030D20_SQC_CACHES                                             0x030D20
-#define   S_030D20_TARGET_INST(x)                                     (((x) & 0x1) << 0)
-#define   G_030D20_TARGET_INST(x)                                     (((x) >> 0) & 0x1)
-#define   C_030D20_TARGET_INST                                        0xFFFFFFFE
-#define   S_030D20_TARGET_DATA(x)                                     (((x) & 0x1) << 1)
-#define   G_030D20_TARGET_DATA(x)                                     (((x) >> 1) & 0x1)
-#define   C_030D20_TARGET_DATA                                        0xFFFFFFFD
-#define   S_030D20_INVALIDATE(x)                                      (((x) & 0x1) << 2)
-#define   G_030D20_INVALIDATE(x)                                      (((x) >> 2) & 0x1)
-#define   C_030D20_INVALIDATE                                         0xFFFFFFFB
-#define   S_030D20_WRITEBACK(x)                                       (((x) & 0x1) << 3)
-#define   G_030D20_WRITEBACK(x)                                       (((x) >> 3) & 0x1)
-#define   C_030D20_WRITEBACK                                          0xFFFFFFF7
-#define   S_030D20_VOL(x)                                             (((x) & 0x1) << 4)
-#define   G_030D20_VOL(x)                                             (((x) >> 4) & 0x1)
-#define   C_030D20_VOL                                                0xFFFFFFEF
-#define   S_030D20_COMPLETE(x)                                        (((x) & 0x1) << 16)
-#define   G_030D20_COMPLETE(x)                                        (((x) >> 16) & 0x1)
-#define   C_030D20_COMPLETE                                           0xFFFEFFFF
-#define R_030D24_SQC_WRITEBACK                                          0x030D24
-#define   S_030D24_DWB(x)                                             (((x) & 0x1) << 0)
-#define   G_030D24_DWB(x)                                             (((x) >> 0) & 0x1)
-#define   C_030D24_DWB                                                0xFFFFFFFE
-#define   S_030D24_DIRTY(x)                                           (((x) & 0x1) << 1)
-#define   G_030D24_DIRTY(x)                                           (((x) >> 1) & 0x1)
-#define   C_030D24_DIRTY                                              0xFFFFFFFD
-#define R_008DFC_SQ_VOP1                                                0x008DFC
-#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
-#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
-#define   C_008DFC_SRC0                                               0xFFFFFE00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define     V_008DFC_SQ_SRC_VGPR                                    0x100
-#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 9)
-#define   G_008DFC_OP(x)                                              (((x) >> 9) & 0xFF)
-#define   C_008DFC_OP                                                 0xFFFE01FF
-#define     V_008DFC_SQ_V_NOP                                       0x00
-#define     V_008DFC_SQ_V_MOV_B32                                   0x01
-#define     V_008DFC_SQ_V_READFIRSTLANE_B32                         0x02
-#define     V_008DFC_SQ_V_CVT_I32_F64                               0x03
-#define     V_008DFC_SQ_V_CVT_F64_I32                               0x04
-#define     V_008DFC_SQ_V_CVT_F32_I32                               0x05
-#define     V_008DFC_SQ_V_CVT_F32_U32                               0x06
-#define     V_008DFC_SQ_V_CVT_U32_F32                               0x07
-#define     V_008DFC_SQ_V_CVT_I32_F32                               0x08
-#define     V_008DFC_SQ_V_MOV_FED_B32                               0x09
-#define     V_008DFC_SQ_V_CVT_F16_F32                               0x0A
-#define     V_008DFC_SQ_V_CVT_F32_F16                               0x0B
-#define     V_008DFC_SQ_V_CVT_RPI_I32_F32                           0x0C
-#define     V_008DFC_SQ_V_CVT_FLR_I32_F32                           0x0D
-#define     V_008DFC_SQ_V_CVT_OFF_F32_I4                            0x0E
-#define     V_008DFC_SQ_V_CVT_F32_F64                               0x0F
-#define     V_008DFC_SQ_V_CVT_F64_F32                               0x10
-#define     V_008DFC_SQ_V_CVT_F32_UBYTE0                            0x11
-#define     V_008DFC_SQ_V_CVT_F32_UBYTE1                            0x12
-#define     V_008DFC_SQ_V_CVT_F32_UBYTE2                            0x13
-#define     V_008DFC_SQ_V_CVT_F32_UBYTE3                            0x14
-#define     V_008DFC_SQ_V_CVT_U32_F64                               0x15
-#define     V_008DFC_SQ_V_CVT_F64_U32                               0x16
-/* CIK */
-#define     V_008DFC_SQ_V_TRUNC_F64                                 0x17
-#define     V_008DFC_SQ_V_CEIL_F64                                  0x18
-#define     V_008DFC_SQ_V_RNDNE_F64                                 0x19
-#define     V_008DFC_SQ_V_FLOOR_F64                                 0x1A
-/*     */
-#define     V_008DFC_SQ_V_FRACT_F32                                 0x20
-#define     V_008DFC_SQ_V_TRUNC_F32                                 0x21
-#define     V_008DFC_SQ_V_CEIL_F32                                  0x22
-#define     V_008DFC_SQ_V_RNDNE_F32                                 0x23
-#define     V_008DFC_SQ_V_FLOOR_F32                                 0x24
-#define     V_008DFC_SQ_V_EXP_F32                                   0x25
-#define     V_008DFC_SQ_V_LOG_CLAMP_F32                             0x26
-#define     V_008DFC_SQ_V_LOG_F32                                   0x27
-#define     V_008DFC_SQ_V_RCP_CLAMP_F32                             0x28
-#define     V_008DFC_SQ_V_RCP_LEGACY_F32                            0x29
-#define     V_008DFC_SQ_V_RCP_F32                                   0x2A
-#define     V_008DFC_SQ_V_RCP_IFLAG_F32                             0x2B
-#define     V_008DFC_SQ_V_RSQ_CLAMP_F32                             0x2C
-#define     V_008DFC_SQ_V_RSQ_LEGACY_F32                            0x2D
-#define     V_008DFC_SQ_V_RSQ_F32                                   0x2E
-#define     V_008DFC_SQ_V_RCP_F64                                   0x2F
-#define     V_008DFC_SQ_V_RCP_CLAMP_F64                             0x30
-#define     V_008DFC_SQ_V_RSQ_F64                                   0x31
-#define     V_008DFC_SQ_V_RSQ_CLAMP_F64                             0x32
-#define     V_008DFC_SQ_V_SQRT_F32                                  0x33
-#define     V_008DFC_SQ_V_SQRT_F64                                  0x34
-#define     V_008DFC_SQ_V_SIN_F32                                   0x35
-#define     V_008DFC_SQ_V_COS_F32                                   0x36
-#define     V_008DFC_SQ_V_NOT_B32                                   0x37
-#define     V_008DFC_SQ_V_BFREV_B32                                 0x38
-#define     V_008DFC_SQ_V_FFBH_U32                                  0x39
-#define     V_008DFC_SQ_V_FFBL_B32                                  0x3A
-#define     V_008DFC_SQ_V_FFBH_I32                                  0x3B
-#define     V_008DFC_SQ_V_FREXP_EXP_I32_F64                         0x3C
-#define     V_008DFC_SQ_V_FREXP_MANT_F64                            0x3D
-#define     V_008DFC_SQ_V_FRACT_F64                                 0x3E
-#define     V_008DFC_SQ_V_FREXP_EXP_I32_F32                         0x3F
-#define     V_008DFC_SQ_V_FREXP_MANT_F32                            0x40
-#define     V_008DFC_SQ_V_CLREXCP                                   0x41
-#define     V_008DFC_SQ_V_MOVRELD_B32                               0x42
-#define     V_008DFC_SQ_V_MOVRELS_B32                               0x43
-#define     V_008DFC_SQ_V_MOVRELSD_B32                              0x44
-/* CIK */
-#define     V_008DFC_SQ_V_LOG_LEGACY_F32                            0x45
-#define     V_008DFC_SQ_V_EXP_LEGACY_F32                            0x46
-/*     */
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 17)
-#define   G_008DFC_VDST(x)                                            (((x) >> 17) & 0xFF)
-#define   C_008DFC_VDST                                               0xFE01FFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x7F) << 25)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 25) & 0x7F)
-#define   C_008DFC_ENCODING                                           0x01FFFFFF
-#define     V_008DFC_SQ_ENC_VOP1_FIELD                              0x3F
-#define R_008DFC_SQ_MIMG_1                                              0x008DFC
-#define   S_008DFC_VADDR(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_VADDR(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_VADDR                                              0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VDATA(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_VDATA(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_VDATA                                              0xFFFF00FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_SRSRC(x)                                           (((x) & 0x1F) << 16)
-#define   G_008DFC_SRSRC(x)                                           (((x) >> 16) & 0x1F)
-#define   C_008DFC_SRSRC                                              0xFFE0FFFF
-#define   S_008DFC_SSAMP(x)                                           (((x) & 0x1F) << 21)
-#define   G_008DFC_SSAMP(x)                                           (((x) >> 21) & 0x1F)
-#define   C_008DFC_SSAMP                                              0xFC1FFFFF
-#define R_008DFC_SQ_VOP3_1                                              0x008DFC
-#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
-#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
-#define   C_008DFC_SRC0                                               0xFFFFFE00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define     V_008DFC_SQ_SRC_VGPR                                    0x100
-#define   S_008DFC_SRC1(x)                                            (((x) & 0x1FF) << 9)
-#define   G_008DFC_SRC1(x)                                            (((x) >> 9) & 0x1FF)
-#define   C_008DFC_SRC1                                               0xFFFC01FF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define     V_008DFC_SQ_SRC_VGPR                                    0x100
-#define   S_008DFC_SRC2(x)                                            (((x) & 0x1FF) << 18)
-#define   G_008DFC_SRC2(x)                                            (((x) >> 18) & 0x1FF)
-#define   C_008DFC_SRC2                                               0xF803FFFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define     V_008DFC_SQ_SRC_VGPR                                    0x100
-#define   S_008DFC_OMOD(x)                                            (((x) & 0x03) << 27)
-#define   G_008DFC_OMOD(x)                                            (((x) >> 27) & 0x03)
-#define   C_008DFC_OMOD                                               0xE7FFFFFF
-#define     V_008DFC_SQ_OMOD_OFF                                    0x00
-#define     V_008DFC_SQ_OMOD_M2                                     0x01
-#define     V_008DFC_SQ_OMOD_M4                                     0x02
-#define     V_008DFC_SQ_OMOD_D2                                     0x03
-#define   S_008DFC_NEG(x)                                             (((x) & 0x07) << 29)
-#define   G_008DFC_NEG(x)                                             (((x) >> 29) & 0x07)
-#define   C_008DFC_NEG                                                0x1FFFFFFF
-#define R_008DFC_SQ_MUBUF_1                                             0x008DFC
-#define   S_008DFC_VADDR(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_VADDR(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_VADDR                                              0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VDATA(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_VDATA(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_VDATA                                              0xFFFF00FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_SRSRC(x)                                           (((x) & 0x1F) << 16)
-#define   G_008DFC_SRSRC(x)                                           (((x) >> 16) & 0x1F)
-#define   C_008DFC_SRSRC                                              0xFFE0FFFF
-#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 22)
-#define   G_008DFC_SLC(x)                                             (((x) >> 22) & 0x1)
-#define   C_008DFC_SLC                                                0xFFBFFFFF
-#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 23)
-#define   G_008DFC_TFE(x)                                             (((x) >> 23) & 0x1)
-#define   C_008DFC_TFE                                                0xFF7FFFFF
-#define   S_008DFC_SOFFSET(x)                                         (((x) & 0xFF) << 24)
-#define   G_008DFC_SOFFSET(x)                                         (((x) >> 24) & 0xFF)
-#define   C_008DFC_SOFFSET                                            0x00FFFFFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define R_008DFC_SQ_DS_0                                                0x008DFC
-#define   S_008DFC_OFFSET0(x)                                         (((x) & 0xFF) << 0)
-#define   G_008DFC_OFFSET0(x)                                         (((x) >> 0) & 0xFF)
-#define   C_008DFC_OFFSET0                                            0xFFFFFF00
-#define   S_008DFC_OFFSET1(x)                                         (((x) & 0xFF) << 8)
-#define   G_008DFC_OFFSET1(x)                                         (((x) >> 8) & 0xFF)
-#define   C_008DFC_OFFSET1                                            0xFFFF00FF
-#define   S_008DFC_GDS(x)                                             (((x) & 0x1) << 17)
-#define   G_008DFC_GDS(x)                                             (((x) >> 17) & 0x1)
-#define   C_008DFC_GDS                                                0xFFFDFFFF
-#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 18)
-#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0xFF)
-#define   C_008DFC_OP                                                 0xFC03FFFF
-#define     V_008DFC_SQ_DS_ADD_U32                                  0x00
-#define     V_008DFC_SQ_DS_SUB_U32                                  0x01
-#define     V_008DFC_SQ_DS_RSUB_U32                                 0x02
-#define     V_008DFC_SQ_DS_INC_U32                                  0x03
-#define     V_008DFC_SQ_DS_DEC_U32                                  0x04
-#define     V_008DFC_SQ_DS_MIN_I32                                  0x05
-#define     V_008DFC_SQ_DS_MAX_I32                                  0x06
-#define     V_008DFC_SQ_DS_MIN_U32                                  0x07
-#define     V_008DFC_SQ_DS_MAX_U32                                  0x08
-#define     V_008DFC_SQ_DS_AND_B32                                  0x09
-#define     V_008DFC_SQ_DS_OR_B32                                   0x0A
-#define     V_008DFC_SQ_DS_XOR_B32                                  0x0B
-#define     V_008DFC_SQ_DS_MSKOR_B32                                0x0C
-#define     V_008DFC_SQ_DS_WRITE_B32                                0x0D
-#define     V_008DFC_SQ_DS_WRITE2_B32                               0x0E
-#define     V_008DFC_SQ_DS_WRITE2ST64_B32                           0x0F
-#define     V_008DFC_SQ_DS_CMPST_B32                                0x10
-#define     V_008DFC_SQ_DS_CMPST_F32                                0x11
-#define     V_008DFC_SQ_DS_MIN_F32                                  0x12
-#define     V_008DFC_SQ_DS_MAX_F32                                  0x13
-/* CIK */
-#define     V_008DFC_SQ_DS_NOP                                      0x14
-/*     */
-#define     V_008DFC_SQ_DS_GWS_INIT                                 0x19
-#define     V_008DFC_SQ_DS_GWS_SEMA_V                               0x1A
-#define     V_008DFC_SQ_DS_GWS_SEMA_BR                              0x1B
-#define     V_008DFC_SQ_DS_GWS_SEMA_P                               0x1C
-#define     V_008DFC_SQ_DS_GWS_BARRIER                              0x1D
-#define     V_008DFC_SQ_DS_WRITE_B8                                 0x1E
-#define     V_008DFC_SQ_DS_WRITE_B16                                0x1F
-#define     V_008DFC_SQ_DS_ADD_RTN_U32                              0x20
-#define     V_008DFC_SQ_DS_SUB_RTN_U32                              0x21
-#define     V_008DFC_SQ_DS_RSUB_RTN_U32                             0x22
-#define     V_008DFC_SQ_DS_INC_RTN_U32                              0x23
-#define     V_008DFC_SQ_DS_DEC_RTN_U32                              0x24
-#define     V_008DFC_SQ_DS_MIN_RTN_I32                              0x25
-#define     V_008DFC_SQ_DS_MAX_RTN_I32                              0x26
-#define     V_008DFC_SQ_DS_MIN_RTN_U32                              0x27
-#define     V_008DFC_SQ_DS_MAX_RTN_U32                              0x28
-#define     V_008DFC_SQ_DS_AND_RTN_B32                              0x29
-#define     V_008DFC_SQ_DS_OR_RTN_B32                               0x2A
-#define     V_008DFC_SQ_DS_XOR_RTN_B32                              0x2B
-#define     V_008DFC_SQ_DS_MSKOR_RTN_B32                            0x2C
-#define     V_008DFC_SQ_DS_WRXCHG_RTN_B32                           0x2D
-#define     V_008DFC_SQ_DS_WRXCHG2_RTN_B32                          0x2E
-#define     V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32                      0x2F
-#define     V_008DFC_SQ_DS_CMPST_RTN_B32                            0x30
-#define     V_008DFC_SQ_DS_CMPST_RTN_F32                            0x31
-#define     V_008DFC_SQ_DS_MIN_RTN_F32                              0x32
-#define     V_008DFC_SQ_DS_MAX_RTN_F32                              0x33
-#define     V_008DFC_SQ_DS_SWIZZLE_B32                              0x35
-#define     V_008DFC_SQ_DS_READ_B32                                 0x36
-#define     V_008DFC_SQ_DS_READ2_B32                                0x37
-#define     V_008DFC_SQ_DS_READ2ST64_B32                            0x38
-#define     V_008DFC_SQ_DS_READ_I8                                  0x39
-#define     V_008DFC_SQ_DS_READ_U8                                  0x3A
-#define     V_008DFC_SQ_DS_READ_I16                                 0x3B
-#define     V_008DFC_SQ_DS_READ_U16                                 0x3C
-#define     V_008DFC_SQ_DS_CONSUME                                  0x3D
-#define     V_008DFC_SQ_DS_APPEND                                   0x3E
-#define     V_008DFC_SQ_DS_ORDERED_COUNT                            0x3F
-#define     V_008DFC_SQ_DS_ADD_U64                                  0x40
-#define     V_008DFC_SQ_DS_SUB_U64                                  0x41
-#define     V_008DFC_SQ_DS_RSUB_U64                                 0x42
-#define     V_008DFC_SQ_DS_INC_U64                                  0x43
-#define     V_008DFC_SQ_DS_DEC_U64                                  0x44
-#define     V_008DFC_SQ_DS_MIN_I64                                  0x45
-#define     V_008DFC_SQ_DS_MAX_I64                                  0x46
-#define     V_008DFC_SQ_DS_MIN_U64                                  0x47
-#define     V_008DFC_SQ_DS_MAX_U64                                  0x48
-#define     V_008DFC_SQ_DS_AND_B64                                  0x49
-#define     V_008DFC_SQ_DS_OR_B64                                   0x4A
-#define     V_008DFC_SQ_DS_XOR_B64                                  0x4B
-#define     V_008DFC_SQ_DS_MSKOR_B64                                0x4C
-#define     V_008DFC_SQ_DS_WRITE_B64                                0x4D
-#define     V_008DFC_SQ_DS_WRITE2_B64                               0x4E
-#define     V_008DFC_SQ_DS_WRITE2ST64_B64                           0x4F
-#define     V_008DFC_SQ_DS_CMPST_B64                                0x50
-#define     V_008DFC_SQ_DS_CMPST_F64                                0x51
-#define     V_008DFC_SQ_DS_MIN_F64                                  0x52
-#define     V_008DFC_SQ_DS_MAX_F64                                  0x53
-#define     V_008DFC_SQ_DS_ADD_RTN_U64                              0x60
-#define     V_008DFC_SQ_DS_SUB_RTN_U64                              0x61
-#define     V_008DFC_SQ_DS_RSUB_RTN_U64                             0x62
-#define     V_008DFC_SQ_DS_INC_RTN_U64                              0x63
-#define     V_008DFC_SQ_DS_DEC_RTN_U64                              0x64
-#define     V_008DFC_SQ_DS_MIN_RTN_I64                              0x65
-#define     V_008DFC_SQ_DS_MAX_RTN_I64                              0x66
-#define     V_008DFC_SQ_DS_MIN_RTN_U64                              0x67
-#define     V_008DFC_SQ_DS_MAX_RTN_U64                              0x68
-#define     V_008DFC_SQ_DS_AND_RTN_B64                              0x69
-#define     V_008DFC_SQ_DS_OR_RTN_B64                               0x6A
-#define     V_008DFC_SQ_DS_XOR_RTN_B64                              0x6B
-#define     V_008DFC_SQ_DS_MSKOR_RTN_B64                            0x6C
-#define     V_008DFC_SQ_DS_WRXCHG_RTN_B64                           0x6D
-#define     V_008DFC_SQ_DS_WRXCHG2_RTN_B64                          0x6E
-#define     V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64                      0x6F
-#define     V_008DFC_SQ_DS_CMPST_RTN_B64                            0x70
-#define     V_008DFC_SQ_DS_CMPST_RTN_F64                            0x71
-#define     V_008DFC_SQ_DS_MIN_RTN_F64                              0x72
-#define     V_008DFC_SQ_DS_MAX_RTN_F64                              0x73
-#define     V_008DFC_SQ_DS_READ_B64                                 0x76
-#define     V_008DFC_SQ_DS_READ2_B64                                0x77
-#define     V_008DFC_SQ_DS_READ2ST64_B64                            0x78
-/* CIK */
-#define     V_008DFC_SQ_DS_CONDXCHG32_RTN_B64                       0x7E
-/*     */
-#define     V_008DFC_SQ_DS_ADD_SRC2_U32                             0x80
-#define     V_008DFC_SQ_DS_SUB_SRC2_U32                             0x81
-#define     V_008DFC_SQ_DS_RSUB_SRC2_U32                            0x82
-#define     V_008DFC_SQ_DS_INC_SRC2_U32                             0x83
-#define     V_008DFC_SQ_DS_DEC_SRC2_U32                             0x84
-#define     V_008DFC_SQ_DS_MIN_SRC2_I32                             0x85
-#define     V_008DFC_SQ_DS_MAX_SRC2_I32                             0x86
-#define     V_008DFC_SQ_DS_MIN_SRC2_U32                             0x87
-#define     V_008DFC_SQ_DS_MAX_SRC2_U32                             0x88
-#define     V_008DFC_SQ_DS_AND_SRC2_B32                             0x89
-#define     V_008DFC_SQ_DS_OR_SRC2_B32                              0x8A
-#define     V_008DFC_SQ_DS_XOR_SRC2_B32                             0x8B
-#define     V_008DFC_SQ_DS_WRITE_SRC2_B32                           0x8D
-#define     V_008DFC_SQ_DS_MIN_SRC2_F32                             0x92
-#define     V_008DFC_SQ_DS_MAX_SRC2_F32                             0x93
-#define     V_008DFC_SQ_DS_ADD_SRC2_U64                             0xC0
-#define     V_008DFC_SQ_DS_SUB_SRC2_U64                             0xC1
-#define     V_008DFC_SQ_DS_RSUB_SRC2_U64                            0xC2
-#define     V_008DFC_SQ_DS_INC_SRC2_U64                             0xC3
-#define     V_008DFC_SQ_DS_DEC_SRC2_U64                             0xC4
-#define     V_008DFC_SQ_DS_MIN_SRC2_I64                             0xC5
-#define     V_008DFC_SQ_DS_MAX_SRC2_I64                             0xC6
-#define     V_008DFC_SQ_DS_MIN_SRC2_U64                             0xC7
-#define     V_008DFC_SQ_DS_MAX_SRC2_U64                             0xC8
-#define     V_008DFC_SQ_DS_AND_SRC2_B64                             0xC9
-#define     V_008DFC_SQ_DS_OR_SRC2_B64                              0xCA
-#define     V_008DFC_SQ_DS_XOR_SRC2_B64                             0xCB
-#define     V_008DFC_SQ_DS_WRITE_SRC2_B64                           0xCD
-#define     V_008DFC_SQ_DS_MIN_SRC2_F64                             0xD2
-#define     V_008DFC_SQ_DS_MAX_SRC2_F64                             0xD3
-/* CIK */
-#define     V_008DFC_SQ_DS_WRITE_B96                                0xDE
-#define     V_008DFC_SQ_DS_WRITE_B128                               0xDF
-#define     V_008DFC_SQ_DS_CONDXCHG32_RTN_B128                      0xFD
-#define     V_008DFC_SQ_DS_READ_B96                                 0xFE
-#define     V_008DFC_SQ_DS_READ_B128                                0xFF
-/*     */
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_DS_FIELD                                0x36
-#define R_008DFC_SQ_SOPC                                                0x008DFC
-#define   S_008DFC_SSRC0(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_SSRC0(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_SSRC0                                              0xFFFFFF00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define   S_008DFC_SSRC1(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_SSRC1(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_SSRC1                                              0xFFFF00FF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 16)
-#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x7F)
-#define   C_008DFC_OP                                                 0xFF80FFFF
-#define     V_008DFC_SQ_S_CMP_EQ_I32                                0x00
-#define     V_008DFC_SQ_S_CMP_LG_I32                                0x01
-#define     V_008DFC_SQ_S_CMP_GT_I32                                0x02
-#define     V_008DFC_SQ_S_CMP_GE_I32                                0x03
-#define     V_008DFC_SQ_S_CMP_LT_I32                                0x04
-#define     V_008DFC_SQ_S_CMP_LE_I32                                0x05
-#define     V_008DFC_SQ_S_CMP_EQ_U32                                0x06
-#define     V_008DFC_SQ_S_CMP_LG_U32                                0x07
-#define     V_008DFC_SQ_S_CMP_GT_U32                                0x08
-#define     V_008DFC_SQ_S_CMP_GE_U32                                0x09
-#define     V_008DFC_SQ_S_CMP_LT_U32                                0x0A
-#define     V_008DFC_SQ_S_CMP_LE_U32                                0x0B
-#define     V_008DFC_SQ_S_BITCMP0_B32                               0x0C
-#define     V_008DFC_SQ_S_BITCMP1_B32                               0x0D
-#define     V_008DFC_SQ_S_BITCMP0_B64                               0x0E
-#define     V_008DFC_SQ_S_BITCMP1_B64                               0x0F
-#define     V_008DFC_SQ_S_SETVSKIP                                  0x10
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1FF) << 23)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 23) & 0x1FF)
-#define   C_008DFC_ENCODING                                           0x007FFFFF
-#define     V_008DFC_SQ_ENC_SOPC_FIELD                              0x17E
-#endif
 #define R_008DFC_SQ_EXP_0                                               0x008DFC
 #define   S_008DFC_EN(x)                                              (((x) & 0x0F) << 0)
 #define   G_008DFC_EN(x)                                              (((x) >> 0) & 0x0F)
 #define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
 #define   C_008DFC_ENCODING                                           0x03FFFFFF
 #define     V_008DFC_SQ_ENC_EXP_FIELD                               0x3E
-#if 0
-#define R_008DFC_SQ_MIMG_0                                              0x008DFC
-#define   S_008DFC_DMASK(x)                                           (((x) & 0x0F) << 8)
-#define   G_008DFC_DMASK(x)                                           (((x) >> 8) & 0x0F)
-#define   C_008DFC_DMASK                                              0xFFFFF0FF
-#define   S_008DFC_UNORM(x)                                           (((x) & 0x1) << 12)
-#define   G_008DFC_UNORM(x)                                           (((x) >> 12) & 0x1)
-#define   C_008DFC_UNORM                                              0xFFFFEFFF
-#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 13)
-#define   G_008DFC_GLC(x)                                             (((x) >> 13) & 0x1)
-#define   C_008DFC_GLC                                                0xFFFFDFFF
-#define   S_008DFC_DA(x)                                              (((x) & 0x1) << 14)
-#define   G_008DFC_DA(x)                                              (((x) >> 14) & 0x1)
-#define   C_008DFC_DA                                                 0xFFFFBFFF
-#define   S_008DFC_R128(x)                                            (((x) & 0x1) << 15)
-#define   G_008DFC_R128(x)                                            (((x) >> 15) & 0x1)
-#define   C_008DFC_R128                                               0xFFFF7FFF
-#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 16)
-#define   G_008DFC_TFE(x)                                             (((x) >> 16) & 0x1)
-#define   C_008DFC_TFE                                                0xFFFEFFFF
-#define   S_008DFC_LWE(x)                                             (((x) & 0x1) << 17)
-#define   G_008DFC_LWE(x)                                             (((x) >> 17) & 0x1)
-#define   C_008DFC_LWE                                                0xFFFDFFFF
-#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 18)
-#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0x7F)
-#define   C_008DFC_OP                                                 0xFE03FFFF
-#define     V_008DFC_SQ_IMAGE_LOAD                                  0x00
-#define     V_008DFC_SQ_IMAGE_LOAD_MIP                              0x01
-#define     V_008DFC_SQ_IMAGE_LOAD_PCK                              0x02
-#define     V_008DFC_SQ_IMAGE_LOAD_PCK_SGN                          0x03
-#define     V_008DFC_SQ_IMAGE_LOAD_MIP_PCK                          0x04
-#define     V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN                      0x05
-#define     V_008DFC_SQ_IMAGE_STORE                                 0x08
-#define     V_008DFC_SQ_IMAGE_STORE_MIP                             0x09
-#define     V_008DFC_SQ_IMAGE_STORE_PCK                             0x0A
-#define     V_008DFC_SQ_IMAGE_STORE_MIP_PCK                         0x0B
-#define     V_008DFC_SQ_IMAGE_GET_RESINFO                           0x0E
-#define     V_008DFC_SQ_IMAGE_ATOMIC_SWAP                           0x0F
-#define     V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP                        0x10
-#define     V_008DFC_SQ_IMAGE_ATOMIC_ADD                            0x11
-#define     V_008DFC_SQ_IMAGE_ATOMIC_SUB                            0x12
-#define     V_008DFC_SQ_IMAGE_ATOMIC_RSUB                           0x13 /* not on CIK */
-#define     V_008DFC_SQ_IMAGE_ATOMIC_SMIN                           0x14
-#define     V_008DFC_SQ_IMAGE_ATOMIC_UMIN                           0x15
-#define     V_008DFC_SQ_IMAGE_ATOMIC_SMAX                           0x16
-#define     V_008DFC_SQ_IMAGE_ATOMIC_UMAX                           0x17
-#define     V_008DFC_SQ_IMAGE_ATOMIC_AND                            0x18
-#define     V_008DFC_SQ_IMAGE_ATOMIC_OR                             0x19
-#define     V_008DFC_SQ_IMAGE_ATOMIC_XOR                            0x1A
-#define     V_008DFC_SQ_IMAGE_ATOMIC_INC                            0x1B
-#define     V_008DFC_SQ_IMAGE_ATOMIC_DEC                            0x1C
-#define     V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP                       0x1D
-#define     V_008DFC_SQ_IMAGE_ATOMIC_FMIN                           0x1E
-#define     V_008DFC_SQ_IMAGE_ATOMIC_FMAX                           0x1F
-#define     V_008DFC_SQ_IMAGE_SAMPLE                                0x20
-#define     V_008DFC_SQ_IMAGE_SAMPLE_CL                             0x21
-#define     V_008DFC_SQ_IMAGE_SAMPLE_D                              0x22
-#define     V_008DFC_SQ_IMAGE_SAMPLE_D_CL                           0x23
-#define     V_008DFC_SQ_IMAGE_SAMPLE_L                              0x24
-#define     V_008DFC_SQ_IMAGE_SAMPLE_B                              0x25
-#define     V_008DFC_SQ_IMAGE_SAMPLE_B_CL                           0x26
-#define     V_008DFC_SQ_IMAGE_SAMPLE_LZ                             0x27
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C                              0x28
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CL                           0x29
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D                            0x2A
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL                         0x2B
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_L                            0x2C
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B                            0x2D
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL                         0x2E
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_LZ                           0x2F
-#define     V_008DFC_SQ_IMAGE_SAMPLE_O                              0x30
-#define     V_008DFC_SQ_IMAGE_SAMPLE_CL_O                           0x31
-#define     V_008DFC_SQ_IMAGE_SAMPLE_D_O                            0x32
-#define     V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O                         0x33
-#define     V_008DFC_SQ_IMAGE_SAMPLE_L_O                            0x34
-#define     V_008DFC_SQ_IMAGE_SAMPLE_B_O                            0x35
-#define     V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O                         0x36
-#define     V_008DFC_SQ_IMAGE_SAMPLE_LZ_O                           0x37
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_O                            0x38
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O                         0x39
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D_O                          0x3A
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O                       0x3B
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_L_O                          0x3C
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B_O                          0x3D
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O                       0x3E
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O                         0x3F
-#define     V_008DFC_SQ_IMAGE_GATHER4                               0x40
-#define     V_008DFC_SQ_IMAGE_GATHER4_CL                            0x41
-#define     V_008DFC_SQ_IMAGE_GATHER4_L                             0x44
-#define     V_008DFC_SQ_IMAGE_GATHER4_B                             0x45
-#define     V_008DFC_SQ_IMAGE_GATHER4_B_CL                          0x46
-#define     V_008DFC_SQ_IMAGE_GATHER4_LZ                            0x47
-#define     V_008DFC_SQ_IMAGE_GATHER4_C                             0x48
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_CL                          0x49
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_L                           0x4C
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_B                           0x4D
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_B_CL                        0x4E
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_LZ                          0x4F
-#define     V_008DFC_SQ_IMAGE_GATHER4_O                             0x50
-#define     V_008DFC_SQ_IMAGE_GATHER4_CL_O                          0x51
-#define     V_008DFC_SQ_IMAGE_GATHER4_L_O                           0x54
-#define     V_008DFC_SQ_IMAGE_GATHER4_B_O                           0x55
-#define     V_008DFC_SQ_IMAGE_GATHER4_B_CL_O                        0x56
-#define     V_008DFC_SQ_IMAGE_GATHER4_LZ_O                          0x57
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_O                           0x58
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_CL_O                        0x59
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_L_O                         0x5C
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_B_O                         0x5D
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O                      0x5E
-#define     V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O                        0x5F
-#define     V_008DFC_SQ_IMAGE_GET_LOD                               0x60
-#define     V_008DFC_SQ_IMAGE_SAMPLE_CD                             0x68
-#define     V_008DFC_SQ_IMAGE_SAMPLE_CD_CL                          0x69
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD                           0x6A
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL                        0x6B
-#define     V_008DFC_SQ_IMAGE_SAMPLE_CD_O                           0x6C
-#define     V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O                        0x6D
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O                         0x6E
-#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O                      0x6F
-#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 25)
-#define   G_008DFC_SLC(x)                                             (((x) >> 25) & 0x1)
-#define   C_008DFC_SLC                                                0xFDFFFFFF
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_MIMG_FIELD                              0x3C
-#define R_008DFC_SQ_SOPP                                                0x008DFC
-#define   S_008DFC_SIMM16(x)                                          (((x) & 0xFFFF) << 0)
-#define   G_008DFC_SIMM16(x)                                          (((x) >> 0) & 0xFFFF)
-#define   C_008DFC_SIMM16                                             0xFFFF0000
-#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 16)
-#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x7F)
-#define   C_008DFC_OP                                                 0xFF80FFFF
-#define     V_008DFC_SQ_S_NOP                                       0x00
-#define     V_008DFC_SQ_S_ENDPGM                                    0x01
-#define     V_008DFC_SQ_S_BRANCH                                    0x02
-#define     V_008DFC_SQ_S_CBRANCH_SCC0                              0x04
-#define     V_008DFC_SQ_S_CBRANCH_SCC1                              0x05
-#define     V_008DFC_SQ_S_CBRANCH_VCCZ                              0x06
-#define     V_008DFC_SQ_S_CBRANCH_VCCNZ                             0x07
-#define     V_008DFC_SQ_S_CBRANCH_EXECZ                             0x08
-#define     V_008DFC_SQ_S_CBRANCH_EXECNZ                            0x09
-#define     V_008DFC_SQ_S_BARRIER                                   0x0A
-/* CIK */
-#define     V_008DFC_SQ_S_SETKILL                                   0x0B
-/*     */
-#define     V_008DFC_SQ_S_WAITCNT                                   0x0C
-#define     V_008DFC_SQ_S_SETHALT                                   0x0D
-#define     V_008DFC_SQ_S_SLEEP                                     0x0E
-#define     V_008DFC_SQ_S_SETPRIO                                   0x0F
-#define     V_008DFC_SQ_S_SENDMSG                                   0x10
-#define     V_008DFC_SQ_S_SENDMSGHALT                               0x11
-#define     V_008DFC_SQ_S_TRAP                                      0x12
-#define     V_008DFC_SQ_S_ICACHE_INV                                0x13
-#define     V_008DFC_SQ_S_INCPERFLEVEL                              0x14
-#define     V_008DFC_SQ_S_DECPERFLEVEL                              0x15
-#define     V_008DFC_SQ_S_TTRACEDATA                                0x16
-/* CIK */
-#define     V_008DFC_SQ_S_CBRANCH_CDBGSYS                           0x17
-#define     V_008DFC_SQ_S_CBRANCH_CDBGUSER                          0x18
-#define     V_008DFC_SQ_S_CBRANCH_CDBGSYS_OR_USER                   0x19
-#define     V_008DFC_SQ_S_CBRANCH_CDBGSYS_AND_USER                  0x1A
-/*     */
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1FF) << 23)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 23) & 0x1FF)
-#define   C_008DFC_ENCODING                                           0x007FFFFF
-#define     V_008DFC_SQ_ENC_SOPP_FIELD                              0x17F
-#define R_008DFC_SQ_VINTRP                                              0x008DFC
-#define   S_008DFC_VSRC(x)                                            (((x) & 0xFF) << 0)
-#define   G_008DFC_VSRC(x)                                            (((x) >> 0) & 0xFF)
-#define   C_008DFC_VSRC                                               0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_ATTRCHAN(x)                                        (((x) & 0x03) << 8)
-#define   G_008DFC_ATTRCHAN(x)                                        (((x) >> 8) & 0x03)
-#define   C_008DFC_ATTRCHAN                                           0xFFFFFCFF
-#define     V_008DFC_SQ_CHAN_X                                      0x00
-#define     V_008DFC_SQ_CHAN_Y                                      0x01
-#define     V_008DFC_SQ_CHAN_Z                                      0x02
-#define     V_008DFC_SQ_CHAN_W                                      0x03
-#define   S_008DFC_ATTR(x)                                            (((x) & 0x3F) << 10)
-#define   G_008DFC_ATTR(x)                                            (((x) >> 10) & 0x3F)
-#define   C_008DFC_ATTR                                               0xFFFF03FF
-#define     V_008DFC_SQ_ATTR                                        0x00
-#define   S_008DFC_OP(x)                                              (((x) & 0x03) << 16)
-#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x03)
-#define   C_008DFC_OP                                                 0xFFFCFFFF
-#define     V_008DFC_SQ_V_INTERP_P1_F32                             0x00
-#define     V_008DFC_SQ_V_INTERP_P2_F32                             0x01
-#define     V_008DFC_SQ_V_INTERP_MOV_F32                            0x02
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 18)
-#define   G_008DFC_VDST(x)                                            (((x) >> 18) & 0xFF)
-#define   C_008DFC_VDST                                               0xFC03FFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_VINTRP_FIELD                            0x32
-#define R_008DFC_SQ_MTBUF_0                                             0x008DFC
-#define   S_008DFC_OFFSET(x)                                          (((x) & 0xFFF) << 0)
-#define   G_008DFC_OFFSET(x)                                          (((x) >> 0) & 0xFFF)
-#define   C_008DFC_OFFSET                                             0xFFFFF000
-#define   S_008DFC_OFFEN(x)                                           (((x) & 0x1) << 12)
-#define   G_008DFC_OFFEN(x)                                           (((x) >> 12) & 0x1)
-#define   C_008DFC_OFFEN                                              0xFFFFEFFF
-#define   S_008DFC_IDXEN(x)                                           (((x) & 0x1) << 13)
-#define   G_008DFC_IDXEN(x)                                           (((x) >> 13) & 0x1)
-#define   C_008DFC_IDXEN                                              0xFFFFDFFF
-#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 14)
-#define   G_008DFC_GLC(x)                                             (((x) >> 14) & 0x1)
-#define   C_008DFC_GLC                                                0xFFFFBFFF
-#define   S_008DFC_ADDR64(x)                                          (((x) & 0x1) << 15)
-#define   G_008DFC_ADDR64(x)                                          (((x) >> 15) & 0x1)
-#define   C_008DFC_ADDR64                                             0xFFFF7FFF
-#define   S_008DFC_OP(x)                                              (((x) & 0x07) << 16)
-#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x07)
-#define   C_008DFC_OP                                                 0xFFF8FFFF
-#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X                       0x00
-#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY                      0x01
-#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ                     0x02
-#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW                    0x03
-#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_X                      0x04
-#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY                     0x05
-#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ                    0x06
-#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW                   0x07
-#define   S_008DFC_DFMT(x)                                            (((x) & 0x0F) << 19)
-#define   G_008DFC_DFMT(x)                                            (((x) >> 19) & 0x0F)
-#define   C_008DFC_DFMT                                               0xFF87FFFF
-#define   S_008DFC_NFMT(x)                                            (((x) & 0x07) << 23)
-#define   G_008DFC_NFMT(x)                                            (((x) >> 23) & 0x07)
-#define   C_008DFC_NFMT                                               0xFC7FFFFF
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_MTBUF_FIELD                             0x3A
-#define R_008DFC_SQ_SMRD                                                0x008DFC
-#define   S_008DFC_OFFSET(x)                                          (((x) & 0xFF) << 0)
-#define   G_008DFC_OFFSET(x)                                          (((x) >> 0) & 0xFF)
-#define   C_008DFC_OFFSET                                             0xFFFFFF00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-/* CIK */
-#define     V_008DFC_SQ_SRC_LITERAL                                 0xFF
-/*     */
-#define   S_008DFC_IMM(x)                                             (((x) & 0x1) << 8)
-#define   G_008DFC_IMM(x)                                             (((x) >> 8) & 0x1)
-#define   C_008DFC_IMM                                                0xFFFFFEFF
-#define   S_008DFC_SBASE(x)                                           (((x) & 0x3F) << 9)
-#define   G_008DFC_SBASE(x)                                           (((x) >> 9) & 0x3F)
-#define   C_008DFC_SBASE                                              0xFFFF81FF
-#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 15)
-#define   G_008DFC_SDST(x)                                            (((x) >> 15) & 0x7F)
-#define   C_008DFC_SDST                                               0xFFC07FFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define   S_008DFC_OP(x)                                              (((x) & 0x1F) << 22)
-#define   G_008DFC_OP(x)                                              (((x) >> 22) & 0x1F)
-#define   C_008DFC_OP                                                 0xF83FFFFF
-#define     V_008DFC_SQ_S_LOAD_DWORD                                0x00
-#define     V_008DFC_SQ_S_LOAD_DWORDX2                              0x01
-#define     V_008DFC_SQ_S_LOAD_DWORDX4                              0x02
-#define     V_008DFC_SQ_S_LOAD_DWORDX8                              0x03
-#define     V_008DFC_SQ_S_LOAD_DWORDX16                             0x04
-#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORD                         0x08
-#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2                       0x09
-#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4                       0x0A
-#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8                       0x0B
-#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16                      0x0C
-/* CIK */
-#define     V_008DFC_SQ_S_DCACHE_INV_VOL                            0x1D
-/*     */
-#define     V_008DFC_SQ_S_MEMTIME                                   0x1E
-#define     V_008DFC_SQ_S_DCACHE_INV                                0x1F
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1F) << 27)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 27) & 0x1F)
-#define   C_008DFC_ENCODING                                           0x07FFFFFF
-#define     V_008DFC_SQ_ENC_SMRD_FIELD                              0x18
-/* CIK */
-#define R_008DFC_SQ_FLAT_0                                              0x008DFC
-#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 16)
-#define   G_008DFC_GLC(x)                                             (((x) >> 16) & 0x1)
-#define   C_008DFC_GLC                                                0xFFFEFFFF
-#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 17)
-#define   G_008DFC_SLC(x)                                             (((x) >> 17) & 0x1)
-#define   C_008DFC_SLC                                                0xFFFDFFFF
-#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 18)
-#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0x7F)
-#define   C_008DFC_OP                                                 0xFE03FFFF
-#define     V_008DFC_SQ_FLAT_LOAD_UBYTE                             0x08
-#define     V_008DFC_SQ_FLAT_LOAD_SBYTE                             0x09
-#define     V_008DFC_SQ_FLAT_LOAD_USHORT                            0x0A
-#define     V_008DFC_SQ_FLAT_LOAD_SSHORT                            0x0B
-#define     V_008DFC_SQ_FLAT_LOAD_DWORD                             0x0C
-#define     V_008DFC_SQ_FLAT_LOAD_DWORDX2                           0x0D
-#define     V_008DFC_SQ_FLAT_LOAD_DWORDX4                           0x0E
-#define     V_008DFC_SQ_FLAT_LOAD_DWORDX3                           0x0F
-#define     V_008DFC_SQ_FLAT_STORE_BYTE                             0x18
-#define     V_008DFC_SQ_FLAT_STORE_SHORT                            0x1A
-#define     V_008DFC_SQ_FLAT_STORE_DWORD                            0x1C
-#define     V_008DFC_SQ_FLAT_STORE_DWORDX2                          0x1D
-#define     V_008DFC_SQ_FLAT_STORE_DWORDX4                          0x1E
-#define     V_008DFC_SQ_FLAT_STORE_DWORDX3                          0x1F
-#define     V_008DFC_SQ_FLAT_ATOMIC_SWAP                            0x30
-#define     V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP                         0x31
-#define     V_008DFC_SQ_FLAT_ATOMIC_ADD                             0x32
-#define     V_008DFC_SQ_FLAT_ATOMIC_SUB                             0x33
-#define     V_008DFC_SQ_FLAT_ATOMIC_SMIN                            0x35
-#define     V_008DFC_SQ_FLAT_ATOMIC_UMIN                            0x36
-#define     V_008DFC_SQ_FLAT_ATOMIC_SMAX                            0x37
-#define     V_008DFC_SQ_FLAT_ATOMIC_UMAX                            0x38
-#define     V_008DFC_SQ_FLAT_ATOMIC_AND                             0x39
-#define     V_008DFC_SQ_FLAT_ATOMIC_OR                              0x3A
-#define     V_008DFC_SQ_FLAT_ATOMIC_XOR                             0x3B
-#define     V_008DFC_SQ_FLAT_ATOMIC_INC                             0x3C
-#define     V_008DFC_SQ_FLAT_ATOMIC_DEC                             0x3D
-#define     V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP                        0x3E
-#define     V_008DFC_SQ_FLAT_ATOMIC_FMIN                            0x3F
-#define     V_008DFC_SQ_FLAT_ATOMIC_FMAX                            0x40
-#define     V_008DFC_SQ_FLAT_ATOMIC_SWAP_X2                         0x50
-#define     V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP_X2                      0x51
-#define     V_008DFC_SQ_FLAT_ATOMIC_ADD_X2                          0x52
-#define     V_008DFC_SQ_FLAT_ATOMIC_SUB_X2                          0x53
-#define     V_008DFC_SQ_FLAT_ATOMIC_SMIN_X2                         0x55
-#define     V_008DFC_SQ_FLAT_ATOMIC_UMIN_X2                         0x56
-#define     V_008DFC_SQ_FLAT_ATOMIC_SMAX_X2                         0x57
-#define     V_008DFC_SQ_FLAT_ATOMIC_UMAX_X2                         0x58
-#define     V_008DFC_SQ_FLAT_ATOMIC_AND_X2                          0x59
-#define     V_008DFC_SQ_FLAT_ATOMIC_OR_X2                           0x5A
-#define     V_008DFC_SQ_FLAT_ATOMIC_XOR_X2                          0x5B
-#define     V_008DFC_SQ_FLAT_ATOMIC_INC_X2                          0x5C
-#define     V_008DFC_SQ_FLAT_ATOMIC_DEC_X2                          0x5D
-#define     V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP_X2                     0x5E
-#define     V_008DFC_SQ_FLAT_ATOMIC_FMIN_X2                         0x5F
-#define     V_008DFC_SQ_FLAT_ATOMIC_FMAX_X2                         0x60
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_FLAT_FIELD                              0x37
-/*     */
-#define R_008DFC_SQ_EXP_1                                               0x008DFC
-#define   S_008DFC_VSRC0(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_VSRC0(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_VSRC0                                              0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VSRC1(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_VSRC1(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_VSRC1                                              0xFFFF00FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VSRC2(x)                                           (((x) & 0xFF) << 16)
-#define   G_008DFC_VSRC2(x)                                           (((x) >> 16) & 0xFF)
-#define   C_008DFC_VSRC2                                              0xFF00FFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VSRC3(x)                                           (((x) & 0xFF) << 24)
-#define   G_008DFC_VSRC3(x)                                           (((x) >> 24) & 0xFF)
-#define   C_008DFC_VSRC3                                              0x00FFFFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define R_008DFC_SQ_DS_1                                                0x008DFC
-#define   S_008DFC_ADDR(x)                                            (((x) & 0xFF) << 0)
-#define   G_008DFC_ADDR(x)                                            (((x) >> 0) & 0xFF)
-#define   C_008DFC_ADDR                                               0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_DATA0(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_DATA0(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_DATA0                                              0xFFFF00FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_DATA1(x)                                           (((x) & 0xFF) << 16)
-#define   G_008DFC_DATA1(x)                                           (((x) >> 16) & 0xFF)
-#define   C_008DFC_DATA1                                              0xFF00FFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 24)
-#define   G_008DFC_VDST(x)                                            (((x) >> 24) & 0xFF)
-#define   C_008DFC_VDST                                               0x00FFFFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define R_008DFC_SQ_VOPC                                                0x008DFC
-#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
-#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
-#define   C_008DFC_SRC0                                               0xFFFFFE00
-#define     V_008DFC_SQ_SGPR                                        0x00
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define     V_008DFC_SQ_SRC_VGPR                                    0x100
-#define   S_008DFC_VSRC1(x)                                           (((x) & 0xFF) << 9)
-#define   G_008DFC_VSRC1(x)                                           (((x) >> 9) & 0xFF)
-#define   C_008DFC_VSRC1                                              0xFFFE01FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 17)
-#define   G_008DFC_OP(x)                                              (((x) >> 17) & 0xFF)
-#define   C_008DFC_OP                                                 0xFE01FFFF
-#define     V_008DFC_SQ_V_CMP_F_F32                                 0x00
-#define     V_008DFC_SQ_V_CMP_LT_F32                                0x01
-#define     V_008DFC_SQ_V_CMP_EQ_F32                                0x02
-#define     V_008DFC_SQ_V_CMP_LE_F32                                0x03
-#define     V_008DFC_SQ_V_CMP_GT_F32                                0x04
-#define     V_008DFC_SQ_V_CMP_LG_F32                                0x05
-#define     V_008DFC_SQ_V_CMP_GE_F32                                0x06
-#define     V_008DFC_SQ_V_CMP_O_F32                                 0x07
-#define     V_008DFC_SQ_V_CMP_U_F32                                 0x08
-#define     V_008DFC_SQ_V_CMP_NGE_F32                               0x09
-#define     V_008DFC_SQ_V_CMP_NLG_F32                               0x0A
-#define     V_008DFC_SQ_V_CMP_NGT_F32                               0x0B
-#define     V_008DFC_SQ_V_CMP_NLE_F32                               0x0C
-#define     V_008DFC_SQ_V_CMP_NEQ_F32                               0x0D
-#define     V_008DFC_SQ_V_CMP_NLT_F32                               0x0E
-#define     V_008DFC_SQ_V_CMP_TRU_F32                               0x0F
-#define     V_008DFC_SQ_V_CMPX_F_F32                                0x10
-#define     V_008DFC_SQ_V_CMPX_LT_F32                               0x11
-#define     V_008DFC_SQ_V_CMPX_EQ_F32                               0x12
-#define     V_008DFC_SQ_V_CMPX_LE_F32                               0x13
-#define     V_008DFC_SQ_V_CMPX_GT_F32                               0x14
-#define     V_008DFC_SQ_V_CMPX_LG_F32                               0x15
-#define     V_008DFC_SQ_V_CMPX_GE_F32                               0x16
-#define     V_008DFC_SQ_V_CMPX_O_F32                                0x17
-#define     V_008DFC_SQ_V_CMPX_U_F32                                0x18
-#define     V_008DFC_SQ_V_CMPX_NGE_F32                              0x19
-#define     V_008DFC_SQ_V_CMPX_NLG_F32                              0x1A
-#define     V_008DFC_SQ_V_CMPX_NGT_F32                              0x1B
-#define     V_008DFC_SQ_V_CMPX_NLE_F32                              0x1C
-#define     V_008DFC_SQ_V_CMPX_NEQ_F32                              0x1D
-#define     V_008DFC_SQ_V_CMPX_NLT_F32                              0x1E
-#define     V_008DFC_SQ_V_CMPX_TRU_F32                              0x1F
-#define     V_008DFC_SQ_V_CMP_F_F64                                 0x20
-#define     V_008DFC_SQ_V_CMP_LT_F64                                0x21
-#define     V_008DFC_SQ_V_CMP_EQ_F64                                0x22
-#define     V_008DFC_SQ_V_CMP_LE_F64                                0x23
-#define     V_008DFC_SQ_V_CMP_GT_F64                                0x24
-#define     V_008DFC_SQ_V_CMP_LG_F64                                0x25
-#define     V_008DFC_SQ_V_CMP_GE_F64                                0x26
-#define     V_008DFC_SQ_V_CMP_O_F64                                 0x27
-#define     V_008DFC_SQ_V_CMP_U_F64                                 0x28
-#define     V_008DFC_SQ_V_CMP_NGE_F64                               0x29
-#define     V_008DFC_SQ_V_CMP_NLG_F64                               0x2A
-#define     V_008DFC_SQ_V_CMP_NGT_F64                               0x2B
-#define     V_008DFC_SQ_V_CMP_NLE_F64                               0x2C
-#define     V_008DFC_SQ_V_CMP_NEQ_F64                               0x2D
-#define     V_008DFC_SQ_V_CMP_NLT_F64                               0x2E
-#define     V_008DFC_SQ_V_CMP_TRU_F64                               0x2F
-#define     V_008DFC_SQ_V_CMPX_F_F64                                0x30
-#define     V_008DFC_SQ_V_CMPX_LT_F64                               0x31
-#define     V_008DFC_SQ_V_CMPX_EQ_F64                               0x32
-#define     V_008DFC_SQ_V_CMPX_LE_F64                               0x33
-#define     V_008DFC_SQ_V_CMPX_GT_F64                               0x34
-#define     V_008DFC_SQ_V_CMPX_LG_F64                               0x35
-#define     V_008DFC_SQ_V_CMPX_GE_F64                               0x36
-#define     V_008DFC_SQ_V_CMPX_O_F64                                0x37
-#define     V_008DFC_SQ_V_CMPX_U_F64                                0x38
-#define     V_008DFC_SQ_V_CMPX_NGE_F64                              0x39
-#define     V_008DFC_SQ_V_CMPX_NLG_F64                              0x3A
-#define     V_008DFC_SQ_V_CMPX_NGT_F64                              0x3B
-#define     V_008DFC_SQ_V_CMPX_NLE_F64                              0x3C
-#define     V_008DFC_SQ_V_CMPX_NEQ_F64                              0x3D
-#define     V_008DFC_SQ_V_CMPX_NLT_F64                              0x3E
-#define     V_008DFC_SQ_V_CMPX_TRU_F64                              0x3F
-#define     V_008DFC_SQ_V_CMPS_F_F32                                0x40
-#define     V_008DFC_SQ_V_CMPS_LT_F32                               0x41
-#define     V_008DFC_SQ_V_CMPS_EQ_F32                               0x42
-#define     V_008DFC_SQ_V_CMPS_LE_F32                               0x43
-#define     V_008DFC_SQ_V_CMPS_GT_F32                               0x44
-#define     V_008DFC_SQ_V_CMPS_LG_F32                               0x45
-#define     V_008DFC_SQ_V_CMPS_GE_F32                               0x46
-#define     V_008DFC_SQ_V_CMPS_O_F32                                0x47
-#define     V_008DFC_SQ_V_CMPS_U_F32                                0x48
-#define     V_008DFC_SQ_V_CMPS_NGE_F32                              0x49
-#define     V_008DFC_SQ_V_CMPS_NLG_F32                              0x4A
-#define     V_008DFC_SQ_V_CMPS_NGT_F32                              0x4B
-#define     V_008DFC_SQ_V_CMPS_NLE_F32                              0x4C
-#define     V_008DFC_SQ_V_CMPS_NEQ_F32                              0x4D
-#define     V_008DFC_SQ_V_CMPS_NLT_F32                              0x4E
-#define     V_008DFC_SQ_V_CMPS_TRU_F32                              0x4F
-#define     V_008DFC_SQ_V_CMPSX_F_F32                               0x50
-#define     V_008DFC_SQ_V_CMPSX_LT_F32                              0x51
-#define     V_008DFC_SQ_V_CMPSX_EQ_F32                              0x52
-#define     V_008DFC_SQ_V_CMPSX_LE_F32                              0x53
-#define     V_008DFC_SQ_V_CMPSX_GT_F32                              0x54
-#define     V_008DFC_SQ_V_CMPSX_LG_F32                              0x55
-#define     V_008DFC_SQ_V_CMPSX_GE_F32                              0x56
-#define     V_008DFC_SQ_V_CMPSX_O_F32                               0x57
-#define     V_008DFC_SQ_V_CMPSX_U_F32                               0x58
-#define     V_008DFC_SQ_V_CMPSX_NGE_F32                             0x59
-#define     V_008DFC_SQ_V_CMPSX_NLG_F32                             0x5A
-#define     V_008DFC_SQ_V_CMPSX_NGT_F32                             0x5B
-#define     V_008DFC_SQ_V_CMPSX_NLE_F32                             0x5C
-#define     V_008DFC_SQ_V_CMPSX_NEQ_F32                             0x5D
-#define     V_008DFC_SQ_V_CMPSX_NLT_F32                             0x5E
-#define     V_008DFC_SQ_V_CMPSX_TRU_F32                             0x5F
-#define     V_008DFC_SQ_V_CMPS_F_F64                                0x60
-#define     V_008DFC_SQ_V_CMPS_LT_F64                               0x61
-#define     V_008DFC_SQ_V_CMPS_EQ_F64                               0x62
-#define     V_008DFC_SQ_V_CMPS_LE_F64                               0x63
-#define     V_008DFC_SQ_V_CMPS_GT_F64                               0x64
-#define     V_008DFC_SQ_V_CMPS_LG_F64                               0x65
-#define     V_008DFC_SQ_V_CMPS_GE_F64                               0x66
-#define     V_008DFC_SQ_V_CMPS_O_F64                                0x67
-#define     V_008DFC_SQ_V_CMPS_U_F64                                0x68
-#define     V_008DFC_SQ_V_CMPS_NGE_F64                              0x69
-#define     V_008DFC_SQ_V_CMPS_NLG_F64                              0x6A
-#define     V_008DFC_SQ_V_CMPS_NGT_F64                              0x6B
-#define     V_008DFC_SQ_V_CMPS_NLE_F64                              0x6C
-#define     V_008DFC_SQ_V_CMPS_NEQ_F64                              0x6D
-#define     V_008DFC_SQ_V_CMPS_NLT_F64                              0x6E
-#define     V_008DFC_SQ_V_CMPS_TRU_F64                              0x6F
-#define     V_008DFC_SQ_V_CMPSX_F_F64                               0x70
-#define     V_008DFC_SQ_V_CMPSX_LT_F64                              0x71
-#define     V_008DFC_SQ_V_CMPSX_EQ_F64                              0x72
-#define     V_008DFC_SQ_V_CMPSX_LE_F64                              0x73
-#define     V_008DFC_SQ_V_CMPSX_GT_F64                              0x74
-#define     V_008DFC_SQ_V_CMPSX_LG_F64                              0x75
-#define     V_008DFC_SQ_V_CMPSX_GE_F64                              0x76
-#define     V_008DFC_SQ_V_CMPSX_O_F64                               0x77
-#define     V_008DFC_SQ_V_CMPSX_U_F64                               0x78
-#define     V_008DFC_SQ_V_CMPSX_NGE_F64                             0x79
-#define     V_008DFC_SQ_V_CMPSX_NLG_F64                             0x7A
-#define     V_008DFC_SQ_V_CMPSX_NGT_F64                             0x7B
-#define     V_008DFC_SQ_V_CMPSX_NLE_F64                             0x7C
-#define     V_008DFC_SQ_V_CMPSX_NEQ_F64                             0x7D
-#define     V_008DFC_SQ_V_CMPSX_NLT_F64                             0x7E
-#define     V_008DFC_SQ_V_CMPSX_TRU_F64                             0x7F
-#define     V_008DFC_SQ_V_CMP_F_I32                                 0x80
-#define     V_008DFC_SQ_V_CMP_LT_I32                                0x81
-#define     V_008DFC_SQ_V_CMP_EQ_I32                                0x82
-#define     V_008DFC_SQ_V_CMP_LE_I32                                0x83
-#define     V_008DFC_SQ_V_CMP_GT_I32                                0x84
-#define     V_008DFC_SQ_V_CMP_NE_I32                                0x85
-#define     V_008DFC_SQ_V_CMP_GE_I32                                0x86
-#define     V_008DFC_SQ_V_CMP_T_I32                                 0x87
-#define     V_008DFC_SQ_V_CMP_CLASS_F32                             0x88
-#define     V_008DFC_SQ_V_CMPX_F_I32                                0x90
-#define     V_008DFC_SQ_V_CMPX_LT_I32                               0x91
-#define     V_008DFC_SQ_V_CMPX_EQ_I32                               0x92
-#define     V_008DFC_SQ_V_CMPX_LE_I32                               0x93
-#define     V_008DFC_SQ_V_CMPX_GT_I32                               0x94
-#define     V_008DFC_SQ_V_CMPX_NE_I32                               0x95
-#define     V_008DFC_SQ_V_CMPX_GE_I32                               0x96
-#define     V_008DFC_SQ_V_CMPX_T_I32                                0x97
-#define     V_008DFC_SQ_V_CMPX_CLASS_F32                            0x98
-#define     V_008DFC_SQ_V_CMP_F_I64                                 0xA0
-#define     V_008DFC_SQ_V_CMP_LT_I64                                0xA1
-#define     V_008DFC_SQ_V_CMP_EQ_I64                                0xA2
-#define     V_008DFC_SQ_V_CMP_LE_I64                                0xA3
-#define     V_008DFC_SQ_V_CMP_GT_I64                                0xA4
-#define     V_008DFC_SQ_V_CMP_NE_I64                                0xA5
-#define     V_008DFC_SQ_V_CMP_GE_I64                                0xA6
-#define     V_008DFC_SQ_V_CMP_T_I64                                 0xA7
-#define     V_008DFC_SQ_V_CMP_CLASS_F64                             0xA8
-#define     V_008DFC_SQ_V_CMPX_F_I64                                0xB0
-#define     V_008DFC_SQ_V_CMPX_LT_I64                               0xB1
-#define     V_008DFC_SQ_V_CMPX_EQ_I64                               0xB2
-#define     V_008DFC_SQ_V_CMPX_LE_I64                               0xB3
-#define     V_008DFC_SQ_V_CMPX_GT_I64                               0xB4
-#define     V_008DFC_SQ_V_CMPX_NE_I64                               0xB5
-#define     V_008DFC_SQ_V_CMPX_GE_I64                               0xB6
-#define     V_008DFC_SQ_V_CMPX_T_I64                                0xB7
-#define     V_008DFC_SQ_V_CMPX_CLASS_F64                            0xB8
-#define     V_008DFC_SQ_V_CMP_F_U32                                 0xC0
-#define     V_008DFC_SQ_V_CMP_LT_U32                                0xC1
-#define     V_008DFC_SQ_V_CMP_EQ_U32                                0xC2
-#define     V_008DFC_SQ_V_CMP_LE_U32                                0xC3
-#define     V_008DFC_SQ_V_CMP_GT_U32                                0xC4
-#define     V_008DFC_SQ_V_CMP_NE_U32                                0xC5
-#define     V_008DFC_SQ_V_CMP_GE_U32                                0xC6
-#define     V_008DFC_SQ_V_CMP_T_U32                                 0xC7
-#define     V_008DFC_SQ_V_CMPX_F_U32                                0xD0
-#define     V_008DFC_SQ_V_CMPX_LT_U32                               0xD1
-#define     V_008DFC_SQ_V_CMPX_EQ_U32                               0xD2
-#define     V_008DFC_SQ_V_CMPX_LE_U32                               0xD3
-#define     V_008DFC_SQ_V_CMPX_GT_U32                               0xD4
-#define     V_008DFC_SQ_V_CMPX_NE_U32                               0xD5
-#define     V_008DFC_SQ_V_CMPX_GE_U32                               0xD6
-#define     V_008DFC_SQ_V_CMPX_T_U32                                0xD7
-#define     V_008DFC_SQ_V_CMP_F_U64                                 0xE0
-#define     V_008DFC_SQ_V_CMP_LT_U64                                0xE1
-#define     V_008DFC_SQ_V_CMP_EQ_U64                                0xE2
-#define     V_008DFC_SQ_V_CMP_LE_U64                                0xE3
-#define     V_008DFC_SQ_V_CMP_GT_U64                                0xE4
-#define     V_008DFC_SQ_V_CMP_NE_U64                                0xE5
-#define     V_008DFC_SQ_V_CMP_GE_U64                                0xE6
-#define     V_008DFC_SQ_V_CMP_T_U64                                 0xE7
-#define     V_008DFC_SQ_V_CMPX_F_U64                                0xF0
-#define     V_008DFC_SQ_V_CMPX_LT_U64                               0xF1
-#define     V_008DFC_SQ_V_CMPX_EQ_U64                               0xF2
-#define     V_008DFC_SQ_V_CMPX_LE_U64                               0xF3
-#define     V_008DFC_SQ_V_CMPX_GT_U64                               0xF4
-#define     V_008DFC_SQ_V_CMPX_NE_U64                               0xF5
-#define     V_008DFC_SQ_V_CMPX_GE_U64                               0xF6
-#define     V_008DFC_SQ_V_CMPX_T_U64                                0xF7
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x7F) << 25)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 25) & 0x7F)
-#define   C_008DFC_ENCODING                                           0x01FFFFFF
-#define     V_008DFC_SQ_ENC_VOPC_FIELD                              0x3E
-#define R_008DFC_SQ_SOP1                                                0x008DFC
-#define   S_008DFC_SSRC0(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_SSRC0(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_SSRC0                                              0xFFFFFF00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 8)
-#define   G_008DFC_OP(x)                                              (((x) >> 8) & 0xFF)
-#define   C_008DFC_OP                                                 0xFFFF00FF
-#define     V_008DFC_SQ_S_MOV_B32                                   0x03
-#define     V_008DFC_SQ_S_MOV_B64                                   0x04
-#define     V_008DFC_SQ_S_CMOV_B32                                  0x05
-#define     V_008DFC_SQ_S_CMOV_B64                                  0x06
-#define     V_008DFC_SQ_S_NOT_B32                                   0x07
-#define     V_008DFC_SQ_S_NOT_B64                                   0x08
-#define     V_008DFC_SQ_S_WQM_B32                                   0x09
-#define     V_008DFC_SQ_S_WQM_B64                                   0x0A
-#define     V_008DFC_SQ_S_BREV_B32                                  0x0B
-#define     V_008DFC_SQ_S_BREV_B64                                  0x0C
-#define     V_008DFC_SQ_S_BCNT0_I32_B32                             0x0D
-#define     V_008DFC_SQ_S_BCNT0_I32_B64                             0x0E
-#define     V_008DFC_SQ_S_BCNT1_I32_B32                             0x0F
-#define     V_008DFC_SQ_S_BCNT1_I32_B64                             0x10
-#define     V_008DFC_SQ_S_FF0_I32_B32                               0x11
-#define     V_008DFC_SQ_S_FF0_I32_B64                               0x12
-#define     V_008DFC_SQ_S_FF1_I32_B32                               0x13
-#define     V_008DFC_SQ_S_FF1_I32_B64                               0x14
-#define     V_008DFC_SQ_S_FLBIT_I32_B32                             0x15
-#define     V_008DFC_SQ_S_FLBIT_I32_B64                             0x16
-#define     V_008DFC_SQ_S_FLBIT_I32                                 0x17
-#define     V_008DFC_SQ_S_FLBIT_I32_I64                             0x18
-#define     V_008DFC_SQ_S_SEXT_I32_I8                               0x19
-#define     V_008DFC_SQ_S_SEXT_I32_I16                              0x1A
-#define     V_008DFC_SQ_S_BITSET0_B32                               0x1B
-#define     V_008DFC_SQ_S_BITSET0_B64                               0x1C
-#define     V_008DFC_SQ_S_BITSET1_B32                               0x1D
-#define     V_008DFC_SQ_S_BITSET1_B64                               0x1E
-#define     V_008DFC_SQ_S_GETPC_B64                                 0x1F
-#define     V_008DFC_SQ_S_SETPC_B64                                 0x20
-#define     V_008DFC_SQ_S_SWAPPC_B64                                0x21
-#define     V_008DFC_SQ_S_RFE_B64                                   0x22
-#define     V_008DFC_SQ_S_AND_SAVEEXEC_B64                          0x24
-#define     V_008DFC_SQ_S_OR_SAVEEXEC_B64                           0x25
-#define     V_008DFC_SQ_S_XOR_SAVEEXEC_B64                          0x26
-#define     V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64                        0x27
-#define     V_008DFC_SQ_S_ORN2_SAVEEXEC_B64                         0x28
-#define     V_008DFC_SQ_S_NAND_SAVEEXEC_B64                         0x29
-#define     V_008DFC_SQ_S_NOR_SAVEEXEC_B64                          0x2A
-#define     V_008DFC_SQ_S_XNOR_SAVEEXEC_B64                         0x2B
-#define     V_008DFC_SQ_S_QUADMASK_B32                              0x2C
-#define     V_008DFC_SQ_S_QUADMASK_B64                              0x2D
-#define     V_008DFC_SQ_S_MOVRELS_B32                               0x2E
-#define     V_008DFC_SQ_S_MOVRELS_B64                               0x2F
-#define     V_008DFC_SQ_S_MOVRELD_B32                               0x30
-#define     V_008DFC_SQ_S_MOVRELD_B64                               0x31
-#define     V_008DFC_SQ_S_CBRANCH_JOIN                              0x32
-#define     V_008DFC_SQ_S_MOV_REGRD_B32                             0x33
-#define     V_008DFC_SQ_S_ABS_I32                                   0x34
-#define     V_008DFC_SQ_S_MOV_FED_B32                               0x35
-#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 16)
-#define   G_008DFC_SDST(x)                                            (((x) >> 16) & 0x7F)
-#define   C_008DFC_SDST                                               0xFF80FFFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1FF) << 23)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 23) & 0x1FF)
-#define   C_008DFC_ENCODING                                           0x007FFFFF
-#define     V_008DFC_SQ_ENC_SOP1_FIELD                              0x17D
-#define R_008DFC_SQ_MTBUF_1                                             0x008DFC
-#define   S_008DFC_VADDR(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_VADDR(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_VADDR                                              0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VDATA(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_VDATA(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_VDATA                                              0xFFFF00FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_SRSRC(x)                                           (((x) & 0x1F) << 16)
-#define   G_008DFC_SRSRC(x)                                           (((x) >> 16) & 0x1F)
-#define   C_008DFC_SRSRC                                              0xFFE0FFFF
-#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 22)
-#define   G_008DFC_SLC(x)                                             (((x) >> 22) & 0x1)
-#define   C_008DFC_SLC                                                0xFFBFFFFF
-#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 23)
-#define   G_008DFC_TFE(x)                                             (((x) >> 23) & 0x1)
-#define   C_008DFC_TFE                                                0xFF7FFFFF
-#define   S_008DFC_SOFFSET(x)                                         (((x) & 0xFF) << 24)
-#define   G_008DFC_SOFFSET(x)                                         (((x) >> 24) & 0xFF)
-#define   C_008DFC_SOFFSET                                            0x00FFFFFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define R_008DFC_SQ_SOP2                                                0x008DFC
-#define   S_008DFC_SSRC0(x)                                           (((x) & 0xFF) << 0)
-#define   G_008DFC_SSRC0(x)                                           (((x) >> 0) & 0xFF)
-#define   C_008DFC_SSRC0                                              0xFFFFFF00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define   S_008DFC_SSRC1(x)                                           (((x) & 0xFF) << 8)
-#define   G_008DFC_SSRC1(x)                                           (((x) >> 8) & 0xFF)
-#define   C_008DFC_SSRC1                                              0xFFFF00FF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 16)
-#define   G_008DFC_SDST(x)                                            (((x) >> 16) & 0x7F)
-#define   C_008DFC_SDST                                               0xFF80FFFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 23)
-#define   G_008DFC_OP(x)                                              (((x) >> 23) & 0x7F)
-#define   C_008DFC_OP                                                 0xC07FFFFF
-#define     V_008DFC_SQ_S_ADD_U32                                   0x00
-#define     V_008DFC_SQ_S_SUB_U32                                   0x01
-#define     V_008DFC_SQ_S_ADD_I32                                   0x02
-#define     V_008DFC_SQ_S_SUB_I32                                   0x03
-#define     V_008DFC_SQ_S_ADDC_U32                                  0x04
-#define     V_008DFC_SQ_S_SUBB_U32                                  0x05
-#define     V_008DFC_SQ_S_MIN_I32                                   0x06
-#define     V_008DFC_SQ_S_MIN_U32                                   0x07
-#define     V_008DFC_SQ_S_MAX_I32                                   0x08
-#define     V_008DFC_SQ_S_MAX_U32                                   0x09
-#define     V_008DFC_SQ_S_CSELECT_B32                               0x0A
-#define     V_008DFC_SQ_S_CSELECT_B64                               0x0B
-#define     V_008DFC_SQ_S_AND_B32                                   0x0E
-#define     V_008DFC_SQ_S_AND_B64                                   0x0F
-#define     V_008DFC_SQ_S_OR_B32                                    0x10
-#define     V_008DFC_SQ_S_OR_B64                                    0x11
-#define     V_008DFC_SQ_S_XOR_B32                                   0x12
-#define     V_008DFC_SQ_S_XOR_B64                                   0x13
-#define     V_008DFC_SQ_S_ANDN2_B32                                 0x14
-#define     V_008DFC_SQ_S_ANDN2_B64                                 0x15
-#define     V_008DFC_SQ_S_ORN2_B32                                  0x16
-#define     V_008DFC_SQ_S_ORN2_B64                                  0x17
-#define     V_008DFC_SQ_S_NAND_B32                                  0x18
-#define     V_008DFC_SQ_S_NAND_B64                                  0x19
-#define     V_008DFC_SQ_S_NOR_B32                                   0x1A
-#define     V_008DFC_SQ_S_NOR_B64                                   0x1B
-#define     V_008DFC_SQ_S_XNOR_B32                                  0x1C
-#define     V_008DFC_SQ_S_XNOR_B64                                  0x1D
-#define     V_008DFC_SQ_S_LSHL_B32                                  0x1E
-#define     V_008DFC_SQ_S_LSHL_B64                                  0x1F
-#define     V_008DFC_SQ_S_LSHR_B32                                  0x20
-#define     V_008DFC_SQ_S_LSHR_B64                                  0x21
-#define     V_008DFC_SQ_S_ASHR_I32                                  0x22
-#define     V_008DFC_SQ_S_ASHR_I64                                  0x23
-#define     V_008DFC_SQ_S_BFM_B32                                   0x24
-#define     V_008DFC_SQ_S_BFM_B64                                   0x25
-#define     V_008DFC_SQ_S_MUL_I32                                   0x26
-#define     V_008DFC_SQ_S_BFE_U32                                   0x27
-#define     V_008DFC_SQ_S_BFE_I32                                   0x28
-#define     V_008DFC_SQ_S_BFE_U64                                   0x29
-#define     V_008DFC_SQ_S_BFE_I64                                   0x2A
-#define     V_008DFC_SQ_S_CBRANCH_G_FORK                            0x2B
-#define     V_008DFC_SQ_S_ABSDIFF_I32                               0x2C
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x03) << 30)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 30) & 0x03)
-#define   C_008DFC_ENCODING                                           0x3FFFFFFF
-#define     V_008DFC_SQ_ENC_SOP2_FIELD                              0x02
-#define R_008DFC_SQ_SOPK                                                0x008DFC
-#define   S_008DFC_SIMM16(x)                                          (((x) & 0xFFFF) << 0)
-#define   G_008DFC_SIMM16(x)                                          (((x) >> 0) & 0xFFFF)
-#define   C_008DFC_SIMM16                                             0xFFFF0000
-#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 16)
-#define   G_008DFC_SDST(x)                                            (((x) >> 16) & 0x7F)
-#define   C_008DFC_SDST                                               0xFF80FFFF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define   S_008DFC_OP(x)                                              (((x) & 0x1F) << 23)
-#define   G_008DFC_OP(x)                                              (((x) >> 23) & 0x1F)
-#define   C_008DFC_OP                                                 0xF07FFFFF
-#define     V_008DFC_SQ_S_MOVK_I32                                  0x00
-#define     V_008DFC_SQ_S_CMOVK_I32                                 0x02
-#define     V_008DFC_SQ_S_CMPK_EQ_I32                               0x03
-#define     V_008DFC_SQ_S_CMPK_LG_I32                               0x04
-#define     V_008DFC_SQ_S_CMPK_GT_I32                               0x05
-#define     V_008DFC_SQ_S_CMPK_GE_I32                               0x06
-#define     V_008DFC_SQ_S_CMPK_LT_I32                               0x07
-#define     V_008DFC_SQ_S_CMPK_LE_I32                               0x08
-#define     V_008DFC_SQ_S_CMPK_EQ_U32                               0x09
-#define     V_008DFC_SQ_S_CMPK_LG_U32                               0x0A
-#define     V_008DFC_SQ_S_CMPK_GT_U32                               0x0B
-#define     V_008DFC_SQ_S_CMPK_GE_U32                               0x0C
-#define     V_008DFC_SQ_S_CMPK_LT_U32                               0x0D
-#define     V_008DFC_SQ_S_CMPK_LE_U32                               0x0E
-#define     V_008DFC_SQ_S_ADDK_I32                                  0x0F
-#define     V_008DFC_SQ_S_MULK_I32                                  0x10
-#define     V_008DFC_SQ_S_CBRANCH_I_FORK                            0x11
-#define     V_008DFC_SQ_S_GETREG_B32                                0x12
-#define     V_008DFC_SQ_S_SETREG_B32                                0x13
-#define     V_008DFC_SQ_S_GETREG_REGRD_B32                          0x14
-#define     V_008DFC_SQ_S_SETREG_IMM32_B32                          0x15
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x0F) << 28)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 28) & 0x0F)
-#define   C_008DFC_ENCODING                                           0x0FFFFFFF
-#define     V_008DFC_SQ_ENC_SOPK_FIELD                              0x0B
-#define R_008DFC_SQ_VOP3_0                                              0x008DFC
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 0)
-#define   G_008DFC_VDST(x)                                            (((x) >> 0) & 0xFF)
-#define   C_008DFC_VDST                                               0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_ABS(x)                                             (((x) & 0x07) << 8)
-#define   G_008DFC_ABS(x)                                             (((x) >> 8) & 0x07)
-#define   C_008DFC_ABS                                                0xFFFFF8FF
-#define   S_008DFC_CLAMP(x)                                           (((x) & 0x1) << 11)
-#define   G_008DFC_CLAMP(x)                                           (((x) >> 11) & 0x1)
-#define   C_008DFC_CLAMP                                              0xFFFFF7FF
-#define   S_008DFC_OP(x)                                              (((x) & 0x1FF) << 17)
-#define   G_008DFC_OP(x)                                              (((x) >> 17) & 0x1FF)
-#define   C_008DFC_OP                                                 0xFC01FFFF
-#define     V_008DFC_SQ_V_OPC_OFFSET                                0x00
-#define     V_008DFC_SQ_V_OP2_OFFSET                                0x100
-#define     V_008DFC_SQ_V_MAD_LEGACY_F32                            0x140
-#define     V_008DFC_SQ_V_MAD_F32                                   0x141
-#define     V_008DFC_SQ_V_MAD_I32_I24                               0x142
-#define     V_008DFC_SQ_V_MAD_U32_U24                               0x143
-#define     V_008DFC_SQ_V_CUBEID_F32                                0x144
-#define     V_008DFC_SQ_V_CUBESC_F32                                0x145
-#define     V_008DFC_SQ_V_CUBETC_F32                                0x146
-#define     V_008DFC_SQ_V_CUBEMA_F32                                0x147
-#define     V_008DFC_SQ_V_BFE_U32                                   0x148
-#define     V_008DFC_SQ_V_BFE_I32                                   0x149
-#define     V_008DFC_SQ_V_BFI_B32                                   0x14A
-#define     V_008DFC_SQ_V_FMA_F32                                   0x14B
-#define     V_008DFC_SQ_V_FMA_F64                                   0x14C
-#define     V_008DFC_SQ_V_LERP_U8                                   0x14D
-#define     V_008DFC_SQ_V_ALIGNBIT_B32                              0x14E
-#define     V_008DFC_SQ_V_ALIGNBYTE_B32                             0x14F
-#define     V_008DFC_SQ_V_MULLIT_F32                                0x150
-#define     V_008DFC_SQ_V_MIN3_F32                                  0x151
-#define     V_008DFC_SQ_V_MIN3_I32                                  0x152
-#define     V_008DFC_SQ_V_MIN3_U32                                  0x153
-#define     V_008DFC_SQ_V_MAX3_F32                                  0x154
-#define     V_008DFC_SQ_V_MAX3_I32                                  0x155
-#define     V_008DFC_SQ_V_MAX3_U32                                  0x156
-#define     V_008DFC_SQ_V_MED3_F32                                  0x157
-#define     V_008DFC_SQ_V_MED3_I32                                  0x158
-#define     V_008DFC_SQ_V_MED3_U32                                  0x159
-#define     V_008DFC_SQ_V_SAD_U8                                    0x15A
-#define     V_008DFC_SQ_V_SAD_HI_U8                                 0x15B
-#define     V_008DFC_SQ_V_SAD_U16                                   0x15C
-#define     V_008DFC_SQ_V_SAD_U32                                   0x15D
-#define     V_008DFC_SQ_V_CVT_PK_U8_F32                             0x15E
-#define     V_008DFC_SQ_V_DIV_FIXUP_F32                             0x15F
-#define     V_008DFC_SQ_V_DIV_FIXUP_F64                             0x160
-#define     V_008DFC_SQ_V_LSHL_B64                                  0x161
-#define     V_008DFC_SQ_V_LSHR_B64                                  0x162
-#define     V_008DFC_SQ_V_ASHR_I64                                  0x163
-#define     V_008DFC_SQ_V_ADD_F64                                   0x164
-#define     V_008DFC_SQ_V_MUL_F64                                   0x165
-#define     V_008DFC_SQ_V_MIN_F64                                   0x166
-#define     V_008DFC_SQ_V_MAX_F64                                   0x167
-#define     V_008DFC_SQ_V_LDEXP_F64                                 0x168
-#define     V_008DFC_SQ_V_MUL_LO_U32                                0x169
-#define     V_008DFC_SQ_V_MUL_HI_U32                                0x16A
-#define     V_008DFC_SQ_V_MUL_LO_I32                                0x16B
-#define     V_008DFC_SQ_V_MUL_HI_I32                                0x16C
-#define     V_008DFC_SQ_V_DIV_SCALE_F32                             0x16D
-#define     V_008DFC_SQ_V_DIV_SCALE_F64                             0x16E
-#define     V_008DFC_SQ_V_DIV_FMAS_F32                              0x16F
-#define     V_008DFC_SQ_V_DIV_FMAS_F64                              0x170
-#define     V_008DFC_SQ_V_MSAD_U8                                   0x171
-#define     V_008DFC_SQ_V_QSAD_U8                                   0x172
-#define     V_008DFC_SQ_V_MQSAD_U8                                  0x173
-#define     V_008DFC_SQ_V_TRIG_PREOP_F64                            0x174
-/* CIK */
-#define     V_008DFC_SQ_V_MQSAD_U32_U8                              0x175
-#define     V_008DFC_SQ_V_MAD_U64_U32                               0x176
-#define     V_008DFC_SQ_V_MAD_I64_I32                               0x177
-/*     */
-#define     V_008DFC_SQ_V_OP1_OFFSET                                0x180
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_VOP3_FIELD                              0x34
-#define R_008DFC_SQ_VOP2                                                0x008DFC
-#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
-#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
-#define   C_008DFC_SRC0                                               0xFFFFFE00
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define     V_008DFC_SQ_M0                                          0x7C
-#define     V_008DFC_SQ_EXEC_LO                                     0x7E
-#define     V_008DFC_SQ_EXEC_HI                                     0x7F
-#define     V_008DFC_SQ_SRC_0                                       0x80
-#define     V_008DFC_SQ_SRC_1_INT                                   0x81
-#define     V_008DFC_SQ_SRC_2_INT                                   0x82
-#define     V_008DFC_SQ_SRC_3_INT                                   0x83
-#define     V_008DFC_SQ_SRC_4_INT                                   0x84
-#define     V_008DFC_SQ_SRC_5_INT                                   0x85
-#define     V_008DFC_SQ_SRC_6_INT                                   0x86
-#define     V_008DFC_SQ_SRC_7_INT                                   0x87
-#define     V_008DFC_SQ_SRC_8_INT                                   0x88
-#define     V_008DFC_SQ_SRC_9_INT                                   0x89
-#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
-#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
-#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
-#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
-#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
-#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
-#define     V_008DFC_SQ_SRC_16_INT                                  0x90
-#define     V_008DFC_SQ_SRC_17_INT                                  0x91
-#define     V_008DFC_SQ_SRC_18_INT                                  0x92
-#define     V_008DFC_SQ_SRC_19_INT                                  0x93
-#define     V_008DFC_SQ_SRC_20_INT                                  0x94
-#define     V_008DFC_SQ_SRC_21_INT                                  0x95
-#define     V_008DFC_SQ_SRC_22_INT                                  0x96
-#define     V_008DFC_SQ_SRC_23_INT                                  0x97
-#define     V_008DFC_SQ_SRC_24_INT                                  0x98
-#define     V_008DFC_SQ_SRC_25_INT                                  0x99
-#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
-#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
-#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
-#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
-#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
-#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
-#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
-#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
-#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
-#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
-#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
-#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
-#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
-#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
-#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
-#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
-#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
-#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
-#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
-#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
-#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
-#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
-#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
-#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
-#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
-#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
-#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
-#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
-#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
-#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
-#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
-#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
-#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
-#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
-#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
-#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
-#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
-#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
-#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
-#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
-#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
-#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
-#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
-#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
-#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
-#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
-#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
-#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
-#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
-#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
-#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
-#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
-#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
-#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
-#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
-#define     V_008DFC_SQ_SRC_0_5                                     0xF0
-#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
-#define     V_008DFC_SQ_SRC_1                                       0xF2
-#define     V_008DFC_SQ_SRC_M_1                                     0xF3
-#define     V_008DFC_SQ_SRC_2                                       0xF4
-#define     V_008DFC_SQ_SRC_M_2                                     0xF5
-#define     V_008DFC_SQ_SRC_4                                       0xF6
-#define     V_008DFC_SQ_SRC_M_4                                     0xF7
-#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
-#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
-#define     V_008DFC_SQ_SRC_SCC                                     0xFD
-#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
-#define     V_008DFC_SQ_SRC_VGPR                                    0x100
-#define   S_008DFC_VSRC1(x)                                           (((x) & 0xFF) << 9)
-#define   G_008DFC_VSRC1(x)                                           (((x) >> 9) & 0xFF)
-#define   C_008DFC_VSRC1                                              0xFFFE01FF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 17)
-#define   G_008DFC_VDST(x)                                            (((x) >> 17) & 0xFF)
-#define   C_008DFC_VDST                                               0xFE01FFFF
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_OP(x)                                              (((x) & 0x3F) << 25)
-#define   G_008DFC_OP(x)                                              (((x) >> 25) & 0x3F)
-#define   C_008DFC_OP                                                 0x81FFFFFF
-#define     V_008DFC_SQ_V_CNDMASK_B32                               0x00
-#define     V_008DFC_SQ_V_READLANE_B32                              0x01
-#define     V_008DFC_SQ_V_WRITELANE_B32                             0x02
-#define     V_008DFC_SQ_V_ADD_F32                                   0x03
-#define     V_008DFC_SQ_V_SUB_F32                                   0x04
-#define     V_008DFC_SQ_V_SUBREV_F32                                0x05
-#define     V_008DFC_SQ_V_MAC_LEGACY_F32                            0x06
-#define     V_008DFC_SQ_V_MUL_LEGACY_F32                            0x07
-#define     V_008DFC_SQ_V_MUL_F32                                   0x08
-#define     V_008DFC_SQ_V_MUL_I32_I24                               0x09
-#define     V_008DFC_SQ_V_MUL_HI_I32_I24                            0x0A
-#define     V_008DFC_SQ_V_MUL_U32_U24                               0x0B
-#define     V_008DFC_SQ_V_MUL_HI_U32_U24                            0x0C
-#define     V_008DFC_SQ_V_MIN_LEGACY_F32                            0x0D
-#define     V_008DFC_SQ_V_MAX_LEGACY_F32                            0x0E
-#define     V_008DFC_SQ_V_MIN_F32                                   0x0F
-#define     V_008DFC_SQ_V_MAX_F32                                   0x10
-#define     V_008DFC_SQ_V_MIN_I32                                   0x11
-#define     V_008DFC_SQ_V_MAX_I32                                   0x12
-#define     V_008DFC_SQ_V_MIN_U32                                   0x13
-#define     V_008DFC_SQ_V_MAX_U32                                   0x14
-#define     V_008DFC_SQ_V_LSHR_B32                                  0x15
-#define     V_008DFC_SQ_V_LSHRREV_B32                               0x16
-#define     V_008DFC_SQ_V_ASHR_I32                                  0x17
-#define     V_008DFC_SQ_V_ASHRREV_I32                               0x18
-#define     V_008DFC_SQ_V_LSHL_B32                                  0x19
-#define     V_008DFC_SQ_V_LSHLREV_B32                               0x1A
-#define     V_008DFC_SQ_V_AND_B32                                   0x1B
-#define     V_008DFC_SQ_V_OR_B32                                    0x1C
-#define     V_008DFC_SQ_V_XOR_B32                                   0x1D
-#define     V_008DFC_SQ_V_BFM_B32                                   0x1E
-#define     V_008DFC_SQ_V_MAC_F32                                   0x1F
-#define     V_008DFC_SQ_V_MADMK_F32                                 0x20
-#define     V_008DFC_SQ_V_MADAK_F32                                 0x21
-#define     V_008DFC_SQ_V_BCNT_U32_B32                              0x22
-#define     V_008DFC_SQ_V_MBCNT_LO_U32_B32                          0x23
-#define     V_008DFC_SQ_V_MBCNT_HI_U32_B32                          0x24
-#define     V_008DFC_SQ_V_ADD_I32                                   0x25
-#define     V_008DFC_SQ_V_SUB_I32                                   0x26
-#define     V_008DFC_SQ_V_SUBREV_I32                                0x27
-#define     V_008DFC_SQ_V_ADDC_U32                                  0x28
-#define     V_008DFC_SQ_V_SUBB_U32                                  0x29
-#define     V_008DFC_SQ_V_SUBBREV_U32                               0x2A
-#define     V_008DFC_SQ_V_LDEXP_F32                                 0x2B
-#define     V_008DFC_SQ_V_CVT_PKACCUM_U8_F32                        0x2C
-#define     V_008DFC_SQ_V_CVT_PKNORM_I16_F32                        0x2D
-#define     V_008DFC_SQ_V_CVT_PKNORM_U16_F32                        0x2E
-#define     V_008DFC_SQ_V_CVT_PKRTZ_F16_F32                         0x2F
-#define     V_008DFC_SQ_V_CVT_PK_U16_U32                            0x30
-#define     V_008DFC_SQ_V_CVT_PK_I16_I32                            0x31
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1) << 31)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 31) & 0x1)
-#define   C_008DFC_ENCODING                                           0x7FFFFFFF
-#define R_008DFC_SQ_VOP3_0_SDST_ENC                                     0x008DFC
-#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 0)
-#define   G_008DFC_VDST(x)                                            (((x) >> 0) & 0xFF)
-#define   C_008DFC_VDST                                               0xFFFFFF00
-#define     V_008DFC_SQ_VGPR                                        0x00
-#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 8)
-#define   G_008DFC_SDST(x)                                            (((x) >> 8) & 0x7F)
-#define   C_008DFC_SDST                                               0xFFFF80FF
-#define     V_008DFC_SQ_SGPR                                        0x00
-/* CIK */
-#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
-#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
-/*     */
-#define     V_008DFC_SQ_VCC_LO                                      0x6A
-#define     V_008DFC_SQ_VCC_HI                                      0x6B
-#define     V_008DFC_SQ_TBA_LO                                      0x6C
-#define     V_008DFC_SQ_TBA_HI                                      0x6D
-#define     V_008DFC_SQ_TMA_LO                                      0x6E
-#define     V_008DFC_SQ_TMA_HI                                      0x6F
-#define     V_008DFC_SQ_TTMP0                                       0x70
-#define     V_008DFC_SQ_TTMP1                                       0x71
-#define     V_008DFC_SQ_TTMP2                                       0x72
-#define     V_008DFC_SQ_TTMP3                                       0x73
-#define     V_008DFC_SQ_TTMP4                                       0x74
-#define     V_008DFC_SQ_TTMP5                                       0x75
-#define     V_008DFC_SQ_TTMP6                                       0x76
-#define     V_008DFC_SQ_TTMP7                                       0x77
-#define     V_008DFC_SQ_TTMP8                                       0x78
-#define     V_008DFC_SQ_TTMP9                                       0x79
-#define     V_008DFC_SQ_TTMP10                                      0x7A
-#define     V_008DFC_SQ_TTMP11                                      0x7B
-#define   S_008DFC_OP(x)                                              (((x) & 0x1FF) << 17)
-#define   G_008DFC_OP(x)                                              (((x) >> 17) & 0x1FF)
-#define   C_008DFC_OP                                                 0xFC01FFFF
-#define     V_008DFC_SQ_V_OPC_OFFSET                                0x00
-#define     V_008DFC_SQ_V_OP2_OFFSET                                0x100
-#define     V_008DFC_SQ_V_MAD_LEGACY_F32                            0x140
-#define     V_008DFC_SQ_V_MAD_F32                                   0x141
-#define     V_008DFC_SQ_V_MAD_I32_I24                               0x142
-#define     V_008DFC_SQ_V_MAD_U32_U24                               0x143
-#define     V_008DFC_SQ_V_CUBEID_F32                                0x144
-#define     V_008DFC_SQ_V_CUBESC_F32                                0x145
-#define     V_008DFC_SQ_V_CUBETC_F32                                0x146
-#define     V_008DFC_SQ_V_CUBEMA_F32                                0x147
-#define     V_008DFC_SQ_V_BFE_U32                                   0x148
-#define     V_008DFC_SQ_V_BFE_I32                                   0x149
-#define     V_008DFC_SQ_V_BFI_B32                                   0x14A
-#define     V_008DFC_SQ_V_FMA_F32                                   0x14B
-#define     V_008DFC_SQ_V_FMA_F64                                   0x14C
-#define     V_008DFC_SQ_V_LERP_U8                                   0x14D
-#define     V_008DFC_SQ_V_ALIGNBIT_B32                              0x14E
-#define     V_008DFC_SQ_V_ALIGNBYTE_B32                             0x14F
-#define     V_008DFC_SQ_V_MULLIT_F32                                0x150
-#define     V_008DFC_SQ_V_MIN3_F32                                  0x151
-#define     V_008DFC_SQ_V_MIN3_I32                                  0x152
-#define     V_008DFC_SQ_V_MIN3_U32                                  0x153
-#define     V_008DFC_SQ_V_MAX3_F32                                  0x154
-#define     V_008DFC_SQ_V_MAX3_I32                                  0x155
-#define     V_008DFC_SQ_V_MAX3_U32                                  0x156
-#define     V_008DFC_SQ_V_MED3_F32                                  0x157
-#define     V_008DFC_SQ_V_MED3_I32                                  0x158
-#define     V_008DFC_SQ_V_MED3_U32                                  0x159
-#define     V_008DFC_SQ_V_SAD_U8                                    0x15A
-#define     V_008DFC_SQ_V_SAD_HI_U8                                 0x15B
-#define     V_008DFC_SQ_V_SAD_U16                                   0x15C
-#define     V_008DFC_SQ_V_SAD_U32                                   0x15D
-#define     V_008DFC_SQ_V_CVT_PK_U8_F32                             0x15E
-#define     V_008DFC_SQ_V_DIV_FIXUP_F32                             0x15F
-#define     V_008DFC_SQ_V_DIV_FIXUP_F64                             0x160
-#define     V_008DFC_SQ_V_LSHL_B64                                  0x161
-#define     V_008DFC_SQ_V_LSHR_B64                                  0x162
-#define     V_008DFC_SQ_V_ASHR_I64                                  0x163
-#define     V_008DFC_SQ_V_ADD_F64                                   0x164
-#define     V_008DFC_SQ_V_MUL_F64                                   0x165
-#define     V_008DFC_SQ_V_MIN_F64                                   0x166
-#define     V_008DFC_SQ_V_MAX_F64                                   0x167
-#define     V_008DFC_SQ_V_LDEXP_F64                                 0x168
-#define     V_008DFC_SQ_V_MUL_LO_U32                                0x169
-#define     V_008DFC_SQ_V_MUL_HI_U32                                0x16A
-#define     V_008DFC_SQ_V_MUL_LO_I32                                0x16B
-#define     V_008DFC_SQ_V_MUL_HI_I32                                0x16C
-#define     V_008DFC_SQ_V_DIV_SCALE_F32                             0x16D
-#define     V_008DFC_SQ_V_DIV_SCALE_F64                             0x16E
-#define     V_008DFC_SQ_V_DIV_FMAS_F32                              0x16F
-#define     V_008DFC_SQ_V_DIV_FMAS_F64                              0x170
-#define     V_008DFC_SQ_V_MSAD_U8                                   0x171
-#define     V_008DFC_SQ_V_QSAD_U8                                   0x172
-#define     V_008DFC_SQ_V_MQSAD_U8                                  0x173
-#define     V_008DFC_SQ_V_TRIG_PREOP_F64                            0x174
-/* CIK */
-#define     V_008DFC_SQ_V_MQSAD_U32_U8                              0x175
-#define     V_008DFC_SQ_V_MAD_U64_U32                               0x176
-#define     V_008DFC_SQ_V_MAD_I64_I32                               0x177
-/*     */
-#define     V_008DFC_SQ_V_OP1_OFFSET                                0x180
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_VOP3_FIELD                              0x34
-#define R_008DFC_SQ_MUBUF_0                                             0x008DFC
-#define   S_008DFC_OFFSET(x)                                          (((x) & 0xFFF) << 0)
-#define   G_008DFC_OFFSET(x)                                          (((x) >> 0) & 0xFFF)
-#define   C_008DFC_OFFSET                                             0xFFFFF000
-#define   S_008DFC_OFFEN(x)                                           (((x) & 0x1) << 12)
-#define   G_008DFC_OFFEN(x)                                           (((x) >> 12) & 0x1)
-#define   C_008DFC_OFFEN                                              0xFFFFEFFF
-#define   S_008DFC_IDXEN(x)                                           (((x) & 0x1) << 13)
-#define   G_008DFC_IDXEN(x)                                           (((x) >> 13) & 0x1)
-#define   C_008DFC_IDXEN                                              0xFFFFDFFF
-#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 14)
-#define   G_008DFC_GLC(x)                                             (((x) >> 14) & 0x1)
-#define   C_008DFC_GLC                                                0xFFFFBFFF
-#define   S_008DFC_ADDR64(x)                                          (((x) & 0x1) << 15)
-#define   G_008DFC_ADDR64(x)                                          (((x) >> 15) & 0x1)
-#define   C_008DFC_ADDR64                                             0xFFFF7FFF
-#define   S_008DFC_LDS(x)                                             (((x) & 0x1) << 16)
-#define   G_008DFC_LDS(x)                                             (((x) >> 16) & 0x1)
-#define   C_008DFC_LDS                                                0xFFFEFFFF
-#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 18)
-#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0x7F)
-#define   C_008DFC_OP                                                 0xFE03FFFF
-#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_X                        0x00
-#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY                       0x01
-#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ                      0x02
-#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW                     0x03
-#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_X                       0x04
-#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_XY                      0x05
-#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ                     0x06
-#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW                    0x07
-#define     V_008DFC_SQ_BUFFER_LOAD_UBYTE                           0x08
-#define     V_008DFC_SQ_BUFFER_LOAD_SBYTE                           0x09
-#define     V_008DFC_SQ_BUFFER_LOAD_USHORT                          0x0A
-#define     V_008DFC_SQ_BUFFER_LOAD_SSHORT                          0x0B
-#define     V_008DFC_SQ_BUFFER_LOAD_DWORD                           0x0C
-#define     V_008DFC_SQ_BUFFER_LOAD_DWORDX2                         0x0D
-#define     V_008DFC_SQ_BUFFER_LOAD_DWORDX4                         0x0E
-/* CIK */
-#define     V_008DFC_SQ_BUFFER_LOAD_DWORDX3                         0x0F
-/*     */
-#define     V_008DFC_SQ_BUFFER_STORE_BYTE                           0x18
-#define     V_008DFC_SQ_BUFFER_STORE_SHORT                          0x1A
-#define     V_008DFC_SQ_BUFFER_STORE_DWORD                          0x1C
-#define     V_008DFC_SQ_BUFFER_STORE_DWORDX2                        0x1D
-#define     V_008DFC_SQ_BUFFER_STORE_DWORDX4                        0x1E
-/* CIK */
-#define     V_008DFC_SQ_BUFFER_STORE_DWORDX3                        0x1F
-/*     */
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SWAP                          0x30
-#define     V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP                       0x31
-#define     V_008DFC_SQ_BUFFER_ATOMIC_ADD                           0x32
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SUB                           0x33
-#define     V_008DFC_SQ_BUFFER_ATOMIC_RSUB                          0x34 /* not on CIK */
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SMIN                          0x35
-#define     V_008DFC_SQ_BUFFER_ATOMIC_UMIN                          0x36
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SMAX                          0x37
-#define     V_008DFC_SQ_BUFFER_ATOMIC_UMAX                          0x38
-#define     V_008DFC_SQ_BUFFER_ATOMIC_AND                           0x39
-#define     V_008DFC_SQ_BUFFER_ATOMIC_OR                            0x3A
-#define     V_008DFC_SQ_BUFFER_ATOMIC_XOR                           0x3B
-#define     V_008DFC_SQ_BUFFER_ATOMIC_INC                           0x3C
-#define     V_008DFC_SQ_BUFFER_ATOMIC_DEC                           0x3D
-#define     V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP                      0x3E
-#define     V_008DFC_SQ_BUFFER_ATOMIC_FMIN                          0x3F
-#define     V_008DFC_SQ_BUFFER_ATOMIC_FMAX                          0x40
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2                       0x50
-#define     V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2                    0x51
-#define     V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2                        0x52
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2                        0x53
-#define     V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2                       0x54 /* not on CIK */
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2                       0x55
-#define     V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2                       0x56
-#define     V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2                       0x57
-#define     V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2                       0x58
-#define     V_008DFC_SQ_BUFFER_ATOMIC_AND_X2                        0x59
-#define     V_008DFC_SQ_BUFFER_ATOMIC_OR_X2                         0x5A
-#define     V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2                        0x5B
-#define     V_008DFC_SQ_BUFFER_ATOMIC_INC_X2                        0x5C
-#define     V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2                        0x5D
-#define     V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2                   0x5E
-#define     V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2                       0x5F
-#define     V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2                       0x60
-#define     V_008DFC_SQ_BUFFER_WBINVL1_SC                           0x70
-/* CIK */
-#define     V_008DFC_SQ_BUFFER_WBINVL1_VOL                          0x70
-/*     */
-#define     V_008DFC_SQ_BUFFER_WBINVL1                              0x71
-#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
-#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
-#define   C_008DFC_ENCODING                                           0x03FFFFFF
-#define     V_008DFC_SQ_ENC_MUBUF_FIELD                             0x38
-#endif
 #define R_030E00_TA_CS_BC_BASE_ADDR                                     0x030E00
 #define R_030E04_TA_CS_BC_BASE_ADDR_HI                                  0x030E04
 #define   S_030E04_ADDRESS(x)                                         (((x) & 0xFF) << 0)
 #define   G_00936C_EN_B(x)                                            (((x) >> 31) & 0x1)
 #define   C_00936C_EN_B                                               0x7FFFFFFF
 #define R_00950C_TA_CS_BC_BASE_ADDR                                     0x00950C
-/* CIK */
-#define R_030E00_TA_CS_BC_BASE_ADDR                                     0x030E00
-#define R_030E04_TA_CS_BC_BASE_ADDR_HI                                  0x030E04
-#define   S_030E04_ADDRESS(x)                                         (((x) & 0xFF) << 0)
-#define   G_030E04_ADDRESS(x)                                         (((x) >> 0) & 0xFF)
-#define   C_030E04_ADDRESS                                            0xFFFFFF00
-/*     */
 #define R_009858_DB_SUBTILE_CONTROL                                     0x009858
 #define   S_009858_MSAA1_X(x)                                         (((x) & 0x03) << 0)
 #define   G_009858_MSAA1_X(x)                                         (((x) >> 0) & 0x03)