remove zscale specific tests

diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index 6a53e7f6384ea3453ed66464a0c8c99a1def096a..024a9a013259e5488369b2a2e6419fc90f19ce52 100644 (file)
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -6,15 +6,12 @@ rv32si_sc_tests = \
        csr \
        shamt \
        ma_fetch \
-       fa_fetch_zscale_8192 \
        illegal \
        privileged \
        scall \
        sbreak \
        ma_addr \
-       fa_addr_zscale_8192 \
        timer \
-       ipi_zscale \
 
 rv32si_mc_tests = \
        ipi \

diff --git a/isa/rv32si/fa_addr_zscale_8192.S b/isa/rv32si/fa_addr_zscale_8192.S
deleted file mode 100644 (file)
index 37b6edf..0000000
--- a/isa/rv32si/fa_addr_zscale_8192.S
+++ /dev/null
@@ -1,94 +0,0 @@
-#*****************************************************************************
-# fa_addr.S
-#-----------------------------------------------------------------------------
-#
-# Test fault load/store trap.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  li s0, 0x2000
-  li s1, 1
-
-loop:
-  addi s1, s1, -1
-
-  la t0, evec_load
-  csrw evec, t0
-
-  li TESTNUM, 2
-  lw x0, 0(s0)
-  j fail
-
-  li TESTNUM, 3
-  lh x0, 0(s0)
-  j fail
-
-  li TESTNUM, 4
-  lhu x0, 0(s0)
-  j fail
-
-  li TESTNUM, 5
-  lb x0, 0(s0)
-  j fail
-
-  li TESTNUM, 6
-  lbu x0, 0(s0)
-  j fail
-
-  la t0, evec_store
-  csrw evec, t0
-
-  li TESTNUM, 7
-  sw x0, 0(s0)
-  j fail
-
-  li TESTNUM, 8
-  sh x0, 0(s0)
-  j fail
-
-  li TESTNUM, 9
-  sb x0, 0(s0)
-  j fail
-
-  li s0, 0xbad1dea0
-  beq s1, x0, loop
-
-  li TESTNUM, 10
-  li s0, 0x1ffc
-  lw x0, 0(s0) // if an exception is taken, then would fail because evec is set to evec_store
-
-  j pass // this time it should pass
-
-  TEST_PASSFAIL
-
-evec_load:
-  li t1, CAUSE_FAULT_LOAD
-  csrr t0, cause
-  bne t0, t1, fail
-  csrr t0, epc
-  addi t0, t0, 8
-  csrw epc, t0
-  sret
-
-evec_store:
-  li t1, CAUSE_FAULT_STORE
-  csrr t0, cause
-  bne t0, t1, fail
-  csrr t0, epc
-  addi t0, t0, 8
-  csrw epc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END

diff --git a/isa/rv32si/fa_fetch_zscale_8192.S b/isa/rv32si/fa_fetch_zscale_8192.S
deleted file mode 100644 (file)
index b7cde4e..0000000
--- a/isa/rv32si/fa_fetch_zscale_8192.S
+++ /dev/null
@@ -1,47 +0,0 @@
-#*****************************************************************************
-# fa_fetch.S
-#-----------------------------------------------------------------------------
-#
-# Test fault fetch trap.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, evec
-  csrw evec, t0
-
-  li TESTNUM, 2
-  li t0, 0x2000
-  jr t0
-  j fail
-
-  li TESTNUM, 3
-  li t0, 0xcafebabc
-  jr t0
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-evec:
-  li t1, CAUSE_FAULT_FETCH
-  csrr t0, cause
-  bne t0, t1, fail
-  csrr t0, epc
-  addi t0, t0, 8
-  csrw epc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END

diff --git a/isa/rv32si/ipi_zscale.S b/isa/rv32si/ipi_zscale.S
deleted file mode 100644 (file)
index 5f1106b..0000000
--- a/isa/rv32si/ipi_zscale.S
+++ /dev/null
@@ -1,48 +0,0 @@
-#*****************************************************************************
-# ipi.S
-#-----------------------------------------------------------------------------
-#
-# Test ipi interrupt.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, evec
-  csrw evec, t0
-
-  csrw clear_ipi, x0
-  li t1, 1<<21
-  csrs status, t1 # turn on timer IRQ 5
-  csrsi status, 4 # enable interrupts
-
-  li t1,1
-  csrw send_ipi, t1
-
-  li TESTNUM, 2
-  li a0,1000
-loop:
-  div x0, x0, x0
-  addi a0, a0, -1
-  bne a0, x0, loop
-  j fail # assumption is that you will get an ipi before this loop ends
-
-  TEST_PASSFAIL
-
-evec:
-  li t1, 0x80000000|IRQ_IPI
-  csrr t0, cause
-  bne t0, t1, fail
-  j pass
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END