Minor fixes in handling of "init" attribute

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0d667c638f9aab5efaf782c119215b9b28f0325c..c6d595c3831d313307c66eddb6edeb0b3d45b8f5 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -295,15 +295,15 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
                f << stringf("%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
        if (wire->port_input && wire->port_output)
                f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
-       if (reg_wires.count(wire->name))
+       if (reg_wires.count(wire->name)) {
                f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
-       else if (!wire->port_input && !wire->port_output)
+               if (wire->attributes.count("\\init")) {
+                       f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
+                       dump_const(f, wire->attributes.at("\\init"));
+                       f << stringf(";\n");
+               }
+       } else if (!wire->port_input && !wire->port_output)
                f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
-       if (wire->attributes.count("\\init")) {
-               f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
-               dump_const(f, wire->attributes.at("\\init"));
-               f << stringf(";\n");
-       }
 #endif
 }
 

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 27c6b3bcf6346d15351fe1c50cb0e4ce964131ef..1f08ab0423c5b8c8f658a38c3d6697b74b262a68 100644 (file)
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -244,6 +244,7 @@ struct ProcArstPass : public Pass {
                }
 
                extra_args(args, argidx, design);
+               pool<Wire*> delete_initattr_wires;
 
                for (auto mod : design->modules())
                        if (design->selected(mod)) {
@@ -265,6 +266,7 @@ struct ProcArstPass : public Pass {
                                                                                value.extend_u0(chunk.wire->width, false);
                                                                                arst_sig.append(chunk);
                                                                                arst_val.append(value.extract(chunk.offset, chunk.width));
+                                                                               delete_initattr_wires.insert(chunk.wire);
                                                                        }
                                                                if (arst_sig.size()) {
                                                                        log("Added global reset to process %s: %s <- %s\n",
@@ -281,6 +283,9 @@ struct ProcArstPass : public Pass {
                                        }
                                }
                        }
+
+               for (auto wire : delete_initattr_wires)
+                       wire->attributes.erase("\\init");
        }
 } ProcArstPass;