---------- Begin Simulation Statistics ----------
-sim_seconds 0.000247 # Number of seconds simulated
-sim_ticks 246648467 # Number of ticks simulated
-final_tick 246648467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000757 # Number of seconds simulated
+sim_ticks 757091500 # Number of ticks simulated
+final_tick 757091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 1526116 # Simulator tick rate (ticks/s)
-host_mem_usage 347672 # Number of bytes of host memory used
-host_seconds 161.62 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 85584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 85024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 83876 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 80921 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 79699 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 87892 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 84658 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 85643 # Number of bytes read from this memory
-system.physmem.bytes_read::total 673297 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 432320 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5346 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5458 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5415 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5191 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5426 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5272 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5284 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5390 # Number of bytes written to this memory
-system.physmem.bytes_written::total 475102 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10992 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11251 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10985 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10991 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11158 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11074 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10988 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 88405 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6755 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5346 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5458 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5415 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5191 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5426 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5272 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5284 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5390 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49537 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 346987764 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 344717326 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 340062929 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 328082315 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 323127895 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 356345211 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 343233433 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 347226971 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2729783843 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1752777973 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 21674572 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 22128660 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 21954323 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 21046147 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 21998920 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 21374550 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 21423202 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 21852964 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1926231311 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1752777973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 368662336 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 366845986 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 362017251 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 349128462 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 345126816 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 377719761 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 364656635 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 369079934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4656015154 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 13761 # number of replacements
-system.l2c.tagsinuse 783.393170 # Cycle average of tags in use
-system.l2c.total_refs 148641 # Total number of references to valid blocks.
-system.l2c.sampled_refs 14595 # Sample count of references to valid blocks.
-system.l2c.avg_refs 10.184378 # Average number of references to valid blocks.
+host_tick_rate 129668365 # Simulator tick rate (ticks/s)
+host_mem_usage 347944 # Number of bytes of host memory used
+host_seconds 5.84 # Real time elapsed on the host
+system.physmem.bytes_read::cpu0 90255 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 89097 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 89397 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 87447 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 92253 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 92127 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 87941 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 90122 # Number of bytes read from this memory
+system.physmem.bytes_read::total 718639 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 466688 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5395 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5319 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5314 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5343 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5295 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5581 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5197 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5320 # Number of bytes written to this memory
+system.physmem.bytes_written::total 509452 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11064 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10977 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11217 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11361 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11298 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11018 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11057 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 89080 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 7292 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5395 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5319 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5314 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5343 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5295 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5581 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5197 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5320 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50056 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 119212803 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 117683265 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 118079519 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 115503872 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 121851850 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 121685424 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 116156369 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 119037131 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 949210234 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 616422189 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 7125955 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 7025571 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 7018967 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 7057271 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 6993871 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 7371632 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 6864428 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 7026892 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 672906775 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 616422189 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 126338758 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 124708836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 125098485 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 122561144 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 128845721 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 129057056 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 123020797 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 126064023 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1622117010 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 15543 # number of replacements
+system.l2c.tagsinuse 804.498263 # Cycle average of tags in use
+system.l2c.total_refs 151705 # Total number of references to valid blocks.
+system.l2c.sampled_refs 16364 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.270655 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 713.127960 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0 9.028795 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1 9.232836 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2 8.886797 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3 8.220590 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu4 8.019568 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu5 9.223605 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu6 8.901601 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu7 8.751418 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.696414 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0 0.008817 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1 0.009016 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2 0.008679 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3 0.008028 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu4 0.007832 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu5 0.009007 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu6 0.008693 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu7 0.008546 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.765032 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0 10550 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1 10636 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2 10602 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3 10831 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 10494 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5 10789 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6 10661 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10646 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 85209 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 74327 # number of Writeback hits
-system.l2c.Writeback_hits::total 74327 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 356 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 351 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 332 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 356 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 355 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 319 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 329 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 315 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2713 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 1919 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 1876 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 1912 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1869 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1927 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1872 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1860 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1792 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 15027 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0 12469 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1 12512 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2 12514 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12700 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 12421 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12661 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12521 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12438 # number of demand (read+write) hits
-system.l2c.demand_hits::total 100236 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0 12469 # number of overall hits
-system.l2c.overall_hits::cpu1 12512 # number of overall hits
-system.l2c.overall_hits::cpu2 12514 # number of overall hits
-system.l2c.overall_hits::cpu3 12700 # number of overall hits
-system.l2c.overall_hits::cpu4 12421 # number of overall hits
-system.l2c.overall_hits::cpu5 12661 # number of overall hits
-system.l2c.overall_hits::cpu6 12521 # number of overall hits
-system.l2c.overall_hits::cpu7 12438 # number of overall hits
-system.l2c.overall_hits::total 100236 # number of overall hits
-system.l2c.ReadReq_misses::cpu0 776 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1 788 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2 764 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3 734 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4 693 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5 810 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6 788 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7 783 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 6136 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0 1809 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1 1871 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2 1852 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 1912 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1931 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1910 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1892 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1902 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 15079 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0 4399 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1 4186 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2 4344 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3 4229 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5 4382 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6 4394 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7 4423 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0 5175 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1 4974 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2 5108 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3 4963 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4 4979 # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu6 5182 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7 5206 # number of demand (read+write) misses
-system.l2c.demand_misses::total 40779 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0 5175 # number of overall misses
-system.l2c.overall_misses::cpu1 4974 # number of overall misses
-system.l2c.overall_misses::cpu2 5108 # number of overall misses
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-system.l2c.overall_misses::cpu4 4979 # number of overall misses
-system.l2c.overall_misses::cpu5 5192 # number of overall misses
-system.l2c.overall_misses::cpu6 5182 # number of overall misses
-system.l2c.overall_misses::cpu7 5206 # number of overall misses
-system.l2c.overall_misses::total 40779 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0 66915276 # number of ReadReq miss cycles
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-system.l2c.ReadReq_miss_latency::cpu2 71963353 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3 67802640 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4 62502773 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5 69794204 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6 71972090 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7 71352329 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 549397675 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0 52428990 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1 52180496 # number of UpgradeReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::cpu3 53430258 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4 54911535 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5 54472253 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6 52324574 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7 51552168 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 422857100 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0 245296624 # number of ReadExReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu2 237706545 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3 232669020 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4 238760287 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5 246249803 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6 240187312 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7 245760610 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 1921517523 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0 312211900 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1 301982332 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2 309669898 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3 300471660 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4 301263060 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5 316044007 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6 312159402 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7 317112939 # number of demand (read+write) miss cycles
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844363 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.849638 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.840396 # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.num_reads 98266 # number of read accesses completed
-system.cpu0.num_writes 53265 # number of write accesses completed
+system.cpu0.num_reads 98965 # number of read accesses completed
+system.cpu0.num_writes 53188 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.replacements 21972 # number of replacements
-system.cpu0.l1c.tagsinuse 389.500163 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 12866 # Total number of references to valid blocks.
-system.cpu0.l1c.sampled_refs 22378 # Sample count of references to valid blocks.
-system.cpu0.l1c.avg_refs 0.574940 # Average number of references to valid blocks.
+system.cpu0.l1c.replacements 22322 # number of replacements
+system.cpu0.l1c.tagsinuse 389.061969 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 13312 # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs 22723 # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs 0.585838 # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.occ_blocks::cpu0 389.500163 # Average occupied blocks per requestor
-system.cpu0.l1c.occ_percent::cpu0 0.760743 # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::total 0.760743 # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits::cpu0 8421 # number of ReadReq hits
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-system.cpu0.l1c.ReadReq_accesses::cpu0 44109 # number of ReadReq accesses(hits+misses)
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 873984178 # number of WriteReq MSHR miss cycles
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-system.cpu0.l1c.demand_mshr_miss_latency::total 1850244182 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1850244182 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1850244182 # number of overall MSHR miss cycles
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.num_copies 0 # number of copy accesses completed
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-system.cpu1.l1c.avg_refs 0.601263 # Average number of references to valid blocks.
+system.cpu1.l1c.replacements 21605 # number of replacements
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system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.l1c.demand_avg_miss_latency::total 32406.192894 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 32406.192894 # average overall miss latency
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+system.cpu1.l1c.overall_hits::total 9592 # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1 35254 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total 35254 # number of ReadReq misses
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+system.cpu1.l1c.overall_misses::total 57881 # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1 4617875359 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total 4617875359 # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1 3138675137 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total 3138675137 # number of WriteReq miss cycles
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+system.cpu1.l1c.demand_miss_latency::total 7756550496 # number of demand (read+write) miss cycles
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+system.cpu1.l1c.overall_miss_latency::total 7756550496 # number of overall miss cycles
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+system.cpu1.l1c.ReadReq_accesses::total 43788 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 23685 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 23685 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 67473 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 67473 # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1 67473 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total 67473 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805106 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.805106 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955330 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.955330 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.857839 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.857839 # miss rate for demand accesses
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+system.cpu1.l1c.overall_miss_rate::total 0.857839 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 130988.692319 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 130988.692319 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 138713.710921 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 138713.710921 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 134008.577875 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 134008.577875 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 134008.577875 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 134008.577875 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 723339270 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 53052 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 62977 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3262.141691 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11485.768932 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9480 # number of writebacks
-system.cpu1.l1c.writebacks::total 9480 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22917 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 22917 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 58680 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 58680 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 58680 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 58680 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 979228369 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 979228369 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 863458324 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 863458324 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1842686693 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1842686693 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1842686693 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1842686693 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740677115 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740677115 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 739780589 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 739780589 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480457704 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480457704 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.801555 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.801555 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956429 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956429 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.855668 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.855668 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 27381.046584 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 27381.046584 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37677.633373 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37677.633373 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency
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+system.cpu1.l1c.writebacks::total 9483 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4547061522 # number of ReadReq MSHR miss cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2297084263 # number of overall MSHR uncacheable cycles
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+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805106 # mshr miss rate for ReadReq accesses
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+system.cpu1.l1c.demand_mshr_miss_rate::total 0.857839 # mshr miss rate for demand accesses
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+system.cpu1.l1c.overall_mshr_miss_rate::total 0.857839 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 128980.017076 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 128980.017076 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 136711.109206 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 136711.109206 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 98639 # number of read accesses completed
-system.cpu2.num_writes 53360 # number of write accesses completed
+system.cpu2.num_reads 98360 # number of read accesses completed
+system.cpu2.num_writes 53068 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.replacements 21788 # number of replacements
-system.cpu2.l1c.tagsinuse 389.777022 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 12892 # Total number of references to valid blocks.
-system.cpu2.l1c.sampled_refs 22192 # Sample count of references to valid blocks.
-system.cpu2.l1c.avg_refs 0.580930 # Average number of references to valid blocks.
+system.cpu2.l1c.replacements 22096 # number of replacements
+system.cpu2.l1c.tagsinuse 389.724593 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 13250 # Total number of references to valid blocks.
+system.cpu2.l1c.sampled_refs 22502 # Sample count of references to valid blocks.
+system.cpu2.l1c.avg_refs 0.588837 # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::cpu2 389.777022 # Average occupied blocks per requestor
-system.cpu2.l1c.occ_percent::cpu2 0.761283 # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::total 0.761283 # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits::cpu2 8419 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8419 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1037 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1037 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9456 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9456 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9456 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9456 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 22886 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 22886 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 58678 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 58678 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 58678 # number of overall misses
-system.cpu2.l1c.overall_misses::total 58678 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 1023256428 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 1023256428 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 895299843 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 895299843 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 1918556271 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 1918556271 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 1918556271 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 1918556271 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44211 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 44211 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 23923 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 23923 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 68134 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 68134 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 68134 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 68134 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809572 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.809572 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.956653 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.956653 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.861215 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.861215 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.861215 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.861215 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 28588.970384 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 28588.970384 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 39119.979158 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 39119.979158 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 32696.347370 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 32696.347370 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 32696.347370 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 32696.347370 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 172516137 # number of cycles access was blocked
+system.cpu2.l1c.occ_blocks::cpu2 389.724593 # Average occupied blocks per requestor
+system.cpu2.l1c.occ_percent::cpu2 0.761181 # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::total 0.761181 # Average percentage of cache occupancy
+system.cpu2.l1c.ReadReq_hits::cpu2 8687 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8687 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2 9808 # number of demand (read+write) hits
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+system.cpu2.l1c.overall_hits::total 9808 # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2 35624 # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total 35624 # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2 22874 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total 22874 # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2 58498 # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total 58498 # number of demand (read+write) misses
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+system.cpu2.l1c.overall_misses::total 58498 # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2 4545456138 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total 4545456138 # number of ReadReq miss cycles
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+system.cpu2.l1c.WriteReq_miss_latency::total 3151736803 # number of WriteReq miss cycles
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+system.cpu2.l1c.demand_miss_latency::total 7697192941 # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2 7697192941 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total 7697192941 # number of overall miss cycles
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+system.cpu2.l1c.ReadReq_accesses::total 44311 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 23995 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 23995 # number of WriteReq accesses(hits+misses)
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+system.cpu2.l1c.demand_accesses::total 68306 # number of demand (read+write) accesses
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+system.cpu2.l1c.overall_accesses::total 68306 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803954 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.803954 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953282 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.953282 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.856411 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.856411 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.856411 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.856411 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 127595.332865 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 127595.332865 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 137786.867317 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 137786.867317 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 131580.446186 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 131580.446186 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 131580.446186 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 131580.446186 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 716129194 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 52707 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 63633 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3273.116227 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11254.053620 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9481 # number of writebacks
-system.cpu2.l1c.writebacks::total 9481 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22886 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 22886 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 58678 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 58678 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 58678 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 58678 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 987321254 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 987321254 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 872322294 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 872322294 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1859643548 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1859643548 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1859643548 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1859643548 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722326579 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722326579 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 745926521 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 745926521 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1468253100 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1468253100 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809572 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809572 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.956653 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.956653 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.861215 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.861215 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 27584.970217 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 27584.970217 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 38115.978939 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 38115.978939 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks 9686 # number of writebacks
+system.cpu2.l1c.writebacks::total 9686 # number of writebacks
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+system.cpu2.l1c.ReadReq_mshr_misses::total 35624 # number of ReadReq MSHR misses
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+system.cpu2.l1c.demand_mshr_misses::total 58498 # number of demand (read+write) MSHR misses
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+system.cpu2.l1c.overall_mshr_misses::total 58498 # number of overall MSHR misses
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+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1379555288 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 954692892 # number of WriteReq MSHR uncacheable cycles
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+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334248180 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803954 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803954 # mshr miss rate for ReadReq accesses
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+system.cpu2.l1c.demand_mshr_miss_rate::total 0.856411 # mshr miss rate for demand accesses
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+system.cpu2.l1c.overall_mshr_miss_rate::total 0.856411 # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 125586.088929 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 125586.088929 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 135784.054123 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 135784.054123 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.num_reads 100000 # number of read accesses completed
-system.cpu3.num_writes 53214 # number of write accesses completed
+system.cpu3.num_writes 53600 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.replacements 22201 # number of replacements
-system.cpu3.l1c.tagsinuse 390.202631 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 13426 # Total number of references to valid blocks.
-system.cpu3.l1c.sampled_refs 22601 # Sample count of references to valid blocks.
-system.cpu3.l1c.avg_refs 0.594045 # Average number of references to valid blocks.
+system.cpu3.l1c.replacements 22673 # number of replacements
+system.cpu3.l1c.tagsinuse 391.747074 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 13403 # Total number of references to valid blocks.
+system.cpu3.l1c.sampled_refs 23070 # Sample count of references to valid blocks.
+system.cpu3.l1c.avg_refs 0.580971 # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.occ_blocks::cpu3 390.202631 # Average occupied blocks per requestor
-system.cpu3.l1c.occ_percent::cpu3 0.762115 # Average percentage of cache occupancy
-system.cpu3.l1c.occ_percent::total 0.762115 # Average percentage of cache occupancy
-system.cpu3.l1c.ReadReq_hits::cpu3 8779 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8779 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1080 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1080 # number of WriteReq hits
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-system.cpu3.l1c.overall_hits::total 9859 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36255 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36255 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 22971 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 22971 # number of WriteReq misses
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-system.cpu3.l1c.demand_misses::total 59226 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 59226 # number of overall misses
-system.cpu3.l1c.overall_misses::total 59226 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 1029467396 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 1029467396 # number of ReadReq miss cycles
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-system.cpu3.l1c.WriteReq_miss_latency::total 892890764 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 1922358160 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 1922358160 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 1922358160 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 1922358160 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45034 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45034 # number of ReadReq accesses(hits+misses)
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-system.cpu3.l1c.WriteReq_accesses::total 24051 # number of WriteReq accesses(hits+misses)
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-system.cpu3.l1c.overall_accesses::total 69085 # number of overall (read+write) accesses
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-system.cpu3.l1c.ReadReq_miss_rate::total 0.805058 # miss rate for ReadReq accesses
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-system.cpu3.l1c.demand_miss_rate::total 0.857292 # miss rate for demand accesses
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-system.cpu3.l1c.overall_miss_rate::total 0.857292 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 28395.184002 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 28395.184002 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38870.348004 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 38870.348004 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 32458.011009 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 32458.011009 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 32458.011009 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 32458.011009 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 173404945 # number of cycles access was blocked
+system.cpu3.l1c.occ_blocks::cpu3 391.747074 # Average occupied blocks per requestor
+system.cpu3.l1c.occ_percent::cpu3 0.765131 # Average percentage of cache occupancy
+system.cpu3.l1c.occ_percent::total 0.765131 # Average percentage of cache occupancy
+system.cpu3.l1c.ReadReq_hits::cpu3 8720 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total 8720 # number of ReadReq hits
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+system.cpu3.l1c.WriteReq_hits::total 1143 # number of WriteReq hits
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+system.cpu3.l1c.overall_hits::total 9863 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 36203 # number of ReadReq misses
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+system.cpu3.l1c.WriteReq_misses::total 22978 # number of WriteReq misses
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+system.cpu3.l1c.overall_misses::total 59181 # number of overall misses
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+system.cpu3.l1c.WriteReq_miss_latency::total 3121949330 # number of WriteReq miss cycles
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+system.cpu3.l1c.overall_miss_latency::total 7727321059 # number of overall miss cycles
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+system.cpu3.l1c.ReadReq_accesses::total 44923 # number of ReadReq accesses(hits+misses)
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+system.cpu3.l1c.WriteReq_accesses::total 24121 # number of WriteReq accesses(hits+misses)
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+system.cpu3.l1c.overall_accesses::total 69044 # number of overall (read+write) accesses
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+system.cpu3.l1c.ReadReq_miss_rate::total 0.805890 # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952614 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total 0.952614 # miss rate for WriteReq accesses
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+system.cpu3.l1c.demand_miss_rate::total 0.857149 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.857149 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.857149 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 127209.671270 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 127209.671270 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135866.887022 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 135866.887022 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 130570.978169 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 130570.978169 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 130570.978169 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 130570.978169 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 721076565 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 53526 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 64491 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3239.639521 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11181.041773 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9609 # number of writebacks
-system.cpu3.l1c.writebacks::total 9609 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36255 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22971 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 22971 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 59226 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 59226 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 59226 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 59226 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 993072387 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 993072387 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869829882 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869829882 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1862902269 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 1862902269 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1862902269 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1862902269 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723358193 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723358193 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 722023340 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 722023340 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1445381533 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1445381533 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805058 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805058 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955095 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955095 # mshr miss rate for WriteReq accesses
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-system.cpu3.l1c.demand_mshr_miss_rate::total 0.857292 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.857292 # mshr miss rate for overall accesses
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-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 27391.322218 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37866.435157 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37866.435157 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency
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+system.cpu3.l1c.writebacks::total 9961 # number of writebacks
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+system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22978 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total 22978 # number of WriteReq MSHR misses
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+system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4532659362 # number of ReadReq MSHR miss cycles
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+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 125201.208795 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133863.956132 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133863.956132 # average WriteReq mshr miss latency
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+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 98672 # number of read accesses completed
-system.cpu4.num_writes 53449 # number of write accesses completed
+system.cpu4.num_reads 99186 # number of read accesses completed
+system.cpu4.num_writes 53232 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.replacements 21899 # number of replacements
-system.cpu4.l1c.tagsinuse 389.567143 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 13162 # Total number of references to valid blocks.
-system.cpu4.l1c.sampled_refs 22307 # Sample count of references to valid blocks.
-system.cpu4.l1c.avg_refs 0.590039 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 22556 # number of replacements
+system.cpu4.l1c.tagsinuse 391.523203 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 13363 # Total number of references to valid blocks.
+system.cpu4.l1c.sampled_refs 22976 # Sample count of references to valid blocks.
+system.cpu4.l1c.avg_refs 0.581607 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.occ_blocks::cpu4 389.567143 # Average occupied blocks per requestor
-system.cpu4.l1c.occ_percent::cpu4 0.760873 # Average percentage of cache occupancy
-system.cpu4.l1c.occ_percent::total 0.760873 # Average percentage of cache occupancy
-system.cpu4.l1c.ReadReq_hits::cpu4 8516 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8516 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1086 # number of WriteReq hits
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-system.cpu4.l1c.overall_hits::total 9602 # number of overall hits
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-system.cpu4.l1c.ReadReq_misses::total 35797 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 23063 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 23063 # number of WriteReq misses
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-system.cpu4.l1c.demand_misses::total 58860 # number of demand (read+write) misses
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-system.cpu4.l1c.overall_misses::total 58860 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 1014475710 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 1014475710 # number of ReadReq miss cycles
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-system.cpu4.l1c.WriteReq_miss_latency::total 905483061 # number of WriteReq miss cycles
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-system.cpu4.l1c.demand_miss_latency::total 1919958771 # number of demand (read+write) miss cycles
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-system.cpu4.l1c.overall_miss_latency::total 1919958771 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 44313 # number of ReadReq accesses(hits+misses)
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-system.cpu4.l1c.overall_accesses::total 68462 # number of overall (read+write) accesses
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-system.cpu4.l1c.ReadReq_miss_rate::total 0.807822 # miss rate for ReadReq accesses
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-system.cpu4.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_miss_rate::total 0.859747 # miss rate for demand accesses
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-system.cpu4.l1c.overall_miss_rate::total 0.859747 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 28339.685169 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 28339.685169 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 39261.286953 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 39261.286953 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 32619.075280 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 32619.075280 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 32619.075280 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 32619.075280 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 173090211 # number of cycles access was blocked
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+system.cpu4.l1c.occ_percent::total 0.764694 # Average percentage of cache occupancy
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+system.cpu4.l1c.ReadReq_hits::total 8704 # number of ReadReq hits
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+system.cpu4.l1c.overall_hits::total 9881 # number of overall hits
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+system.cpu4.l1c.ReadReq_misses::total 35925 # number of ReadReq misses
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+system.cpu4.l1c.overall_misses::total 58880 # number of overall misses
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+system.cpu4.l1c.ReadReq_miss_latency::total 4605243494 # number of ReadReq miss cycles
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+system.cpu4.l1c.WriteReq_accesses::total 24132 # number of WriteReq accesses(hits+misses)
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+system.cpu4.l1c.ReadReq_miss_rate::total 0.804970 # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951227 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total 0.951227 # miss rate for WriteReq accesses
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+system.cpu4.l1c.demand_miss_rate::total 0.856299 # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4 0.856299 # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total 0.856299 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 128190.493918 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 128190.493918 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 135313.432237 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 135313.432237 # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 130967.447877 # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 130967.447877 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 130967.447877 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 130967.447877 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 718630789 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 52926 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 64157 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3270.419284 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11201.128310 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9537 # number of writebacks
-system.cpu4.l1c.writebacks::total 9537 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35797 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 35797 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23063 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23063 # number of WriteReq MSHR misses
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-system.cpu4.l1c.demand_mshr_misses::total 58860 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 58860 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 58860 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 978543547 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 978543547 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 882330817 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 882330817 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1860874364 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 1860874364 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1860874364 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1860874364 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 726225983 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 726225983 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 739406150 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 739406150 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1465632133 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1465632133 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807822 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807822 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955029 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.859747 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.859747 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 27335.909350 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 27335.909350 # average ReadReq mshr miss latency
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-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 98938 # number of read accesses completed
-system.cpu5.num_writes 52979 # number of write accesses completed
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system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.replacements 22003 # number of replacements
-system.cpu5.l1c.tagsinuse 389.145531 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 13186 # Total number of references to valid blocks.
-system.cpu5.l1c.sampled_refs 22409 # Sample count of references to valid blocks.
-system.cpu5.l1c.avg_refs 0.588424 # Average number of references to valid blocks.
+system.cpu5.l1c.replacements 22776 # number of replacements
+system.cpu5.l1c.tagsinuse 391.477551 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 13322 # Total number of references to valid blocks.
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+system.cpu5.l1c.avg_refs 0.575539 # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu5.l1c.occ_percent::total 0.760050 # Average percentage of cache occupancy
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-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 28346.731655 # average ReadReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 32567.702492 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 32567.702492 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 32567.702492 # average overall miss latency
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+system.cpu5.l1c.occ_percent::total 0.764605 # Average percentage of cache occupancy
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+system.cpu5.l1c.demand_miss_rate::total 0.857186 # miss rate for demand accesses
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+system.cpu5.l1c.overall_miss_rate::total 0.857186 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 126495.185207 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 126495.185207 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 135560.394797 # average WriteReq miss latency
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+system.cpu5.l1c.overall_avg_miss_latency::cpu5 130027.245872 # average overall miss latency
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu5.l1c.writebacks::total 9578 # number of writebacks
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-system.cpu5.l1c.overall_mshr_misses::total 59064 # number of overall MSHR misses
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-system.cpu5.l1c.demand_mshr_miss_latency::total 1864286543 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1864286543 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1864286543 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 726267830 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 726267830 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 727074165 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 727074165 # number of WriteReq MSHR uncacheable cycles
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-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1453341995 # number of overall MSHR uncacheable cycles
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-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses
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-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.957048 # mshr miss rate for WriteReq accesses
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-system.cpu5.l1c.demand_mshr_miss_rate::total 0.859350 # mshr miss rate for demand accesses
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-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 27342.870383 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 27342.870383 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 38205.931242 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 38205.931242 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency
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+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 124486.113893 # average ReadReq mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 53264 # number of write accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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-system.cpu6.l1c.tagsinuse 389.196991 # Cycle average of tags in use
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-system.cpu6.l1c.avg_refs 0.592924 # Average number of references to valid blocks.
+system.cpu6.l1c.replacements 21524 # number of replacements
+system.cpu6.l1c.tagsinuse 387.796217 # Cycle average of tags in use
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system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu6.l1c.demand_mshr_miss_latency::total 1864786092 # number of demand (read+write) MSHR miss cycles
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu7.num_copies 0 # number of copy accesses completed
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system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
projects / gem5.git / commitdiff