ARM: Add in more bits for the mon mode.

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6341e6cd01f5f6e530469a0dfab46df5203e9969..f8359679b2ddd0e94496074147d44421f40bf4eb 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -63,6 +63,9 @@ namespace ArmISA
               case MODE_SVC:
                 intRegMap = IntRegSvcMap;
                 break;
+              case MODE_MON:
+                intRegMap = IntRegMonMap;
+                break;
               case MODE_ABORT:
                 intRegMap = IntRegAbtMap;
                 break;

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 3180669de334da800ca89ff497c46e541b9059e2..ba394d49c54ca125d6d2e3f9a4d70ec705e5a3bd 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -59,6 +59,7 @@ namespace ArmISA
         MISCREG_SPSR_FIQ,
         MISCREG_SPSR_IRQ,
         MISCREG_SPSR_SVC,
+        MISCREG_SPSR_MON,
         MISCREG_SPSR_UND,
         MISCREG_SPSR_ABT,
         MISCREG_FPSR,

diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 2c4e1291c06dc36454e700c76b6144544885c250..d5cc07eaf68d51edd50f1fd4097d23afea39f4f1 100644 (file)
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -156,6 +156,7 @@ namespace ArmISA
         MODE_FIQ = 17,
         MODE_IRQ = 18,
         MODE_SVC = 19,
+        MODE_MON = 22,
         MODE_ABORT = 23,
         MODE_UNDEFINED = 27,
         MODE_SYSTEM = 31