struct r600_command_buffer *cb = &rctx->start_cs_cmd;
int tmp, i;
- r600_init_command_buffer(cb, 341);
+ r600_init_command_buffer(cb, 338);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
- r600_store_context_reg(cb, R_028AB4_VGT_REUSE_OFF, 0);
-
r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
return;
}
- r600_init_command_buffer(cb, 341);
+ r600_init_command_buffer(cb, 338);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
- r600_store_context_reg(cb, R_028AB4_VGT_REUSE_OFF, 0);
-
r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
- r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
+ r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
{
if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
- current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable) {
- rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
- rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
- rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
- r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
+ current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
+ current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
+ rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
+ rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
+ rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
+ rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
+ r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
}
}
radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
state->pa_cl_vs_out_cntl |
(state->clip_plane_enable & state->clip_dist_write));
+ /* reuse needs to be set off if we write oViewport */
+ if (rctx->b.chip_class >= EVERGREEN)
+ radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
+ S_028AB4_REUSE_OFF(state->vs_out_viewport));
}
static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)