Added Xilinx test case for initialized brams

diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore
index bc2f8babf120527dbbf19773d8899673ae3db650..496b87461a7082c50b0f882f75ec5935c5ba3e8a 100644 (file)
--- a/techlibs/xilinx/tests/.gitignore
+++ b/techlibs/xilinx/tests/.gitignore
@@ -1,3 +1,6 @@
 bram1_cmp
 bram1.mk
 bram1_[0-9]*/
+bram2.log
+bram2_syn.v
+bram2_tb

diff --git a/techlibs/xilinx/tests/bram2.sh b/techlibs/xilinx/tests/bram2.sh
new file mode 100644 (file)
index 0000000..d8d8ed3
--- /dev/null
+++ b/techlibs/xilinx/tests/bram2.sh
@@ -0,0 +1,8 @@
+#!/bin/bash
+
+set -ex
+unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
+../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
+iverilog -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
+vvp -N bram2_tb
+

diff --git a/techlibs/xilinx/tests/bram2.v b/techlibs/xilinx/tests/bram2.v
new file mode 100644 (file)
index 0000000..9444fb1
--- /dev/null
+++ b/techlibs/xilinx/tests/bram2.v
@@ -0,0 +1,24 @@
+module myram(
+       input             rd_clk,
+       input      [ 7:0] rd_addr,
+       output reg [15:0] rd_data,
+       input             wr_clk,
+       input             wr_enable,
+       input      [ 7:0] wr_addr,
+       input      [15:0] wr_data
+);
+       reg [15:0] memory [0:255];
+       integer i;
+
+       initial begin
+               for (i = 0; i < 256; i = i+1)
+                       memory[i] = i;
+       end
+
+       always @(posedge rd_clk)
+               rd_data <= memory[rd_addr];
+
+       always @(posedge wr_clk)
+               if (wr_enable)
+                       memory[wr_addr] <= wr_data;
+endmodule

diff --git a/techlibs/xilinx/tests/bram2_tb.v b/techlibs/xilinx/tests/bram2_tb.v
new file mode 100644 (file)
index 0000000..3a43b65
--- /dev/null
+++ b/techlibs/xilinx/tests/bram2_tb.v
@@ -0,0 +1,45 @@
+`timescale 1 ns / 1 ps
+
+module testbench;
+       reg         rd_clk;
+       reg  [ 7:0] rd_addr;
+       wire [15:0] rd_data;
+
+       wire        wr_clk    = 0;
+       wire        wr_enable = 0;
+       wire [ 7:0] wr_addr   = 0;
+       wire [15:0] wr_data   = 0;
+
+       myram uut (
+               .rd_clk   (rd_clk   ),
+               .rd_addr  (rd_addr  ),
+               .rd_data  (rd_data  ),
+               .wr_clk   (wr_clk   ),
+               .wr_enable(wr_enable),
+               .wr_addr  (wr_addr  ),
+               .wr_data  (wr_data  )
+       );
+
+       initial begin
+               rd_clk = 0;
+               #1000;
+               forever #10 rd_clk <= ~rd_clk;
+       end
+
+       integer i;
+       initial begin
+               rd_addr <= 0;
+               @(posedge rd_clk);
+               for (i = 0; i < 256; i=i+1) begin
+                       rd_addr <= rd_addr + 1;
+                       @(posedge rd_clk);
+                       // $display("%3d %3d", i, rd_data);
+                       if (i != rd_data) begin
+                               $display("[%1t] ERROR: addr=%3d, data=%3d", $time, i, rd_data);
+                               $stop;
+                       end
+               end
+               $display("[%1t] Passed bram2 test.", $time);
+               $finish;
+       end
+endmodule