update to openlane-nmigen fork (thx lethalbit)

diff --git a/resources.mdwn b/resources.mdwn
index f7a1e0ea31fa6ed974edf28b73283c9fc41e1d68..155c2f2718ff3ec22b4920cfd8d2654f8c4bddb7 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -350,7 +350,7 @@ Some learning resources I found in the community:
   Understanding Latency Hiding on GPUs, by Vasily Volkov
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * example of openlane with nmigen
-  <https://gist.github.com/lethalbit/e65e296bc6a3810280d1b256c9df591b>
+  <https://github.com/lethalbit/nmigen/tree/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
 * Multi-read/write ported memories