mibuild/altera_quartus: enforce use of SystemVerilog in Quartus (Verilog does not...

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index cfda1cf06008bbe963a75f0f12bc614b80b2a43b..d2265b086e1df890383e0b90263145045ab3c4ff 100644 (file)
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -51,6 +51,9 @@ def _build_qsf(named_sc, named_pc):
 def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
        qsf_contents = ""
        for filename, language in sources:
+               # Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
+               if language == "verilog":
+                       language = "systemverilog"
                qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"
 
        for path in vincpaths: