case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
- S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
+ S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode) |
+ S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache0_bank) |
+ S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache1_bank);
bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
+ S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache1_mode) |
+ S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache0_addr) |
+ S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache1_addr) |
S_SQ_CF_ALU_WORD1_BARRIER(1) |
S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
break;
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
- S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
+ S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode) |
+ S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache0_bank) |
+ S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache1_bank);
bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
+ S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache1_mode) |
+ S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache0_addr) |
+ S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache1_addr) |
S_SQ_CF_ALU_WORD1_BARRIER(1) |
S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == 0 ? cf->r6xx_uses_waterfall : 0) |
S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
unsigned pop_count;
unsigned cf_addr; /* control flow addr */
unsigned kcache0_mode;
+ unsigned kcache1_mode;
+ unsigned kcache0_addr;
+ unsigned kcache1_addr;
+ unsigned kcache0_bank;
+ unsigned kcache1_bank;
unsigned r6xx_uses_waterfall;
struct list_head alu;
struct list_head tex;