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diff --git a/openpower/ISA_WG/Board_letter_26mar2021.mdwn b/openpower/ISA_WG/Board_letter_26mar2021.mdwn
index df5e44c63dd8c692e8058da9e14162f98075668f..e03c93c32fc6b9270674ed7c7aa64284b00e63a9 100644 (file)
--- a/openpower/ISA_WG/Board_letter_26mar2021.mdwn
+++ b/openpower/ISA_WG/Board_letter_26mar2021.mdwn
@@ -25,7 +25,9 @@ to be sent to:
 
 Dear OPF Board,
 
-As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs over the next few decades in a clean and elegant fashion.  RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA. It goes without saying that over the past few decades, SIMD has been demonstrated to be harmful.
+As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs over the next few decades in a clean and elegant fashion.
+
+RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA which is already so large that efforts to update it would so far more harm than good.  It goes without saying that over the past few decades, SIMD has been demonstrated to be harmful.
 
 https://www.sigarch.org/simd-instructions-considered-harmful/