projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
1940bf6
)
Update manual
author
Miodrag Milanovic
<mmicko@gmail.com>
Fri, 10 Jun 2022 13:00:07 +0000
(15:00 +0200)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Fri, 10 Jun 2022 13:00:07 +0000
(15:00 +0200)
manual/command-reference-manual.tex
patch
|
blob
|
history
diff --git
a/manual/command-reference-manual.tex
b/manual/command-reference-manual.tex
index 4108527d8d8452f03c2ad8e21dd2770e1fae1ef7..edc8af6e69a3eab4b86962dc2355c888f566aef5 100644
(file)
--- a/
manual/command-reference-manual.tex
+++ b/
manual/command-reference-manual.tex
@@
-7838,6
+7838,11
@@
Add Verilog library directories. Verific will search in this directories to
find undefined modules.
+ verific -vlog-libext <extension>..
+
+Add Verilog library extensions, used when searching in library directories.
+
+
verific -vlog-define <macro>[=<value>]..
Add Verilog defines.
@@
-8057,6
+8062,9
@@
Options:
Do not change the width of memory address ports. Use this options in
flows that use the 'memory_memx' pass.
+ -mux_undef
+ remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
+
-keepdc
Do not optimize explicit don't-care values.
\end{lstlisting}