-# Load Byte and Zero with Post-Update
-
-D-Form
-
-* lbzup RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA)
- RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
- RA <- (RA) + EXTS(D)
-
-Description:
-
- Let the effective address (EA) be register RA.
- The byte in storage addressed by EA is loaded into RT[56:63].
- RT[0:55] are set to 0.
-
- The sum (RA) + D is placed into register RA.
-
- If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Load Byte and Zero with Post-Update Indexed
X-Form
None
-# Load Halfword and Zero with Post-Update
-
-D-Form
-
-* lhzup RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA)
- RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
- RA <- (RA) + EXTS(D)
-
-Description:
-
- Let the effective address (EA) be register RA.
- The halfword in storage addressed by EA is loaded into RT[48:63].
- RT[0:47] are set to 0.
-
- The sum (RA) + D is placed into register RA.
-
- If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Load Halfword and Zero with Post-Update Indexed
X-Form
None
-# Load Word and Zero with Post-Update
-
-D-Form
-
-* lwzup RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA)
- RT <- [0]*32 || MEM(EA, 4)
- RA <- (RA) + EXTS(D)
-
-Description:
-
- Let the effective address (EA) be the register RA.
- The halfword in storage addressed by EA is loaded into RT[48:63].
- RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
-
- The sum (RA) + D is placed into register RA.
-
- If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Load Word and Zero with Post-Update Indexed
X-Form
# Load Doubleword with Post-Update Indexed
-DS-Form
-
-* ldup RT,DS(RA)
-
-Pseudo-code:
-
- EA <- (RA)
- RT <- MEM(EA, 8)
- RA <- (RA) + EXTS(DS || 0b00)
-
-Description:
-
- Let the effective address (EA) be the register RA.
- The doubleword in storage addressed by EA is loaded into RT.
-
- The sum (RA)+ (DS||0b00) is placed into register RA.
-
- If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-# Load Doubleword with Post-Update Indexed
-
X-Form
* ldupx RT,RA,RB
<!-- This defines instructions that store from a register to RAM -->
<!-- Effective Address is always RA, and the usual EA is stored late in RA -->
-# Store Byte with Post-Update
-
-D-Form
-
-* stbup RS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- ea <- (RA)
- MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA)+ D.
-
- (RS)[56:63] are stored into the byte in storage addressed
- by RA.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Store Byte with Post-Update Indexed
X-Form
None
-# Store Halfword with Post-Update
-
-D-Form
-
-* sthup RS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- ea <- (RA)
- MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA|0)+ D.
-
- (RS)[48:63] are stored into the halfword in storage
- addressed by EA.
-
-Special Registers Altered:
-
- None
-
# Store Halfword with Post-Update Indexed
X-Form
None
-# Store Word with Post-Update
-
-D-Form
-
-* stwup RS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- ea <- (RA)
- MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA)+ D.
-
- (RS)[32:63] are stored into the word in storage addressed
- by EA.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Store Word with Post-Update Indexed
X-Form
None
-# Store Doubleword with Post-Update
-
-DS-Form
-
-* stdup RS,DS(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(DS || 0b00)
- ea <- (RA)
- MEM(ea, 8) <- (RS)
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum.
-
- (RA)+ (DS||0b00). (RS) is stored into the doubleword in
- storage addressed by RA.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Store Doubleword with Post-Update Indexed
X-Form
<!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
-# Load Floating-Point Single with Post-Update
-
-D-Form
-
-* lfsup FRT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- FRT <- DOUBLE(MEM(RA, 4))
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA)+D.
-
- The word in storage addressed by EA is interpreted as
- a floating-point single-precision operand. This word is
- converted to floating-point double format (see
- page 138) and placed into register FRT.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Load Floating-Point Single with Post-Update Indexed
X-Form
None
-# Load Floating-Point Double with Post-Update
-
-D-Form
-
-* lfdup FRT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- FRT <- MEM(RA, 8)
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA)+D.
-
- The doubleword in storage addressed by EA is loaded
- into register FRT.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Load Floating-Point Double with Post-Update Indexed
X-Form
<!-- Section 4.6.3 Floating-point store instructions. P 144 - 147 -->
-# Store Floating-Point Single with Update
-
-D-Form
-
-* stfsu FRS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- MEM(RA, 4)<- SINGLE( (FRS) )
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA) +D.
-
- The contents of register FRS are converted to single
- format (see page 142) and stored into the word in stor-
- age addressed by RA.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Store Floating-Point Single with Update Indexed
X-Form
None
-# Store Floating-Point Double with Update
-
-D-Form
-
-* stfdu FRS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- MEM(RA, 8)<- (FRS)
- RA <- EA
-
-Description:
-
- Let the effective address (EA) be the sum (RA)+D.
-
- The contents of register FRS are stored into the dou-
- bleword in storage addressed by RA.
-
- EA is placed into register RA.
-
- If RA=0, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
# Store Floating-Point Double with Update Indexed
X-Form
projects / openpower-isa.git / commitdiff