Remove option for "short" 16x16 bit multiplier

Now that we have a 33 bit x 33 bit signed multiplier in execute1,
there is really no need for the 16 bit multiplier.  The coremark
results are just as good without it as with it.  This removes the
option for the sake of simplicity.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

diff --git a/core.vhdl b/core.vhdl
index d7036f1035b04228829ff698d713907920d9bce0..aef2d7f2177c2fb07ed29986df48fac46fab4afa 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -13,7 +13,6 @@ entity core is
         EX1_BYPASS : boolean := true;
         HAS_FPU : boolean := true;
         HAS_BTC : boolean := true;
-        HAS_SHORT_MULT : boolean := false;
        ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
         LOG_LENGTH : natural := 512;
         ICACHE_NUM_LINES : natural := 64;
@@ -366,7 +365,6 @@ begin
             SIM => SIM,
             EX1_BYPASS => EX1_BYPASS,
             HAS_FPU => HAS_FPU,
-            HAS_SHORT_MULT => HAS_SHORT_MULT,
             LOG_LENGTH => LOG_LENGTH
             )
         port map (

diff --git a/execute1.vhdl b/execute1.vhdl
index 721d4936445549fc993183080329cf101bee99cd..a8fd052f03c52563f7b586042ff96cee913e3dd1 100644 (file)
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -15,7 +15,6 @@ entity execute1 is
         SIM : boolean := false;
         EX1_BYPASS : boolean := true;
         HAS_FPU : boolean := true;
-        HAS_SHORT_MULT : boolean := false;
         -- Non-zero to enable log data collection
         LOG_LENGTH : natural := 0
         );
@@ -448,17 +447,6 @@ begin
             p_out => pmu_to_x
             );
 
-    short_mult_0: if HAS_SHORT_MULT generate
-    begin
-        short_mult: entity work.short_multiply
-        port map (
-            clk => clk,
-            a_in => a_in(15 downto 0),
-            b_in => b_in(15 downto 0),
-            m_out => mshort_p
-            );
-    end generate;
-
     dbg_ctrl_out <= ctrl;
     log_rd_addr <= ex2.log_addr_spr;
 
@@ -1288,13 +1276,6 @@ begin
                     v.se.mult_32s := '1';
                     v.res2_sel := "00";
                     slow_op := '1';
-                elsif HAS_SHORT_MULT and e_in.reg_valid3 = '0' and
-                    fits_in_n_bits(a_in, 16) and fits_in_n_bits(b_in, 16) then
-                    -- Operands fit into 16 bits, so use short multiplier
-                    if e_in.oe = '1' then
-                        -- Note 16x16 multiply can't overflow, even for mullwo
-                        set_ov(v.e, '0', '0');
-                    end if;
                 else
                     -- Use standard multiplier
                     v.start_mul := '1';

diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index 0c5822fc3ba29c2de08acf18f0795f968a652340..ecdd5d42281dfd401ec94b87f8ddc6ded6ca90cf 100644 (file)
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -16,7 +16,6 @@ entity toplevel is
         CLK_FREQUENCY      : positive := 100000000;
         HAS_FPU            : boolean  := true;
         HAS_BTC            : boolean  := true;
-        HAS_SHORT_MULT     : boolean  := false;
         USE_LITEDRAM       : boolean  := false;
         NO_BRAM            : boolean  := false;
         DISABLE_FLATTEN_CORE : boolean := false;
@@ -199,7 +198,6 @@ begin
             CLK_FREQ           => CLK_FREQUENCY,
             HAS_FPU            => HAS_FPU,
             HAS_BTC            => HAS_BTC,
-            HAS_SHORT_MULT     => HAS_SHORT_MULT,
             HAS_DRAM           => USE_LITEDRAM,
             DRAM_SIZE          => 256 * 1024 * 1024,
             DRAM_INIT_SIZE     => PAYLOAD_SIZE,

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index da42bb57d7b56cda35cfb0c216e7965280e337ea..c75e4657ef8aba47b4553e1c61b80ffdaf1eea4d 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -13,7 +13,6 @@ entity toplevel is
        CLK_FREQUENCY : positive := 100000000;
         HAS_FPU       : boolean  := true;
         HAS_BTC       : boolean  := false;
-        HAS_SHORT_MULT: boolean  := false;
         ICACHE_NUM_LINES : natural := 64;
         LOG_LENGTH    : natural := 512;
        DISABLE_FLATTEN_CORE : boolean := false;
@@ -75,7 +74,6 @@ begin
            CLK_FREQ      => CLK_FREQUENCY,
             HAS_FPU       => HAS_FPU,
             HAS_BTC       => HAS_BTC,
-            HAS_SHORT_MULT => HAS_SHORT_MULT,
            ICACHE_NUM_LINES => ICACHE_NUM_LINES,
             LOG_LENGTH    => LOG_LENGTH,
            DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,

diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index 3dd99987106c6256469a563163a22f9181d7ac48..beb4045f7fe5712a155b6456e911e9f636106911 100644 (file)
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -16,7 +16,6 @@ entity toplevel is
        CLK_FREQUENCY : positive := 100000000;
         HAS_FPU       : boolean  := true;
         HAS_BTC       : boolean  := true;
-        HAS_SHORT_MULT: boolean  := false;
        USE_LITEDRAM  : boolean  := false;
        NO_BRAM       : boolean  := false;
        DISABLE_FLATTEN_CORE : boolean := false;
@@ -175,7 +174,6 @@ begin
            CLK_FREQ      => CLK_FREQUENCY,
             HAS_FPU       => HAS_FPU,
             HAS_BTC       => HAS_BTC,
-            HAS_SHORT_MULT=> HAS_SHORT_MULT,
            HAS_DRAM      => USE_LITEDRAM,
            DRAM_SIZE     => 512 * 1024 * 1024,
             DRAM_INIT_SIZE => PAYLOAD_SIZE,

diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl
index e3e9c80a5b512473b5f3036d94b5ca20d08f0a6c..ada940cce3452d1bea37c28c51f796478e330b6a 100644 (file)
--- a/fpga/top-orangecrab0.2.vhdl
+++ b/fpga/top-orangecrab0.2.vhdl
@@ -188,7 +188,6 @@ begin
             HAS_UART1          => HAS_UART1,
             HAS_SD_CARD        => USE_LITESDCARD,
             ICACHE_NUM_LINES   => ICACHE_NUM_LINES,
-            HAS_SHORT_MULT     => true,
             NGPIO              => NGPIO
             )
         port map (

diff --git a/fpga/top-wukong-v2.vhdl b/fpga/top-wukong-v2.vhdl
index d2a23ab5b5da9065539516510ef1cd2b0d83632a..d3f7bd886fda415f8a53f46016aa15d0ab98c6eb 100644 (file)
--- a/fpga/top-wukong-v2.vhdl
+++ b/fpga/top-wukong-v2.vhdl
@@ -16,7 +16,6 @@ entity toplevel is
         CLK_FREQUENCY      : positive := 100000000;
         HAS_FPU            : boolean  := true;
         HAS_BTC            : boolean  := true;
-        HAS_SHORT_MULT     : boolean  := false;
         USE_LITEDRAM       : boolean  := false;
         NO_BRAM            : boolean  := false;
         DISABLE_FLATTEN_CORE : boolean := false;
@@ -175,7 +174,6 @@ begin
             CLK_FREQ           => CLK_FREQUENCY,
             HAS_FPU            => HAS_FPU,
             HAS_BTC            => HAS_BTC,
-            HAS_SHORT_MULT     => HAS_SHORT_MULT,
             HAS_DRAM           => USE_LITEDRAM,
             DRAM_SIZE          => 256 * 1024 * 1024,
             DRAM_INIT_SIZE     => PAYLOAD_SIZE,

diff --git a/microwatt.core b/microwatt.core
index b817901f68fea24205267ed6a8e8e974dfcc0f9f..07085b1a7a2c7398a068c6defb349d966c1e1380 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -146,7 +146,6 @@ targets:
       - uart_is_16550
       - has_fpu
       - has_btc
-      - has_short_mult
     tools:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : toplevel
@@ -252,7 +251,6 @@ targets:
       - uart_is_16550
       - has_fpu
       - has_btc
-      - has_short_mult
     generate: [litedram_nexys_video, liteeth_nexys_video, litesdcard_nexys_video]
     tools:
       vivado: {part : xc7a200tsbg484-1}
@@ -273,7 +271,6 @@ targets:
       - has_uart1
       - has_fpu=false
       - has_btc=false
-      - has_short_mult
       - use_litesdcard
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -296,7 +293,6 @@ targets:
       - has_uart1
       - has_fpu=false
       - has_btc=false
-      - has_short_mult
     generate: [litedram_arty, liteeth_arty, litesdcard_arty]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -317,7 +313,6 @@ targets:
       - has_uart1
       - has_fpu
       - has_btc
-      - has_short_mult
       - use_litesdcard
     tools:
       vivado: {part : xc7a100ticsg324-1L}
@@ -340,7 +335,6 @@ targets:
       - has_uart1
       - has_fpu
       - has_btc
-      - has_short_mult
     generate: [litedram_arty, liteeth_arty, litesdcard_arty]
     tools:
       vivado: {part : xc7a100ticsg324-1L}
@@ -362,7 +356,6 @@ targets:
       - uart_is_16550
       - has_fpu
       - has_btc
-      - has_short_mult
     generate: [litesdcard_wukong-v2]
     tools:
       vivado: {part : xc7a100tfgg676-1}
@@ -384,7 +377,6 @@ targets:
       - uart_is_16550
       - has_fpu
       - has_btc
-      - has_short_mult
     generate: [litedram_wukong-v2, liteeth_wukong-v2, litesdcard_wukong-v2]
     tools:
       vivado: {part : xc7a100tfgg676-1}
@@ -500,12 +492,6 @@ parameters:
     paramtype   : generic
     default     : true
 
-  has_short_mult:
-    datatype    : bool
-    description : Include a 16 bit x 16 bit single-cycle multiplier in the core
-    paramtype   : generic
-    default     : false
-
   disable_flatten_core:
     datatype    : bool
     description : Prevent Vivado from flattening the main core components

diff --git a/soc.vhdl b/soc.vhdl
index 6842473a90e290ec450953b741c1006b1ea4a696..7daca5fa52f82c775721cfad1ac3fe71e8d01683 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -59,7 +59,6 @@ entity soc is
        SIM                : boolean;
         HAS_FPU            : boolean := true;
         HAS_BTC            : boolean := true;
-        HAS_SHORT_MULT     : boolean := false;
        DISABLE_FLATTEN_CORE : boolean := false;
         ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
        HAS_DRAM           : boolean  := false;
@@ -335,7 +334,6 @@ begin
            SIM => SIM,
             HAS_FPU => HAS_FPU,
             HAS_BTC => HAS_BTC,
-            HAS_SHORT_MULT => HAS_SHORT_MULT,
            DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
            ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
             LOG_LENGTH => LOG_LENGTH,