Update configs to set the CPU clock properly.

--HG--
extra : convert_revision : 62fec666f987e9a9a441e319458908483cd2c5ff

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 331e2c569dc34b88c679b8fde20450682e82a81c..1e414294c885589fbd307a41911d36c94f5a25c2 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -73,6 +73,7 @@ for cpu in cpus:
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 5600d9f22526fa6ee105b5f8fb4317a70a896976..d20a7e0c861e63b11b26c9e8e6a62d4a71953e4f 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -40,6 +40,7 @@ class MyCache(BaseCache):
 cpu = DerivO3CPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
+cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index f9e4e27679bc168a59f2fc97a2bcdc561c63f626..e8000cd0a9b0bba46581a086d95a2cfeb7878ccc 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port

diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index a8a87699482820933c358fdab7283fadc146a497..cc303886b9ef8a9c322d4b1796bdd88361b5971c 100644 (file)
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
+system.cpu.clock = '2GHz'
 
 root = Root(system = system)

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 0d99d8714d9b4a9c05688329080558d15855af98..a263bcf572b0e1283f4226f65aa3a1070eed4523 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index d7d505a5ac2029ea19aab670c52d4b5966df1b71..6c4b8232f2db49fa966c32787a4a594ae199fa39 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -44,5 +44,6 @@ system = System(cpu = cpu,
                 membus = Bus())
 system.physmem.port = system.membus.port
 cpu.connectMemPorts(system.membus)
+cpu.clock = '2GHz'
 
 root = Root(system = system)