cpu: Remove alpha specialized code.

Change-Id: I770132af2f11ed232a100ab8bef942f17789ef36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24648
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 09a8b331f10da62d0ace7f6c8167794a9564cc3f..527d5db4a7d75ce976b62fe0dea35bf78e375558 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -62,11 +62,7 @@ from m5.objects.Platform import Platform
 
 default_tracer = ExeTracer()
 
-if buildEnv['TARGET_ISA'] == 'alpha':
-    from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
-    from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
-    from m5.objects.AlphaISA import AlphaISA as ArchISA
-elif buildEnv['TARGET_ISA'] == 'sparc':
+if buildEnv['TARGET_ISA'] == 'sparc':
     from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
     from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
     from m5.objects.SparcISA import SparcISA as ArchISA

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index fce4a9fc36bd7d6459aa5465dff0cfb3d0183ca4..f4b43b2986ce3442bbe80a6fdfd969f1187ba684 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -207,9 +207,6 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst)
 
         // maintain $r0 semantics
         thread->setIntReg(ZeroReg, 0);
-#if THE_ISA == ALPHA_ISA
-        thread->setFloatReg(ZeroReg, 0);
-#endif
 
         // Check if any recent PC changes match up with anything we
         // expect to happen.  This is mostly to check if traps or

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 4cc41c6c89e2490eda965012ee37157e800f8c7d..2b1b53054293370418e81762aefe4acc1629d699 100644 (file)
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -99,9 +99,6 @@ class ExecContext : public ::ExecContext
         setPredicate(inst->readPredicate());
         setMemAccPredicate(inst->readMemAccPredicate());
         thread.setIntReg(TheISA::ZeroReg, 0);
-#if THE_ISA == ALPHA_ISA
-        thread.setFloatReg(TheISA::ZeroReg, 0);
-#endif
     }
 
     ~ExecContext()

diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 465372a08b8bc69a65afe4294ecb87aa47d90dae..d302f0f1c5d8721511795e5c4f6248e5ee2aa7ab 100644 (file)
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -196,15 +196,7 @@ Fetch1::fetchLine(ThreadID tid)
     /* Step the PC for the next line onto the line aligned next address.
      * Note that as instructions can span lines, this PC is only a
      * reliable 'new' PC if the next line has a new stream sequence number. */
-#if THE_ISA == ALPHA_ISA
-    /* Restore the low bits of the PC used as address space flags */
-    Addr pc_low_bits = thread.pc.instAddr() &
-        ((Addr) (1 << sizeof(TheISA::MachInst)) - 1);
-
-    thread.pc.set(aligned_pc + request_size + pc_low_bits);
-#else
     thread.pc.set(aligned_pc + request_size);
-#endif
 }
 
 std::ostream &

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index fa2d72494c910cb4a32e49c026e4761020a05b96..fc927077ff0c1d8704eab41f8c0482e29fea9b74 100644 (file)
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1053,11 +1053,8 @@ DefaultCommit<Impl>::commitInsts()
                 // Set the doneSeqNum to the youngest committed instruction.
                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 
-                if (tid == 0) {
-                    canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
-                                           ((THE_ISA != ALPHA_ISA) ||
-                                             (!(pc[0].instAddr() & 0x3)));
-                }
+                if (tid == 0)
+                    canHandleInterrupts = !head_inst->isDelayedCommit();
 
                 // at this point store conditionals should either have
                 // been completed or predicated false

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 27800dea5fbd1c132f97f52b5578f3ccf4547473..31334a313eb76f8d8d5e8d47972290babd5da9f3 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -68,12 +68,6 @@
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
 
-#if THE_ISA == ALPHA_ISA
-#include "arch/alpha/osfpal.hh"
-#include "debug/Activity.hh"
-
-#endif
-
 struct BaseCPUParams;
 
 using namespace TheISA;
@@ -231,14 +225,11 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
         // use an invalid FP register index to avoid special treatment
         // of any valid FP reg.
         RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
-        RegIndex fpZeroReg =
-            (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
 
-        commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
-                                  &freeList,
-                                  vecMode);
+        commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, invalidFPReg,
+                                  &freeList, vecMode);
 
-        renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
+        renameMap[tid].init(&regFile, TheISA::ZeroReg, invalidFPReg,
                             &freeList, vecMode);
     }
 

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index b8766ad775b70077dcbc4c895a2da64ab82d65b1..890e8f362e92d158a701b49fe67ca2c583a9f3b3 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -325,7 +325,7 @@ class DefaultFetch
     bool
     checkInterrupt(Addr pc)
     {
-        return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
+        return interruptPending;
     }
 
     /** Squashes a specific thread and resets the PC. */

diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index e71e938bf1e5d0d4abbab52b9161ce883949fd9c..5158137abd7859e35c26bed42bc677918eb33c73 100644 (file)
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -140,9 +140,7 @@ class RegId {
 
     inline bool isZeroReg() const
     {
-        return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
-               (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
-                regIdx == TheISA::ZeroReg));
+        return regClass == IntRegClass && regIdx == TheISA::ZeroReg;
     }
 
     /** @return true if it is an integer physical register. */

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 06dd7739057aa570ad7cee86c32737ac46d9294c..2a7c987306cf18981c1f7c1633601e35f955a5ed 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -486,9 +486,6 @@ BaseSimpleCPU::preExecute()
 
     // maintain $r0 semantics
     thread->setIntReg(ZeroReg, 0);
-#if THE_ISA == ALPHA_ISA
-    thread->setFloatReg(ZeroReg, 0);
-#endif // ALPHA_ISA
 
     // resets predicates
     t_info.setPredicate(true);