m68k.h (EXTRA_CONSTRAINT): add 'U' for register offset addressing.

	* config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for register offset
	addressing.
	* config/m68k/m68k.md: Add 'U,U' alternative to ColdFire variants of
	movsi,movhi,movqi insn patterns.

From-SVN: r82420

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 055155ce78bae4136f49a42947d4ee37646a30b3..ca2b422b8febc858def7aac507611af77240bba3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2004-05-29  Peter Barada  <peter@the-baradas.com>
+
+       * config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for register offset
+       addressing.
+       * config/m68k/m68k.md: Add 'U,U' alternative to ColdFire variants of
+       movsi,movhi,movqi insn patterns.
+
 2005-05-28  Andrew Pinski  <pinskia@physics.uc.edu>
 
        * c-semantics.c (emit_local_var): Remove code for DECL_INITIAL.

diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index 522f0dc5e4fd08cf0c3170c85c9e4410c430ea86..c7cc76b7d458502fd201a04c30e7f87fe61a4998 100644 (file)
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -735,7 +735,8 @@ extern enum reg_class regno_reg_class[];
 
    `Q' means address register indirect addressing mode.
    `S' is for operands that satisfy 'm' when -mpcrel is in effect.
-   `T' is for operands that satisfy 's' when -mpcrel is not in effect.  */
+   `T' is for operands that satisfy 's' when -mpcrel is not in effect.
+   `U' is for register offset addressing.  */
 
 #define EXTRA_CONSTRAINT(OP,CODE)                      \
   (((CODE) == 'S')                                     \
@@ -755,7 +756,13 @@ extern enum reg_class regno_reg_class[];
    ? (GET_CODE (OP) == MEM                             \
       && GET_CODE (XEXP (OP, 0)) == REG)               \
    :                                                   \
-   0)))
+  (((CODE) == 'U')                                     \
+   ? (GET_CODE (OP) == MEM                             \
+      && GET_CODE (XEXP (OP, 0)) == PLUS               \
+      && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG      \
+      && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
+   :                                                   \
+   0))))
 
 /* Given an rtx X being reloaded into a reg required to be
    in class CLASS, return the class of reg to actually use.

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index e674ca2a7d73597be60ea50c152527307970a5d2..2603195224dc97f199a62f838ec0641e13336025 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -676,8 +676,8 @@
 })
 
 (define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
-       (match_operand:SI 1 "general_operand" "g,r<Q>"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
+       (match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
   "TARGET_COLDFIRE"
   "* return output_move_simode (operands);")
 
@@ -706,8 +706,8 @@
   "* return output_move_himode (operands);")
 
  (define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
-       (match_operand:HI 1 "general_operand" "g,r<Q>"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
+       (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
   "TARGET_COLDFIRE"
   "* return output_move_himode (operands);")
 
@@ -742,8 +742,8 @@
   "* return output_move_qimode (operands);")
 
 (define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
-       (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
+       (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
   "TARGET_COLDFIRE"
   "* return output_move_qimode (operands);")