CGEN is cool, but the BPF architecture is simply too bizarre for it.
The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port. The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update. Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.
This is getting un-maintenable.
So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN. Overall, this involved:
* To remove the cpu/bpf.{cpu,opc} descriptions.
* To remove the CGEN generated files.
* To replace the CGEN generated opcodes table with a new hand-written
opcodes table for BPF.
* To replace the CGEN generated disassembler wih a new disassembler
that uses the new opcodes.
* To replace the CGEN generated assembler with a new assembler that uses the
new opcodes.
* To replace the CGEN generated simulator with a new simulator that uses the
new opcodes. [This is pushed in GDB in another patch.]
* To adapt the build systems to the new situation.
Additionally, this patch introduces some extensions and improvements:
* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These
relocations are used for section-relative 16-bit offsets used in
load/store instructions.
* The disassembler now has support for the "pseudo-c" assembly syntax of
BPF. What dialect to use when disassembling is controlled by a command
line option.
* The disassembler now has support for dumping instruction immediates in
either octal, hexadecimal or decimal. The used output base is controlled
by a new command-line option.
* The GAS BPF test suite has been re-structured and expanded in order to
test the disassembler pseudoc syntax support. Minor bugs have been also
fixed there. The assembler generic tests that were disabled for bpf-*-*
targets due to the previous implementation of pseudoc syntax are now
re-enabled. Additional tests have been added to test the new features of
the assembler. .dump files are no longer used.
* The linker BPF test suite has been adapted to the command line options
used by the new disassembler.
The result is very satisfactory. This patchs adds 3448 lines of code
and removes 10542 lines of code.
Tested in:
* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
little-endian host.
* Target x86-64-linux-gnu with --enable-targets=all
Note that I have not tested in a big-endian host yet. I will do so
once this lands upstream so I can use the GCC compiler farm.
I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port. I beg the indulgence of the global maintainers.
/* Linux eBPF relocations. */
BFD_RELOC_BPF_64,
BFD_RELOC_BPF_DISP32,
+ BFD_RELOC_BPF_DISP16,
/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
BFD_RELOC_EPIPHANY_SIMM8,
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
true) /* pcrel_offset */
+
+ /* 16-bit PC-relative address in load instructions. */
+ BPF_HOWTO (R_BPF_GNU_64_16, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 16, /* bitsize */
+ true, /* pc_relative */
+ 16, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bpf_elf_generic_reloc, /* special_function */
+ "R_BPF_GNU_64_16", /* name */
+ true, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ true) /* pcrel_offset */
return &bpf_elf_howto_table[ (int) R_BPF_64_64_IDX];
case BFD_RELOC_BPF_DISP32:
return &bpf_elf_howto_table[ (int) R_BPF_64_32_IDX];
+ case BFD_RELOC_BPF_DISP16:
+ return &bpf_elf_howto_table[ (int) R_BPF_GNU_64_16_IDX];
default:
/* Pacify gcc -Wall. */
"BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD",
"BFD_RELOC_BPF_64",
"BFD_RELOC_BPF_DISP32",
+ "BFD_RELOC_BPF_DISP16",
"BFD_RELOC_EPIPHANY_SIMM8",
"BFD_RELOC_EPIPHANY_SIMM24",
"BFD_RELOC_EPIPHANY_HIGH",
BFD_RELOC_BPF_64
ENUMX
BFD_RELOC_BPF_DISP32
+ENUMX
+ BFD_RELOC_BPF_DISP16
ENUMDOC
Linux eBPF relocations.
+++ /dev/null
-;; Linux BPF CPU description -*- Scheme -*-
-;; Copyright (C) 2019 Free Software Foundation, Inc.
-;;
-;; Contributed by Oracle Inc.
-;;
-;; This file is part of the GNU Binutils and of GDB.
-;;
-;; This program is free software; you can redistribute it and/or
-;; modify it under the terms of the GNU General Public License as
-;; published by the Free Software Foundation; either version 3 of the
-;; License, or (at your option) any later version.
-;;
-;; This program is distributed in the hope that it will be useful, but
-;; WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-;; General Public License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with this program; if not, write to the Free Software
-;; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
-;; 02110-1301, USA.
-
-;; This file contains a CGEN CPU description for the Linux kernel eBPF
-;; instruction set. eBPF is documented in the linux kernel source
-;; tree. See linux/Documentation/networking/filter.txt, and also the
-;; sources in the networking subsystem, notably
-;; linux/net/core/filter.c.
-
-(include "simplify.inc")
-
-(define-arch
- (name bpf)
- (comment "Linux kernel BPF")
- (insn-lsb0? #t)
- ;; XXX explain the default-alignment setting is for the simulator.
- ;; It is confusing that the simulator follows the emulated memory
- ;; access conventions for fetching instructions by pieces...
- (default-alignment unaligned)
- (machs bpf xbpf)
- (isas ebpfle ebpfbe xbpfle xbpfbe))
-
-;;;; The ISAs
-
-;; Logically, eBPF comforms a single instruction set featuring two
-;; kind of instructions: 64-bit instructions and 128-bit instructions.
-;;
-;; The 64-bit instructions have the form:
-;;
-;; code:8 regs:8 offset:16 imm:32
-;;
-;; Whereas the 128-bit instructions (at the moment there is only one
-;; of such instructions, lddw) have the form:
-;;
-;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32
-;;
-;; In both formats `regs' is itself composed by two fields:
-;;
-;; dst:4 src:4
-;;
-;; The ISA is supposed to be orthogonal to endianness: the endianness
-;; of the instruction fields follow the endianness of the host running
-;; the eBPF program, and that's all. However, this is not entirely
-;; true. The definition of an eBPF code in the Linux kernel is:
-;;
-;; struct bpf_insn {
-;; __u8 code; /* opcode */
-;; __u8 dst_reg:4; /* dest register */
-;; __u8 src_reg:4; /* source register */
-;; __s16 off; /* signed offset */
-;; __s32 imm; /* signed immediate constant */
-;; };
-;;
-;; Since the ordering of fields in C bitmaps is defined by the
-;; implementation, the impact of endianness in the encoding of eBPF
-;; instructions is effectively defined by GCC. In particular, GCC
-;; places dst_reg before src_reg in little-endian code, and the other
-;; way around in big-endian code.
-;;
-;; So, in reality, eBPF comprises two instruction sets: one for
-;; little-endian with instructions like:
-;;
-;; code:8 src:4 dst:4 offset:16 imm:32 [unused:32 imm:32]
-;;
-;; and another for big-endian with instructions like:
-;;
-;; code:8 dst:4 src:4 offset:16 imm:32 [unused:32 imm:32]
-;;
-;; where `offset' and the immediate fields are encoded in
-;; little-endian and big-endian byte-order, respectively.
-
-(define-pmacro (define-bpf-isa x-endian)
- (define-isa
- (name (.sym ebpf x-endian))
- (comment "The eBPF instruction set")
- ;; Default length to record in ifields. This is used in
- ;; calculations involving bit numbers.
- (default-insn-word-bitsize 64)
- ;; Length of an unknown instruction. Used by disassembly and by the
- ;; simulator's invalid insn handler.
- (default-insn-bitsize 64)
- ;; Number of bits of insn that can be initially fetched. This is
- ;; the size of the smallest insn.
- (base-insn-bitsize 64)))
-
-(define-bpf-isa le)
-(define-bpf-isa be)
-
-(define-pmacro (define-xbpf-isa x-endian)
- (define-isa
- (name (.sym xbpf x-endian))
- (comment "The xBPF instruction set")
- (default-insn-word-bitsize 64)
- (default-insn-bitsize 64)
- (base-insn-bitsize 64)))
-
-(define-xbpf-isa le)
-(define-xbpf-isa be)
-
-(define-pmacro all-isas () (ISA ebpfle,ebpfbe,xbpfle,xbpfbe))
-(define-pmacro xbpf-isas () (ISA xbpfle,xbpfbe))
-
-(define-pmacro (endian-isas x-endian)
- ((ISA (.sym ebpf x-endian) (.sym xbpf x-endian))))
-
-;;;; Hardware Hierarchy
-
-;;
-;; bpf architecture
-;; |
-;; bpfbf cpu-family
-;; / \
-;; bpf xbpf machine
-;; | |
-;; bpf-def xbpf-def model
-
-(define-cpu
- (name bpfbf)
- (comment "Linux kernel eBPF virtual CPU")
- (insn-endian big)
- (word-bitsize 64))
-
-(define-mach
- (name bpf)
- (comment "Linux eBPF")
- (cpu bpfbf)
- (isas ebpfle ebpfbe))
-
-(define-model
- (name bpf-def)
- (comment "Linux eBPF default model")
- (mach bpf)
- (unit u-exec "execution unit" ()
- 1 ; issue
- 1 ; done
- () ; state
- () ; inputs
- () ; outputs
- () ; profile action (default)
- ))
-
-(define-mach
- (name xbpf)
- (comment "Experimental BPF")
- (cpu bpfbf)
- (isas ebpfle ebpfbe xbpfle xbpfbe))
-
-(define-model
- (name xbpf-def)
- (comment "xBPF default model")
- (mach xbpf)
- (unit u-exec "execution unit" ()
- 1 ; issue
- 1 ; done
- () ; state
- () ; inputs
- () ; outputs
- () ; profile action (default)
- ))
-
-;;;; Hardware Elements
-
-;; eBPF programs can access 10 general-purpose registers which are
-;; 64-bit.
-
-(define-hardware
- (name h-gpr)
- (comment "General Purpose Registers")
- (attrs all-isas (MACH bpf xbpf))
- (type register DI (16))
- (indices keyword "%"
- ;; XXX the frame pointer fp is read-only, so it should
- ;; go in a different hardware.
- (;; ABI names. Take priority when disassembling.
- (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
- (r7 7) (r8 8) (r9 9) (fp 10)
- ;; Additional names recognized when assembling.
- (r0 0) (r6 6) (r10 10))))
-
-;; The program counter. CGEN requires it, even if it is not visible
-;; to eBPF programs.
-
-(define-hardware
- (name h-pc)
- (comment "program counter")
- (attrs PC PROFILE all-isas)
- (type pc UDI)
- (get () (raw-reg h-pc))
- (set (newval) (set (raw-reg h-pc) newval)))
-
-;; A 64-bit h-sint to be used by the imm64 operand below. XXX this
-;; shouldn't be needed, as h-sint is supposed to be able to hold
-;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits
-;; in 32-bit hosts. To be fixed in CGEN.
-
-(dnh h-sint64 "signed 64-bit integer" (all-isas) (immediate DI)
- () () ())
-
-;;;; The Instruction Sets
-
-;;; Fields and Opcodes
-
-;; Convenience macro to shorten the definition of the fields below.
-(define-pmacro (dwf x-name x-comment x-attrs
- x-word-offset x-word-length x-start x-length
- x-mode)
- "Define a field including its containing word."
- (define-ifield
- (name x-name)
- (comment x-comment)
- (.splice attrs (.unsplice x-attrs))
- (word-offset x-word-offset)
- (word-length x-word-length)
- (start x-start)
- (length x-length)
- (mode x-mode)))
-
-;; For arithmetic and jump instructions the 8-bit code field is
-;; subdivided in:
-;;
-;; op-code:4 op-src:1 op-class:3
-
-(dwf f-op-code "eBPF opcode code" (all-isas) 0 8 7 4 UINT)
-(dwf f-op-src "eBPF opcode source" (all-isas) 0 8 3 1 UINT)
-(dwf f-op-class "eBPF opcode instruction class" (all-isas) 0 8 2 3 UINT)
-
-(define-normal-insn-enum insn-op-code-alu "eBPF instruction codes"
- (all-isas) OP_CODE_ f-op-code
- (;; Codes for OP_CLASS_ALU and OP_CLASS_ALU64
- (ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5)
- (LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb)
- (ARSH #xc) (END #xd)
- ;; xBPF-only: signed div, signed mod
- (SDIV #xe) (SMOD #xf)
- ;; Codes for OP_CLASS_JMP
- (JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4)
- (JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9)
- (JLT #xa) (JLE #xb) (JSLT #xc) (JSLE #xd)))
-
-(define-normal-insn-enum insn-op-src "eBPF instruction source"
- (all-isas) OP_SRC_ f-op-src
- ;; X => use `src' as source operand.
- ;; K => use `imm32' as source operand.
- ((K #b0) (X #b1)))
-
-(define-normal-insn-enum insn-op-class "eBPF instruction class"
- (all-isas) OP_CLASS_ f-op-class
- ((LD #b000) (LDX #b001) (ST #b010) (STX #b011)
- (ALU #b100) (JMP #b101) (JMP32 #b110) (ALU64 #b111)))
-
-;; For load/store instructions, the 8-bit code field is subdivided in:
-;;
-;; op-mode:3 op-size:2 op-class:3
-
-(dwf f-op-mode "eBPF opcode mode" (all-isas) 0 8 7 3 UINT)
-(dwf f-op-size "eBPF opcode size" (all-isas) 0 8 4 2 UINT)
-
-(define-normal-insn-enum insn-op-mode "eBPF load/store instruction modes"
- (all-isas) OP_MODE_ f-op-mode
- ((IMM #b000) (ABS #b001) (IND #b010) (MEM #b011)
- ;; #b100 and #b101 are used in classic BPF only, reserved in eBPF.
- (XADD #b110)))
-
-(define-normal-insn-enum insn-op-size "eBPF load/store instruction sizes"
- (all-isas) OP_SIZE_ f-op-size
- ((W #b00) ;; Word: 4 byte
- (H #b01) ;; Half-word: 2 byte
- (B #b10) ;; Byte: 1 byte
- (DW #b11))) ;; Double-word: 8 byte
-
-;; The fields for the source and destination registers are a bit
-;; tricky. Due to the bizarre nibble swap between little-endian and
-;; big-endian ISAs we need to keep different variants of the fields.
-;;
-;; Note that f-regs is used in the format spec of instructions that do
-;; NOT use registers, where endianness is irrelevant i.e. f-regs is a
-;; constant 0 opcode.
-
-(dwf f-dstle "eBPF dst register field" ((ISA ebpfle xbpfle)) 8 8 3 4 UINT)
-(dwf f-srcle "eBPF source register field" ((ISA ebpfle xbpfle)) 8 8 7 4 UINT)
-
-(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe xbpfbe)) 8 8 7 4 UINT)
-(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe xbpfbe)) 8 8 3 4 UINT)
-
-(dwf f-regs "eBPF registers field" (all-isas) 8 8 7 8 UINT)
-
-;; Finally, the fields for the immediates.
-;;
-;; The 16-bit offsets and 32-bit immediates do not present any special
-;; difficulty: we put them in their own instruction word so the
-;; byte-endianness will be properly applied.
-
-(dwf f-offset16 "eBPF offset field" (all-isas) 16 16 15 16 HI)
-(dwf f-imm32 "eBPF 32-bit immediate field" (all-isas) 32 32 31 32 INT)
-
-;; For the disjoint 64-bit signed immediate, however, we need to use a
-;; multi-ifield.
-
-(dwf f-imm64-a "eBPF 64-bit immediate a" (all-isas) 32 32 31 32 UINT)
-(dwf f-imm64-b "eBPF 64-bit immediate b" (all-isas) 64 32 31 32 UINT)
-(dwf f-imm64-c "eBPF 64-bit immediate c" (all-isas) 96 32 31 32 UINT)
-
-(define-multi-ifield
- (name f-imm64)
- (comment "eBPF 64-bit immediate field")
- (attrs all-isas)
- (mode DI)
- (subfields f-imm64-a f-imm64-b f-imm64-c)
- (insert (sequence ()
- (set (ifield f-imm64-b) (const 0))
- (set (ifield f-imm64-c) (srl (ifield f-imm64) (const 32)))
- (set (ifield f-imm64-a) (and (ifield f-imm64) (const #xffffffff)))))
- (extract (sequence ()
- (set (ifield f-imm64)
- (or (sll UDI (zext UDI (ifield f-imm64-c)) (const 32))
- (zext UDI (ifield f-imm64-a)))))))
-
-;;; Operands
-
-;; A couple of source and destination register operands are defined
-;; for each ISA: ebpfle and ebpfbe.
-
-(dno dstle "destination register" ((ISA ebpfle xbpfle)) h-gpr f-dstle)
-(dno srcle "source register" ((ISA ebpfle xbpfle)) h-gpr f-srcle)
-
-(dno dstbe "destination register" ((ISA ebpfbe xbpfbe)) h-gpr f-dstbe)
-(dno srcbe "source register" ((ISA ebpfbe xbpfbe)) h-gpr f-srcbe)
-
-;; Jump instructions have a 16-bit PC-relative address.
-;; CALL instructions have a 32-bit PC-relative address.
-
-(dno disp16 "16-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
- f-offset16)
-(dno disp32 "32-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
- f-imm32)
-
-;; Immediate operands in eBPF are signed, and we want the disassembler
-;; to print negative values in a sane way. Therefore we use the macro
-;; below to register a printer, which is itself defined as a C
-;; function in bpf.opc.
-
-;; define-normal-signed-immediate-operand
-(define-pmacro (dnsio x-name x-comment x-attrs x-type x-index)
- (define-operand
- (name x-name)
- (comment x-comment)
- (.splice attrs (.unsplice x-attrs))
- (type x-type)
- (index x-index)
- (handlers (print "immediate"))))
-
-(dnsio imm32 "32-bit immediate" (all-isas) h-sint f-imm32)
-(dnsio offset16 "16-bit offset" (all-isas) h-sint f-offset16)
-
-;; The 64-bit immediate cannot use the default
-;; cgen_parse_signed_integer, because it assumes operands are at much
-;; 32-bit wide. Use our own.
-
-(define-operand
- (name imm64)
- (comment "64-bit immediate")
- (attrs all-isas)
- (type h-sint64)
- (index f-imm64)
- (handlers (parse "imm64") (print "immediate")))
-
-;; The endle/endbe instructions take an operand to specify the word
-;; width in endianness conversions. We use both a parser and printer,
-;; which are defined as C functions in bpf.opc.
-
-(define-operand
- (name endsize)
- (comment "endianness size immediate: 16, 32 or 64")
- (attrs all-isas)
- (type h-uint)
- (index f-imm32)
- (handlers (parse "endsize") (print "endsize")))
-
-;;; ALU instructions
-
-;; For each opcode in insn-op-code-alu representing and integer
-;; arithmetic instruction (ADD, SUB, etc) we define a bunch of
-;; instruction variants:
-;;
-;; ADD[32]{i,r}le for the little-endian ISA
-;; ADD[32]{i,r}be for the big-endian ISA
-;;
-;; The `i' variants perform `dst OP imm32 -> dst' operations.
-;; The `r' variants perform `dst OP src -> dst' operations.
-;;
-;; The variants with 32 in their name are of ALU class. Otherwise
-;; they are ALU64 class.
-
-(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code
- x-endian x-mode x-semop)
- (dni (.sym x-basename x-suffix x-endian)
- (.str x-basename x-suffix)
- (endian-isas x-endian)
- (.str x-basename x-suffix " $dst" x-endian)
- (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K x-op-code)
- (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian)))
- ()))
-
-(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
- x-endian x-mode x-semop x-isas)
- (begin
- ;; dst = dst OP immediate
- (dni (.sym x-basename x-suffix "i" x-endian)
- (.str x-basename x-suffix " immediate")
- (.splice (.unsplice x-isas))
- (.str x-basename x-suffix " $dst" x-endian ",$imm32")
- (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K x-op-code)
- (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32))
- ())
- ;; dst = dst OP src
- (dni (.sym x-basename x-suffix "r" x-endian)
- (.str x-basename x-suffix " register")
- (.splice (.unsplice x-isas))
- (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
- (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
- x-op-class OP_SRC_X x-op-code)
- (set x-mode (.sym dst x-endian)
- (x-semop x-mode (.sym dst x-endian) (.sym src x-endian)))
- ())))
-
-(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code
- x-endian x-mode)
- (begin
- (dni (.sym mov x-suffix "i" x-endian)
- (.str mov x-suffix " immediate")
- (endian-isas x-endian)
- (.str x-basename x-suffix " $dst" x-endian ",$imm32")
- (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K x-op-code)
- (set x-mode (.sym dst x-endian) imm32)
- ())
- (dni (.sym mov x-suffix "r" x-endian)
- (.str mov x-suffix " register")
- (endian-isas x-endian)
- (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
- (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
- x-op-class OP_SRC_X x-op-code)
- (set x-mode (.sym dst x-endian) (.sym src x-endian))
- ())))
-
-
-;; Unary ALU instructions (neg)
-(define-pmacro (daiu x-basename x-op-code x-endian x-semop)
- (begin
- (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
- (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
-
-;; Binary ALU instructions (all the others)
-;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
-(define-pmacro (daib x-basename x-op-code x-endian x-semop x-isas)
- (begin
- (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop x-isas)
- (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop x-isas)))
-
-;; Move ALU instructions (mov)
-(define-pmacro (daim x-basename x-op-code x-endian)
- (begin
- (define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI)
- (define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI)))
-
-(define-pmacro (define-alu-instructions x-endian)
- (begin
- (daib add OP_CODE_ADD x-endian add (endian-isas x-endian))
- (daib sub OP_CODE_SUB x-endian sub (endian-isas x-endian))
- (daib mul OP_CODE_MUL x-endian mul (endian-isas x-endian))
- (daib div OP_CODE_DIV x-endian udiv (endian-isas x-endian))
- (daib or OP_CODE_OR x-endian or (endian-isas x-endian))
- (daib and OP_CODE_AND x-endian and (endian-isas x-endian))
- (daib lsh OP_CODE_LSH x-endian sll (endian-isas x-endian))
- (daib rsh OP_CODE_RSH x-endian srl (endian-isas x-endian))
- (daib mod OP_CODE_MOD x-endian umod (endian-isas x-endian))
- (daib xor OP_CODE_XOR x-endian xor (endian-isas x-endian))
- (daib arsh OP_CODE_ARSH x-endian sra (endian-isas x-endian))
- (daib sdiv OP_CODE_SDIV x-endian div ((ISA (.sym xbpf x-endian))))
- (daib smod OP_CODE_SMOD x-endian mod ((ISA (.sym xbpf x-endian))))
- (daiu neg OP_CODE_NEG x-endian neg)
- (daim mov OP_CODE_MOV x-endian)))
-
-(define-alu-instructions le)
-(define-alu-instructions be)
-
-;;; Endianness conversion instructions
-
-;; The endianness conversion instructions come in several variants:
-;;
-;; END{le,be}le for the little-endian ISA
-;; END{le,be}be for the big-endian ISA
-;;
-;; Please do not be confused by the repeated `be' and `le' here. Each
-;; ISA has both endle and endbe instructions. It is the disposition
-;; of the source and destination register fields that change between
-;; ISAs, not the semantics of the instructions themselves (see section
-;; "The ISAs" above in this very file.)
-
-(define-pmacro (define-endian-insn x-suffix x-op-src x-endian)
- (dni (.sym "end" x-suffix x-endian)
- (.str "end" x-suffix " register")
- (endian-isas x-endian)
- (.str "end" x-suffix " $dst" x-endian ",$endsize")
- (+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
- OP_CLASS_ALU x-op-src OP_CODE_END)
- (set (.sym dst x-endian)
- (c-call DI (.str "bpfbf_end" x-suffix) (.sym dst x-endian) endsize))
- ()))
-
-(define-endian-insn "le" OP_SRC_K le)
-(define-endian-insn "be" OP_SRC_X le)
-(define-endian-insn "le" OP_SRC_K be)
-(define-endian-insn "be" OP_SRC_X be)
-
-;;; Load/Store instructions
-
-;; The lddw instruction takes a 64-bit immediate as an operand. Since
-;; this instruction also takes a `dst' operand, we need to define a
-;; variant for each ISA:
-;;
-;; LDDWle for the little-endian ISA
-;; LDDWbe for the big-endian ISA
-
-(define-pmacro (define-lddw x-endian)
- (dni (.sym lddw x-endian)
- (.str "lddw" x-endian)
- (endian-isas x-endian)
- (.str "lddw $dst" x-endian ",$imm64")
- (+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
- (.sym dst x-endian)
- OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM)
- (set DI (.sym dst x-endian) imm64)
- ()))
-
-(define-lddw le)
-(define-lddw be)
-
-;; The absolute load instructions are non-generic loads designed to be
-;; used in socket filters. They come in several variants:
-;;
-;; LDABS{w,h,b,dw}
-
-(define-pmacro (dlabs x-suffix x-size x-smode)
- (dni (.sym "ldabs" x-suffix)
- (.str "ldabs" x-suffix)
- (all-isas)
- (.str "ldabs" x-suffix " $imm32")
- (+ imm32 (f-offset16 0) (f-regs 0)
- OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
- (set x-smode
- (reg x-smode h-gpr 0)
- (mem x-smode
- (add DI
- (mem DI
- (add DI
- (reg DI h-gpr 6) ;; Pointer to struct sk_buff
- (c-call "bpfbf_skb_data_offset")))
- imm32)))
- ;; XXX this clobbers R1-R5
- ()))
-
-(dlabs "w" W SI)
-(dlabs "h" H HI)
-(dlabs "b" B QI)
-(dlabs "dw" DW DI)
-
-;; The indirect load instructions are non-generic loads designed to be
-;; used in socket filters. They come in several variants:
-;;
-;; LDIND{w,h,b,dw}le for the little-endian ISA
-;; LDIND[w,h,b,dw}be for the big-endian ISA
-
-(define-pmacro (dlind x-suffix x-size x-endian x-smode)
- (dni (.sym "ldind" x-suffix x-endian)
- (.str "ldind" x-suffix)
- (endian-isas x-endian)
- (.str "ldind" x-suffix " $src" x-endian ",$imm32")
- (+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
- OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
- (set x-smode
- (reg x-smode h-gpr 0)
- (mem x-smode
- (add DI
- (mem DI
- (add DI
- (reg DI h-gpr 6) ;; Pointer to struct sk_buff
- (c-call "bpfbf_skb_data_offset")))
- (add DI
- (.sym src x-endian)
- imm32))))
- ;; XXX this clobbers R1-R5
- ()))
-
-(define-pmacro (define-ldind x-endian)
- (begin
- (dlind "w" W x-endian SI)
- (dlind "h" H x-endian HI)
- (dlind "b" B x-endian QI)
- (dlind "dw" DW x-endian DI)))
-
-(define-ldind le)
-(define-ldind be)
-
-;; Generic load and store instructions are provided for several word
-;; sizes. They come in several variants:
-;;
-;; LDX{b,h,w,dw}le, STX{b,h,w,dw}le for the little-endian ISA
-;;
-;; LDX{b,h,w,dw}be, STX{b,h,w,dw}be for the big-endian ISA
-;;
-;; Loads operate on [$SRC+-OFFSET] -> $DST
-;; Stores operate on $SRC -> [$DST+-OFFSET]
-
-(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
- (dni (.sym x-basename x-suffix x-endian)
- (.str x-basename x-suffix)
- (endian-isas x-endian)
- (.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
- (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
- OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
- (set x-mode
- (.sym dst x-endian)
- (mem x-mode (add DI (.sym src x-endian) offset16)))
- ()))
-
-(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
- (dni (.sym x-basename x-suffix x-endian)
- (.str x-basename x-suffix)
- (endian-isas x-endian)
- (.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
- (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
- OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
- (set x-mode
- (mem x-mode (add DI (.sym dst x-endian) offset16))
- (.sym src x-endian)) ;; XXX address is section-relative
- ()))
-
-(define-pmacro (define-ldstx-insns x-endian)
- (begin
- (dxli "ldx" "w" W x-endian SI)
- (dxli "ldx" "h" H x-endian HI)
- (dxli "ldx" "b" B x-endian QI)
- (dxli "ldx" "dw" DW x-endian DI)
-
- (dxsi "stx" "w" W x-endian SI)
- (dxsi "stx" "h" H x-endian HI)
- (dxsi "stx" "b" B x-endian QI)
- (dxsi "stx" "dw" DW x-endian DI)))
-
-(define-ldstx-insns le)
-(define-ldstx-insns be)
-
-;; Generic store instructions of the form IMM32 -> [$DST+OFFSET] are
-;; provided in several variants:
-;;
-;; ST{b,h,w,dw}le for the little-endian ISA
-;; ST{b,h,w,dw}be for the big-endian ISA
-
-(define-pmacro (dsti x-suffix x-size x-endian x-mode)
- (dni (.sym "st" x-suffix x-endian)
- (.str "st" x-suffix)
- (endian-isas x-endian)
- (.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
- (+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
- OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
- (set x-mode
- (mem x-mode (add DI (.sym dst x-endian) offset16))
- imm32) ;; XXX address is section-relative
- ()))
-
-(define-pmacro (define-st-insns x-endian)
- (begin
- (dsti "b" B x-endian QI)
- (dsti "h" H x-endian HI)
- (dsti "w" W x-endian SI)
- (dsti "dw" DW x-endian DI)))
-
-(define-st-insns le)
-(define-st-insns be)
-
-;;; Jump instructions
-
-;; Compare-and-jump instructions, on the other hand, make use of
-;; registers. Therefore, we need to define several variants in both
-;; ISAs:
-;;
-;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}[32]{i,r}le for the
-;; little-endian ISA.
-;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
-;; big-endian ISA.
-
-(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop)
- (begin
- (dni (.sym j x-cond x-suffix i x-endian)
- (.str j x-cond x-suffix " i")
- (endian-isas x-endian)
- (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
- (+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
- (if VOID (x-semop x-mode (.sym dst x-endian) imm32)
- (set DI
- (reg DI h-pc) (add DI (reg DI h-pc)
- (mul DI (add HI disp16 1) 8))))
- ())
- (dni (.sym j x-cond x-suffix r x-endian)
- (.str j x-cond x-suffix " r")
- (endian-isas x-endian)
- (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
- (+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
- x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
- (if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))
- (set DI
- (reg DI h-pc) (add DI (reg DI h-pc)
- (mul DI (add HI disp16 1) 8))))
- ())))
-
-(define-pmacro (dcji x-cond x-op-code x-endian x-semop)
- (begin
- (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop)
- (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop )))
-
-(define-pmacro (define-condjump-insns x-endian)
- (begin
- (dcji "eq" JEQ x-endian eq)
- (dcji "gt" JGT x-endian gtu)
- (dcji "ge" JGE x-endian geu)
- (dcji "lt" JLT x-endian ltu)
- (dcji "le" JLE x-endian leu)
- (dcji "set" JSET x-endian and)
- (dcji "ne" JNE x-endian ne)
- (dcji "sgt" JSGT x-endian gt)
- (dcji "sge" JSGE x-endian ge)
- (dcji "slt" JSLT x-endian lt)
- (dcji "sle" JSLE x-endian le)))
-
-(define-condjump-insns le)
-(define-condjump-insns be)
-
-;; The `call' instruction doesn't make use of registers, but the
-;; semantic routine should have access to the src register in order to
-;; properly interpret the meaning of disp32. Therefore we need one
-;; version per ISA.
-
-(define-pmacro (define-call-insn x-endian)
- (dni (.sym call x-endian)
- "call"
- (endian-isas x-endian)
- "call $disp32"
- (+ disp32 (f-offset16 0) (.sym src x-endian) ((.sym f-dst x-endian) 0)
- OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
- (c-call VOID
- "bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
- ()))
-
-(define-call-insn le)
-(define-call-insn be)
-
-(define-pmacro (define-callr-insn x-endian)
- (dni (.sym callr x-endian)
- "callr"
- ((ISA (.sym xbpf x-endian)))
- (.str "call $dst" x-endian)
- (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- OP_CLASS_JMP OP_SRC_X OP_CODE_CALL)
- (c-call VOID
- "bpfbf_callr" (ifield (.sym f-dst x-endian)))
- ()))
-
-(define-callr-insn le)
-(define-callr-insn be)
-
-;; The jump-always and `exit' instructions dont make use of either
-;; source nor destination registers, so only one variant per
-;; instruction is defined.
-
-(dni ja "ja" (all-isas) "ja $disp16"
- (+ (f-imm32 0) disp16 (f-regs 0)
- OP_CLASS_JMP OP_SRC_K OP_CODE_JA)
- (set DI (reg DI h-pc) (add DI (reg DI h-pc)
- (mul DI (add HI disp16 1) 8)))
- ())
-
-(dni "exit" "exit" (all-isas) "exit"
- (+ (f-imm32 0) (f-offset16 0) (f-regs 0)
- OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT)
- (c-call VOID "bpfbf_exit")
- ())
-
-;;; Atomic instructions
-
-;; The atomic exchange-and-add instructions come in two flavors: one
-;; for swapping 64-bit quantities and another for 32-bit quantities.
-
-(define-pmacro (sem-exchange-and-add x-endian x-mode)
- (sequence VOID ((x-mode tmp))
- ;; XXX acquire lock in simulator... as a hardware element?
- (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16)))
- (set x-mode
- (mem x-mode (add DI (.sym dst x-endian) offset16))
- (add x-mode tmp (.sym src x-endian)))))
-
-(define-pmacro (define-atomic-insns x-endian)
- (begin
- (dni (.str "xadddw" x-endian)
- "xadddw"
- (endian-isas x-endian)
- (.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
- (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
- offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
- (sem-exchange-and-add x-endian DI)
- ())
- (dni (.str "xaddw" x-endian)
- "xaddw"
- (endian-isas x-endian)
- (.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
- (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
- offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)
- (sem-exchange-and-add x-endian SI)
- ())))
-
-(define-atomic-insns le)
-(define-atomic-insns be)
-
-;;; Breakpoint instruction
-
-;; The brkpt instruction is used by the BPF simulator and it doesn't
-;; really belong to the eBPF instruction set.
-
-(dni "brkpt" "brkpt" (all-isas) "brkpt"
- (+ (f-imm32 0) (f-offset16 0) (f-regs 0)
- OP_CLASS_ALU OP_SRC_X OP_CODE_NEG)
- (c-call VOID "bpfbf_breakpoint")
- ())
+++ /dev/null
-/* EBPF opcode support. -*- c -*-
-
- Copyright (C) 2019 Free Software Foundation, Inc.
-
- Contributed by Oracle, Inc.
-
- This file is part of the GNU Binutils and of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-/*
- Each section is delimited with start and end markers.
-
- <arch>-opc.h additions use: "-- opc.h"
- <arch>-opc.c additions use: "-- opc.c"
- <arch>-asm.c additions use: "-- asm.c"
- <arch>-dis.c additions use: "-- dis.c"
- <arch>-ibd.h additions use: "-- ibd.h". */
-\f
-/* -- opc.h */
-
-#undef CGEN_DIS_HASH_SIZE
-#define CGEN_DIS_HASH_SIZE 1
-
-#undef CGEN_DIS_HASH
-#define CGEN_DIS_HASH(buffer, value) 0
-
-/* Allows reason codes to be output when assembler errors occur. */
-#define CGEN_VERBOSE_ASSEMBLER_ERRORS
-
-#define CGEN_VALIDATE_INSN_SUPPORTED
-extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
-
-\f
-/* -- opc.c */
-\f
-/* -- asm.c */
-
-/* Parse a signed 64-bit immediate. */
-
-static const char *
-parse_imm64 (CGEN_CPU_DESC cd,
- const char **strp,
- int opindex,
- int64_t *valuep)
-{
- bfd_vma value;
- enum cgen_parse_operand_result result;
- const char *errmsg;
-
- errmsg = (* cd->parse_operand_fn)
- (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
- &result, &value);
- if (!errmsg)
- *valuep = value;
-
- return errmsg;
-}
-
-/* Endianness size operands are integer immediates whose values can be
- 16, 32 or 64. */
-
-static const char *
-parse_endsize (CGEN_CPU_DESC cd,
- const char **strp,
- int opindex,
- unsigned long *valuep)
-{
- const char *errmsg;
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
- if (errmsg)
- return errmsg;
-
- switch (*valuep)
- {
- case 16:
- case 32:
- case 64:
- break;
- default:
- return _("expected 16, 32 or 64 in");
- }
-
- return NULL;
-}
-
-/* Special check to ensure that the right instruction variant is used
- for the given endianness induced by the ISA selected in the CPU.
- See bpf.cpu for a discussion on how eBPF is really two instruction
- sets. */
-
-int
-bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
-{
- CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
-
- return cgen_bitset_intersect_p (&isas, cd->isas);
-}
-
-\f
-/* -- dis.c */
-
-/* We need to customize the disassembler a bit:
- - Use 8 bytes per line by default.
-*/
-
-#define CGEN_PRINT_INSN bpf_print_insn
-
-static int
-bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
- int buflen;
- int status;
-
- info->bytes_per_chunk = 1;
- info->bytes_per_line = 8;
-
- /* Attempt to read the base part of the insn. */
- buflen = cd->base_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- /* Try again with the minimum part, if min < base. */
- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
- {
- buflen = cd->min_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
- }
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- return print_insn (cd, pc, info, buf, buflen);
-}
-
-/* Signed immediates should be printed in hexadecimal. */
-
-static void
-print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- int64_t value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- if (value <= 9)
- (*info->fprintf_func) (info->stream, "%" PRId64, value);
- else
- (*info->fprintf_func) (info->stream, "%#" PRIx64, value);
-
- /* This is to avoid -Wunused-function for print_normal. */
- if (0)
- print_normal (cd, dis_info, value, attrs, pc, length);
-}
-
-/* Endianness bit sizes should be printed in decimal. */
-
-static void
-print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- unsigned long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
- (*info->fprintf_func) (info->stream, "%lu", value);
-}
-
-\f
-/* -- */
-
#include "as.h"
#include "subsegs.h"
#include "symcat.h"
-#include "opcodes/bpf-desc.h"
-#include "opcodes/bpf-opc.h"
-#include "cgen.h"
+#include "opcode/bpf.h"
#include "elf/common.h"
#include "elf/bpf.h"
#include "dwarf2dbg.h"
+#include "libiberty.h"
#include <ctype.h>
+/* Data structure representing a parsed BPF instruction. */
+
+struct bpf_insn
+{
+ int size; /* Instruction size in bytes. */
+ bpf_insn_word opcode;
+ uint8_t dst;
+ uint8_t src;
+ expressionS offset16;
+ expressionS imm32;
+ expressionS imm64;
+ expressionS disp16;
+ expressionS disp32;
+
+ unsigned int has_dst : 1;
+ unsigned int has_src : 1;
+ unsigned int has_offset16 : 1;
+ unsigned int has_disp16 : 1;
+ unsigned int has_disp32 : 1;
+ unsigned int has_imm32 : 1;
+ unsigned int has_imm64 : 1;
+};
+
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
const char line_separator_chars[] = "`";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "fFdD";
-static const char *invalid_expression;
-static char pseudoc_lex[256];
-static const char symbol_chars[] =
-"_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789";
-
-static const char arithm_op[] = "+-/<>%&|^";
-
-static void init_pseudoc_lex (void);
-
-#define LEX_IS_SYMBOL_COMPONENT 1
-#define LEX_IS_WHITESPACE 2
-#define LEX_IS_NEWLINE 3
-#define LEX_IS_ARITHM_OP 4
-#define LEX_IS_STAR 6
-#define LEX_IS_CLSE_BR 7
-#define LEX_IS_OPEN_BR 8
-#define LEX_IS_EQUAL 9
-#define LEX_IS_EXCLA 10
-
-#define ST_EOI 100
-#define MAX_TOKEN_SZ 100
-
/* Like s_lcomm_internal in gas/read.c but the alignment string
is allowed to be optional. */
\f
-/* ISA handling. */
-static CGEN_BITSET *bpf_isa;
-
-\f
-
/* Command-line options processing. */
enum options
{
OPTION_LITTLE_ENDIAN = OPTION_MD_BASE,
OPTION_BIG_ENDIAN,
- OPTION_XBPF
+ OPTION_XBPF,
+ OPTION_DIALECT,
+ OPTION_ISA_SPEC,
};
struct option md_longopts[] =
{ "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN },
{ "EB", no_argument, NULL, OPTION_BIG_ENDIAN },
{ "mxbpf", no_argument, NULL, OPTION_XBPF },
+ { "mdialect", required_argument, NULL, OPTION_DIALECT},
+ { "misa-spec", required_argument, NULL, OPTION_ISA_SPEC},
{ NULL, no_argument, NULL, 0 },
};
const char * md_shortopts = "";
-extern int target_big_endian;
+/* BPF supports little-endian and big-endian variants. The following
+ global records what endianness to use. It can be configured using
+ command-line options. It defaults to the host endianness
+ initialized in md_begin. */
-/* Whether target_big_endian has been set while parsing command-line
- arguments. */
static int set_target_endian = 0;
+extern int target_big_endian;
+
+/* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4
+ or BPF_XPBF. The ISA spec to use can be configured using
+ command-line options. It defaults to the latest BPF spec. */
+
+static int isa_spec = BPF_V4;
-static int target_xbpf = 0;
+/* The assembler supports two different dialects: "normal" syntax and
+ "pseudoc" syntax. The dialect to use can be configured using
+ command-line options. */
-static int set_xbpf = 0;
+enum target_asm_dialect
+{
+ DIALECT_NORMAL,
+ DIALECT_PSEUDOC
+};
+
+static int asm_dialect = DIALECT_NORMAL;
int
-md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+md_parse_option (int c, const char * arg)
{
switch (c)
{
target_big_endian = 1;
break;
case OPTION_LITTLE_ENDIAN:
- set_target_endian = 1;
+ set_target_endian = 0;
target_big_endian = 0;
break;
+ case OPTION_DIALECT:
+ if (strcmp (arg, "normal") == 0)
+ asm_dialect = DIALECT_NORMAL;
+ else if (strcmp (arg, "pseudoc") == 0)
+ asm_dialect = DIALECT_PSEUDOC;
+ else
+ as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"),
+ arg);
+ break;
+ case OPTION_ISA_SPEC:
+ if (strcmp (arg, "v1") == 0)
+ isa_spec = BPF_V1;
+ else if (strcmp (arg, "v2") == 0)
+ isa_spec = BPF_V2;
+ else if (strcmp (arg, "v3") == 0)
+ isa_spec = BPF_V3;
+ else if (strcmp (arg, "v4") == 0)
+ isa_spec = BPF_V4;
+ else if (strcmp (arg, "xbpf") == 0)
+ isa_spec = BPF_XBPF;
+ else
+ as_fatal (_("-misa-spec=%s is not valid. Expected v1, v2, v3, v4 o xbpf"),
+ arg);
+ break;
case OPTION_XBPF:
- set_xbpf = 1;
- target_xbpf = 1;
+ /* This is an alias for -misa-spec=xbpf. */
+ isa_spec = BPF_XBPF;
break;
default:
return 0;
{
fprintf (stream, _("\nBPF options:\n"));
fprintf (stream, _("\
- --EL generate code for a little endian machine\n\
- --EB generate code for a big endian machine\n\
- -mxbpf generate xBPF instructions\n"));
+BPF options:\n\
+ -EL generate code for a little endian machine\n\
+ -EB generate code for a big endian machine\n\
+ -mdialect=DIALECT set the assembly dialect (normal, pseudoc)\n\
+ -misa-spec set the BPF ISA spec (v1, v2, v3, v4, xbpf)\n\
+ -mxbpf alias for -misa-spec=xbpf\n"));
}
\f
-
-static void
-init_pseudoc_lex (void)
-{
- const char *p;
-
- for (p = symbol_chars; *p; ++p)
- pseudoc_lex[(unsigned char) *p] = LEX_IS_SYMBOL_COMPONENT;
-
- pseudoc_lex[' '] = LEX_IS_WHITESPACE;
- pseudoc_lex['\t'] = LEX_IS_WHITESPACE;
- pseudoc_lex['\r'] = LEX_IS_WHITESPACE;
- pseudoc_lex['\n'] = LEX_IS_NEWLINE;
- pseudoc_lex['*'] = LEX_IS_STAR;
- pseudoc_lex[')'] = LEX_IS_CLSE_BR;
- pseudoc_lex['('] = LEX_IS_OPEN_BR;
- pseudoc_lex[']'] = LEX_IS_CLSE_BR;
- pseudoc_lex['['] = LEX_IS_OPEN_BR;
-
- for (p = arithm_op; *p; ++p)
- pseudoc_lex[(unsigned char) *p] = LEX_IS_ARITHM_OP;
-
- pseudoc_lex['='] = LEX_IS_EQUAL;
- pseudoc_lex['!'] = LEX_IS_EXCLA;
-}
+/* This function is called once, at assembler startup time. This
+ should set up all the tables, etc that the MD part of the assembler
+ needs. */
void
md_begin (void)
{
- /* Initialize the `cgen' interface. */
-
/* If not specified in the command line, use the host
endianness. */
if (!set_target_endian)
#endif
}
- /* If not specified in the command line, use eBPF rather
- than xBPF. */
- if (!set_xbpf)
- target_xbpf = 0;
-
- /* Set the ISA, which depends on the target endianness. */
- bpf_isa = cgen_bitset_create (ISA_MAX);
- if (target_big_endian)
- {
- if (target_xbpf)
- cgen_bitset_set (bpf_isa, ISA_XBPFBE);
- else
- cgen_bitset_set (bpf_isa, ISA_EBPFBE);
- }
- else
- {
- if (target_xbpf)
- cgen_bitset_set (bpf_isa, ISA_XBPFLE);
- else
- cgen_bitset_set (bpf_isa, ISA_EBPFLE);
- }
-
/* Ensure that lines can begin with '*' in BPF store pseudoc instruction. */
lex_type['*'] |= LEX_BEGIN_NAME;
- /* Set the machine number and endian. */
- gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,
- target_big_endian ?
- CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE,
- CGEN_CPU_OPEN_INSN_ENDIAN,
- CGEN_ENDIAN_LITTLE,
- CGEN_CPU_OPEN_ISAS,
- bpf_isa,
- CGEN_CPU_OPEN_END);
- bpf_cgen_init_asm (gas_cgen_cpu_desc);
-
- /* This is a callback from cgen to gas to parse operands. */
- cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
-
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf);
- init_pseudoc_lex();
}
+/* Round up a section size to the appropriate boundary. */
+
valueT
md_section_align (segT segment, valueT size)
{
}
arelent *
-tc_gen_reloc (asection *sec, fixS *fix)
+tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixP)
{
- return gas_cgen_tc_gen_reloc (sec, fix);
-}
+ bfd_reloc_code_real_type r_type = fixP->fx_r_type;
+ arelent *reloc;
-/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. This
- is called when the operand is an expression that couldn't be fully
- resolved. Returns BFD_RELOC_NONE if no reloc type can be found.
- *FIXP may be modified if desired. */
+ reloc = XNEW (arelent);
-bfd_reloc_code_real_type
-md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
- const CGEN_OPERAND *operand,
- fixS *fixP)
-{
- switch (operand->type)
+ if (fixP->fx_pcrel)
+ {
+ r_type = (r_type == BFD_RELOC_8 ? BFD_RELOC_8_PCREL
+ : r_type == BFD_RELOC_16 ? BFD_RELOC_16_PCREL
+ : r_type == BFD_RELOC_24 ? BFD_RELOC_24_PCREL
+ : r_type == BFD_RELOC_32 ? BFD_RELOC_32_PCREL
+ : r_type == BFD_RELOC_64 ? BFD_RELOC_64_PCREL
+ : r_type);
+ }
+
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type);
+
+ if (reloc->howto == (reloc_howto_type *) NULL)
{
- case BPF_OPERAND_IMM64:
- return BFD_RELOC_BPF_64;
- case BPF_OPERAND_DISP32:
- fixP->fx_pcrel = 1;
- return BFD_RELOC_BPF_DISP32;
- default:
- break;
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("relocation is not supported"));
+ return NULL;
}
- return BFD_RELOC_NONE;
+
+ //XXX gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+
+ /* Use fx_offset for these cases. */
+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT)
+ reloc->addend = fixP->fx_offset;
+ else
+ reloc->addend = fixP->fx_addnumber;
+
+ reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+ return reloc;
}
+
\f
/* *FRAGP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
}
\f
+/* Apply a fixS (fixup of an instruction or data that we didn't have
+ enough info to complete immediately) to the data in a frag. */
+
void
-md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
{
- /* Some fixups for instructions require special attention. This is
- handled in the code block below. */
- if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+ char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+ switch (fixP->fx_r_type)
{
- int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
- const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
- opindex);
- char *where;
+ case BFD_RELOC_BPF_DISP16:
+ /* Convert from bytes to number of 64-bit words to the target,
+ minus one. */
+ *valP = (((long) (*valP)) - 8) / 8;
+ break;
+ case BFD_RELOC_BPF_DISP32:
+ /* eBPF supports two kind of CALL instructions: the so called
+ pseudo calls ("bpf to bpf") and external calls ("bpf to
+ kernel").
+
+ Both kind of calls use the same instruction (CALL). However,
+ external calls are constructed by passing a constant argument
+ to the instruction, whereas pseudo calls result from
+ expressions involving symbols. In practice, instructions
+ requiring a fixup are interpreted as pseudo-calls. If we are
+ executing this code, this is a pseudo call.
+
+ The kernel expects for pseudo-calls to be annotated by having
+ BPF_PSEUDO_CALL in the SRC field of the instruction. But
+ beware the infamous nibble-swapping of eBPF and take
+ endianness into account here.
+
+ Note that the CALL instruction has only one operand, so
+ this code is executed only once per instruction. */
+ md_number_to_chars (where + 1, target_big_endian ? 0x01 : 0x10, 1);
+
+ /* Convert from bytes to number of 64-bit words to the target,
+ minus one. */
+ *valP = (((long) (*valP)) - 8) / 8;
+ break;
+ case BFD_RELOC_16_PCREL:
+ /* Convert from bytes to number of 64-bit words to the target,
+ minus one. */
+ *valP = (((long) (*valP)) - 8) / 8;
+ break;
+ default:
+ break;
+ }
- switch (operand->type)
- {
- case BPF_OPERAND_DISP32:
- /* eBPF supports two kind of CALL instructions: the so
- called pseudo calls ("bpf to bpf") and external calls
- ("bpf to kernel").
-
- Both kind of calls use the same instruction (CALL).
- However, external calls are constructed by passing a
- constant argument to the instruction, whereas pseudo
- calls result from expressions involving symbols. In
- practice, instructions requiring a fixup are interpreted
- as pseudo-calls. If we are executing this code, this is
- a pseudo call.
-
- The kernel expects for pseudo-calls to be annotated by
- having BPF_PSEUDO_CALL in the SRC field of the
- instruction. But beware the infamous nibble-swapping of
- eBPF and take endianness into account here.
-
- Note that the CALL instruction has only one operand, so
- this code is executed only once per instruction. */
- where = fixP->fx_frag->fr_literal + fixP->fx_where + 1;
- where[0] = target_big_endian ? 0x01 : 0x10;
- /* Fallthrough. */
- case BPF_OPERAND_DISP16:
- /* The PC-relative displacement fields in jump instructions
- shouldn't be in bytes. Instead, they hold the number of
- 64-bit words to the target, _minus one_. */
- *valP = (((long) (*valP)) - 8) / 8;
+ if (fixP->fx_addsy == (symbolS *) NULL)
+ fixP->fx_done = 1;
+
+ if (fixP->fx_done)
+ {
+ /* We're finished with this fixup. Install it because
+ bfd_install_relocation won't be called to do it. */
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_8:
+ md_number_to_chars (where, *valP, 1);
+ break;
+ case BFD_RELOC_16:
+ md_number_to_chars (where, *valP, 2);
+ break;
+ case BFD_RELOC_32:
+ md_number_to_chars (where, *valP, 4);
+ break;
+ case BFD_RELOC_64:
+ md_number_to_chars (where, *valP, 8);
+ break;
+ case BFD_RELOC_BPF_DISP16:
+ md_number_to_chars (where + 2, (uint16_t) *valP, 2);
break;
- default:
+ case BFD_RELOC_BPF_DISP32:
+ md_number_to_chars (where + 4, (uint32_t) *valP, 4);
break;
- }
+ case BFD_RELOC_16_PCREL:
+ md_number_to_chars (where + 2, (uint32_t) *valP, 2);
+ break;
+ default:
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("internal error: can't install fix for reloc type %d (`%s')"),
+ fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type));
+ break;
+ }
}
- /* And now invoke CGEN's handler, which will eventually install
- *valP into the corresponding operand. */
- gas_cgen_md_apply_fix (fixP, valP, seg);
+ /* Tuck `value' away for use by tc_gen_reloc.
+ See the comment describing fx_addnumber in write.h.
+ This field is misnamed (or misused :-). */
+ fixP->fx_addnumber = *valP;
}
-/*
- The BPF pseudo grammar:
-
- instruction : bpf_alu_insn
- | bpf_alu32_insn
- | bpf_jump_insn
- | bpf_load_store_insn
- | bpf_load_store32_insn
- | bpf_non_generic_load
- | bpf_endianness_conv_insn
- | bpf_64_imm_load_insn
- | bpf_atomic_insn
- ;
-
- bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32
- ;
-
- bpf_alu32_insn : BPF_REG32 bpf_alu_operator register32_or_imm32
- ;
-
- bpf_jump_insn : BPF_JA offset
- | IF BPF_REG bpf_jump_operator register_or_imm32 BPF_JA offset
- | IF BPF_REG32 bpf_jump_operator register_or_imm32 BPF_JA offset
- | BPF_CALL offset
- | BPF_EXIT
- ;
-
- bpf_load_store_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \
- register_and_offset BPF_CHR_CLSE_BR
- | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG
- ;
-
- bpf_load_store32_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \
- register32_and_offset BPF_CHR_CLSE_BR
- | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG32
- ;
-
- bpf_non_generic_load : BPF_REG_R0 CHR_EQUAL bpf_size_cast BPF_LD BPF_CHR_OPEN_BR \
- imm32 BPF_CHR_CLSE_BR
- ;
-
- bpf_endianness_conv_insn : BPF_REG_N bpf_endianness_mnem BPF_REG_N
- ;
-
- bpf_64_imm_load_insn : BPF_REG imm64 BPF_LL
- ;
-
- bpf_atomic_insn : BPF_LOCK bpf_size_cast_32_64 register_and_offset BPF_ADD BPF_REG
-
- register_and_offset : BPF_CHR_OPEN_BR BPF_REG offset BPF_CHR_CLSE_BR
- ;
-
- register32_and_offset : BPF_CHR_OPEN_BR BPF_REG32 offset BPF_CHR_CLSE_BR
- ;
-
- bpf_size_cast : CHR_START BPF_CHR_OPEN_BR bpf_size CHR_START BPF_CHR_CLSE_BR
- ;
-
- bpf_size_cast_32_64 : CHR_START BPF_CHR_OPEN_BR bpf_size_cast_32_64 CHR_STAR BPF_CHR_CLSE_BR
- ;
-
- bpf_size_32_64 : BPF_CAST_U32
- | BPF_CAST_U64
- ;
-
- bpf_size : BPF_CAST_U8
- | BPF_CAST_U16
- | BPF_CAST_U32
- | BPF_CAST_U64
- ;
-
- bpf_jump_operator : BPF_JEQ
- | BPF_JGT
- | BPF_JGE
- | BPF_JNE
- | BPF_JSGT
- | BPF_JSGE
- | BPF_JLT
- | BPF_JLE
- | BPF_JSLT
- | BPF_JSLE
- ;
-
- bpf_alu_operator : BPF_ADD
- | BPF_SUB
- | BPF_MUL
- | BPF_DIV
- | BPF_OR
- | BPF_AND
- | BPF_LSH
- | BPF_RSH
- | BPF_NEG
- | BPF_MOD
- | BPF_XOR
- | BPF_ARSH
- | CHR_EQUAL
- ;
-
- bpf_endianness_mnem : BPF_LE16
- | BPF_LE32
- | BPF_LE64
- | BPF_BE16
- | BPF_BE32
- | BPF_BE64
- ;
-
- offset : BPF_EXPR
- | BPF_SYMBOL
- ;
-
- register_or_imm32 : BPF_REG
- | expression
- ;
-
- register32_or_imm32 : BPF_REG32
- | expression
- ;
-
- imm32 : BPF_EXPR
- | BPF_SYMBOL
- ;
-
- imm64 : BPF_EXPR
- | BPF_SYMBOL
- ;
-
- register_or_expression : BPF_EXPR
- | BPF_REG
- ;
-
- BPF_EXPR : GAS_EXPR
-
-*/
-
-enum bpf_token_type
- {
- /* Keep grouped to quickly access. */
- BPF_ADD,
- BPF_SUB,
- BPF_MUL,
- BPF_DIV,
- BPF_OR,
- BPF_AND,
- BPF_LSH,
- BPF_RSH,
- BPF_MOD,
- BPF_XOR,
- BPF_MOV,
- BPF_ARSH,
- BPF_NEG,
-
- BPF_REG,
-
- BPF_IF,
- BPF_GOTO,
-
- /* Keep grouped to quickly access. */
- BPF_JEQ,
- BPF_JGT,
- BPF_JGE,
- BPF_JLT,
- BPF_JLE,
- BPF_JSET,
- BPF_JNE,
- BPF_JSGT,
- BPF_JSGE,
- BPF_JSLT,
- BPF_JSLE,
-
- BPF_SYMBOL,
- BPF_CHR_CLSE_BR,
- BPF_CHR_OPEN_BR,
-
- /* Keep grouped to quickly access. */
- BPF_CAST_U8,
- BPF_CAST_U16,
- BPF_CAST_U32,
- BPF_CAST_U64,
-
- /* Keep grouped to quickly access. */
- BPF_LE16,
- BPF_LE32,
- BPF_LE64,
- BPF_BE16,
- BPF_BE32,
- BPF_BE64,
-
- BPF_LOCK,
-
- BPF_IND_CALL,
- BPF_LD,
- BPF_LL,
- BPF_EXPR,
- BPF_UNKNOWN,
- };
-
-static int
-valid_expr (const char *e, const char **end_expr)
-{
- invalid_expression = NULL;
- char *hold = input_line_pointer;
- expressionS exp;
-
- input_line_pointer = (char *) e;
- deferred_expression (&exp);
- *end_expr = input_line_pointer;
- input_line_pointer = hold;
+/* Parse an operand expression. Returns the first character that is
+ not part of the expression, or NULL in case of parse error.
- return invalid_expression == NULL;
-}
+ See md_operand below to see how exp_parse_failed is used. */
-static char *
-build_bpf_non_generic_load (char *src, enum bpf_token_type cast,
- const char *imm32)
-{
- char *bpf_insn;
- static const char *cast_rw[] = {"b", "h", "w", "dw"};
-
- bpf_insn = xasprintf ("%s%s%s %s%s%s%s",
- "ld",
- src ? "ind" : "abs",
- cast_rw[cast - BPF_CAST_U8],
- src ? "%" : "",
- src ? src : "",
- src ? "," : "",
- imm32);
- return bpf_insn;
-}
+static int exp_parse_failed = 0;
static char *
-build_bpf_atomic_insn (char *dst, char *src,
- enum bpf_token_type atomic_insn,
- enum bpf_token_type cast,
- const char *offset)
+parse_expression (char *s, expressionS *exp)
{
- char *bpf_insn;
- static const char *cast_rw[] = {"w", "dw"};
- static const char *mnem[] = {"xadd"};
-
- bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", mnem[atomic_insn - BPF_ADD],
- cast_rw[cast - BPF_CAST_U32], dst,
- *offset != '+' ? "+" : "",
- offset, src);
- return bpf_insn;
-}
+ char *saved_input_line_pointer = input_line_pointer;
+ char *saved_s = s;
-static char *
-build_bpf_jmp_insn (char *dst, char *src,
- char *imm32, enum bpf_token_type op,
- const char *sym, const char *offset)
-{
- char *bpf_insn;
- static const char *mnem[] =
- {
- "jeq", "jgt", "jge", "jlt",
- "jle", "jset", "jne", "jsgt",
- "jsge", "jslt", "jsle"
- };
-
- const char *in32 = (*dst == 'w' ? "32" : "");
-
- *dst = 'r';
- if (src)
- *src = 'r';
-
- bpf_insn = xasprintf ("%s%s %%%s,%s%s,%s",
- mnem[op - BPF_JEQ], in32, dst,
- src ? "%" : "",
- src ? src : imm32,
- offset ? offset : sym);
- return bpf_insn;
-}
+ exp_parse_failed = 0;
+ input_line_pointer = s;
+ expression (exp);
+ s = input_line_pointer;
+ input_line_pointer = saved_input_line_pointer;
-static char *
-build_bpf_arithm_insn (char *dst, char *src,
- int load64, const char *imm32,
- enum bpf_token_type type)
-{
- char *bpf_insn;
- static const char *mnem[] =
- {
- "add", "sub", "mul", "div",
- "or", "and", "lsh", "rsh",
- "mod", "xor", "mov", "arsh",
- "neg",
- };
- const char *in32 = (*dst == 'w' ? "32" : "");
-
- *dst = 'r';
- if (src)
- *src = 'r';
-
- if (type == BPF_NEG)
- bpf_insn = xasprintf ("%s%s %%%s", mnem[type - BPF_ADD], in32, dst);
- else if (load64)
- bpf_insn = xasprintf ("%s %%%s,%s", "lddw", dst, imm32);
- else
- bpf_insn = xasprintf ("%s%s %%%s,%s%s", mnem[type - BPF_ADD],
- in32, dst,
- src ? "%" : "",
- src ? src: imm32);
- return bpf_insn;
-}
+ switch (exp->X_op == O_absent || exp_parse_failed)
+ return NULL;
-static char *
-build_bpf_endianness (char *dst, enum bpf_token_type endianness)
-{
- char *bpf_insn;
- static const char *size[] = {"16", "32", "64"};
- int be = 1;
-
- if (endianness == BPF_LE16
- || endianness == BPF_LE32
- || endianness == BPF_LE64)
- be = 0;
- else
- gas_assert (endianness == BPF_BE16 || endianness == BPF_BE32 || endianness == BPF_BE64);
+ /* The expression parser may consume trailing whitespaces. We have
+ to undo that since the instruction templates may be expecting
+ these whitespaces. */
+ {
+ char *p;
+ for (p = s - 1; p >= saved_s && *p == ' '; --p)
+ --s;
+ }
- bpf_insn = xasprintf ("%s %%%s,%s", be ? "endbe" : "endle",
- dst, be ? size[endianness - BPF_BE16] : size[endianness - BPF_LE16]);
- return bpf_insn;
+ return s;
}
-static char *
-build_bpf_load_store_insn (char *dst, char *src,
- enum bpf_token_type cast,
- const char *offset, int isload)
-{
- char *bpf_insn;
- static const char *cast_rw[] = {"b", "h", "w", "dw"};
-
- *dst = *src = 'r';
- if (isload)
- bpf_insn = xasprintf ("%s%s %%%s,[%%%s%s%s]", "ldx",
- cast_rw[cast - BPF_CAST_U8], dst, src,
- *offset != '+' ? "+" : "",
- offset);
- else
- bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", "stx",
- cast_rw[cast - BPF_CAST_U8], dst,
- *offset != '+' ? "+" : "",
- offset, src);
- return bpf_insn;
-}
+/* Parse a BPF register name and return the corresponding register
+ number. Return NULL in case of parse error, or a pointer to the
+ first character in S that is not part of the register name. */
-static int
-look_for_reserved_word (const char *token, enum bpf_token_type *type)
+static char *
+parse_bpf_register (char *s, char rw, uint8_t *regno)
{
- int i;
- static struct
- {
- const char *name;
- enum bpf_token_type type;
- } reserved_words[] =
+ if (asm_dialect == DIALECT_NORMAL)
{
- {
- .name = "if",
- .type = BPF_IF
- },
- {
- .name = "goto",
- .type = BPF_GOTO
- },
- {
- .name = "le16",
- .type = BPF_LE16
- },
- {
- .name = "le32",
- .type = BPF_LE32
- },
- {
- .name = "le64",
- .type = BPF_LE64
- },
- {
- .name = "be16",
- .type = BPF_BE16
- },
- {
- .name = "be32",
- .type = BPF_BE32
- },
- {
- .name = "be64",
- .type = BPF_BE64
- },
- {
- .name = "lock",
- .type = BPF_LOCK
- },
- {
- .name = "callx",
- .type = BPF_IND_CALL
- },
- {
- .name = "skb",
- .type = BPF_LD
- },
- {
- .name = "ll",
- .type = BPF_LL
- },
- {
- .name = NULL,
- }
- };
+ rw = 'r';
+ if (*s != '%')
+ return NULL;
+ s += 1;
- for (i = 0; reserved_words[i].name; ++i)
- if (*reserved_words[i].name == *token
- && !strcmp (reserved_words[i].name, token))
- {
- *type = reserved_words[i].type;
- return 1;
- }
+ if (*s == 'f' && *(s + 1) == 'p')
+ {
+ *regno = 10;
+ s += 2;
+ return s;
+ }
+ }
- return 0;
-}
+ if (*s != rw)
+ return NULL;
+ s += 1;
-static int
-is_register (const char *token, int len)
-{
- if (token[0] == 'r' || token[0] == 'w')
- if ((len == 2 && isdigit (token[1]))
- || (len == 3 && token[1] == '1' && token[2] == '0'))
- return 1;
+ if (*s == '1')
+ {
+ if (*(s + 1) == '0')
+ {
+ *regno = 10;
+ s += 2;
+ }
+ else
+ {
+ *regno = 1;
+ s += 1;
+ }
+ }
+ else if (*s >= '0' && *s <= '9')
+ {
+ *regno = *s - '0';
+ s += 1;
+ }
- return 0;
+ return s;
}
-static enum bpf_token_type
-is_cast (const char *token)
-{
- static const char *cast_rw[] = {"u8", "u16", "u32", "u64"};
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE (cast_rw); ++i)
- if (!strcmp (token, cast_rw[i]))
- return BPF_CAST_U8 + i;
+/* Collect a parse error message. */
- return BPF_UNKNOWN;
-}
+static int partial_match_length = 0;
+static char *errmsg = NULL;
-static enum bpf_token_type
-get_token (const char **insn, char *token, size_t *tlen)
+static void
+parse_error (int length, const char *fmt, ...)
{
-#define GET() \
- (*str == '\0' \
- ? EOF \
- : *(unsigned char *)(str++))
-
-#define UNGET() (--str)
-
-#define START_EXPR() \
- do \
- { \
- if (expr == NULL) \
- expr = str - 1; \
- } while (0)
-
-#define SCANNER_SKIP_WHITESPACE() \
- do \
- { \
- do \
- ch = GET (); \
- while (ch != EOF \
- && ((ch) == ' ' || (ch) == '\t')); \
- if (ch != EOF) \
- UNGET (); \
- } while (0)
-
- const char *str = *insn;
- int ch, ch2 = 0;
- enum bpf_token_type ttype = BPF_UNKNOWN;
- size_t len = 0;
- const char *expr = NULL;
- const char *end_expr = NULL;
- int state = 0;
- int return_token = 0;
-
- while (1)
+ if (length > partial_match_length)
{
- ch = GET ();
-
- if (ch == EOF || len > MAX_TOKEN_SZ)
- break;
-
- switch (pseudoc_lex[(unsigned char) ch])
- {
- case LEX_IS_WHITESPACE:
- SCANNER_SKIP_WHITESPACE ();
- return_token = 1;
-
- switch (state)
- {
- case 12: /* >' ' */
- ttype = BPF_JGT;
- break;
-
- case 17: /* ==' ' */
- ttype = BPF_JEQ;
- break;
-
- case 18: /* <' ' */
- ttype = BPF_JLT;
- break;
-
- case 20: /* &' ' */
- ttype = BPF_JSET;
- break;
-
- case 22: /* s<' '*/
- ttype = BPF_JSLT;
- break;
-
- case 14: /* s> ' ' */
- ttype = BPF_JSGT;
- break;
-
- case 16: /* =' ' */
- ttype = BPF_MOV;
- break;
-
- default:
- return_token = 0;
- }
- break;
-
- case LEX_IS_EXCLA:
- token[len++] = ch;
- state = 21;
- break;
-
- case LEX_IS_ARITHM_OP:
- if (state == 16)
- {
- /* ='-' is handle as '=' */
- UNGET ();
- ttype = BPF_MOV;
- return_token = 1;
- break;
- }
-
- START_EXPR();
- token[len++] = ch;
- switch (ch)
- {
-#define BPF_ARITHM_OP(op, type) \
- case (op): \
- state = 6; \
- ttype = (type); \
- break;
-
- BPF_ARITHM_OP('+', BPF_ADD);
- BPF_ARITHM_OP('-', BPF_SUB);
- BPF_ARITHM_OP('*', BPF_MUL);
- BPF_ARITHM_OP('/', BPF_DIV);
- BPF_ARITHM_OP('|', BPF_OR);
- BPF_ARITHM_OP('%', BPF_MOD);
- BPF_ARITHM_OP('^', BPF_XOR);
-
- case '&':
- state = 20; /* '&' */
- break;
-
- case '<':
- switch (state)
- {
- case 0:
- state = 18; /* '<' */
- break;
-
- case 18:
- state = 19; /* <'<' */
- break;
-
- case 8:
- state = 22; /* s'<' */
- break;
- }
- break;
-
- case '>':
- switch (state)
- {
- case 0:
- state = 12; /* '>' */
- break;
-
- case 12:
- state = 13; /* >'>' */
- break;
-
- case 8:
- state = 14; /* s'>' */
- break;
-
- case 14:
- state = 15; /* s>'>' */
- break;
- }
- break;
- }
- break;
-
- case LEX_IS_STAR:
- switch (state)
- {
- case 0:
- token[len++] = ch;
- START_EXPR ();
- state = 2; /* '*', It could be the fist cast char. */
- break;
-
- case 16: /* ='*' Not valid token. */
- ttype = BPF_MOV;
- return_token = 1;
- UNGET ();
- break;
-
- case 4: /* *(uXX'*' */
- token[len++] = ch;
- state = 5;
- break;
- }
- break;
-
- case LEX_IS_OPEN_BR:
- START_EXPR ();
- token[len++] = ch;
- return_token = 1;
-
- switch (state)
- {
- case 2:
- state = 3; /* *'(' second char of a cast or expr. */
- return_token = 0;
- break;
-
- case 6:
- if (valid_expr (expr, &end_expr))
- {
- len = end_expr - expr;
- memcpy (token, expr, len);
- ttype = BPF_EXPR;
- str = end_expr;
- }
- else
- {
- len = 0;
- while (*invalid_expression)
- token[len++] = *invalid_expression++;
-
- token[len] = 0;
- ttype = BPF_UNKNOWN;
- }
- break;
-
- default:
- ttype = BPF_CHR_OPEN_BR;
- SCANNER_SKIP_WHITESPACE ();
- ch2 = GET ();
-
- if ((isdigit (ch2) || ch2 == '(')
- && valid_expr (expr, &end_expr))
- {
- len = end_expr - expr;
- memcpy (token, expr, len);
- ttype = BPF_EXPR;
- str = end_expr;
- }
- else
- UNGET ();
- }
- break;
-
- case LEX_IS_CLSE_BR:
- token[len++] = ch;
-
- if (state == 0)
- {
- ttype = BPF_CHR_CLSE_BR;
- return_token = 1;
- }
- else if (state == 5) /* *(uXX*')' */
- return_token = 1;
- break;
-
- case LEX_IS_EQUAL:
- token[len++] = ch;
- return_token = 1;
-
- switch (state)
- {
- case 0:
- state = 16; /* '=' */
- return_token = 0;
- break;
-
- case 16:
- state = 17; /* ='=' */
- return_token = 0;
- break;
-
- case 2: /* *'=' */
- ttype = BPF_MUL;
- break;
-
- case 10: /* s>>'=' */
- ttype = BPF_ARSH;
- break;
-
- case 12: /* >'=' */
- ttype = BPF_JGE;
- break;
-
- case 13: /* >>'=' */
- ttype = BPF_RSH;
- break;
-
- case 14: /* s>'=' */
- ttype = BPF_JSGE;
- break;
-
- case 15: /* s>>'=' */
- ttype = BPF_ARSH;
- break;
-
- case 18: /* <'=' */
- ttype = BPF_JLE;
- break;
-
- case 19: /* <<'=' */
- ttype = BPF_LSH;
- break;
-
- case 20: /* &'=' */
- ttype = BPF_AND;
- break;
-
- case 21: /* !'=' */
- ttype = BPF_JNE;
- break;
-
- case 22: /* s<'=' */
- ttype = BPF_JSLE;
- break;
- }
- break;
-
- case LEX_IS_SYMBOL_COMPONENT:
- return_token = 1;
-
- switch (state)
- {
- case 17: /* =='sym' */
- ttype = BPF_JEQ;
- break;
-
- case 12: /* >'sym' */
- ttype = BPF_JGT;
- break;
-
- case 18: /* <'sym' */
- ttype = BPF_JLT;
- break;
-
- case 20: /* &'sym' */
- ttype = BPF_JSET;
- break;
-
- case 14: /*s>'sym' */
- ttype = BPF_JSGT;
- break;
-
- case 22: /* s<'sym' */
- ttype = BPF_JSLT;
- break;
-
- case 16: /* ='sym' */
- ttype = BPF_MOV;
- break;
-
- default:
- return_token = 0;
- }
-
- if (return_token)
- {
- UNGET ();
- break;
- }
-
- START_EXPR ();
- token[len++] = ch;
-
- while ((ch2 = GET ()) != EOF)
- {
- int type;
-
- type = pseudoc_lex[(unsigned char) ch2];
- if (type != LEX_IS_SYMBOL_COMPONENT)
- break;
- token[len++] = ch2;
- }
-
- if (ch2 != EOF)
- UNGET ();
-
- if (state == 0)
- {
- if (len == 1 && ch == 's')
- state = 8; /* signed instructions: 's' */
- else
- {
- ttype = BPF_SYMBOL;
- if (is_register (token, len))
- ttype = BPF_REG;
- else if (look_for_reserved_word (token, &ttype))
- ;
- else if ((pseudoc_lex[(unsigned char) *token] == LEX_IS_ARITHM_OP
- || *token == '(' || isdigit(*token))
- && valid_expr (expr, &end_expr))
- {
- len = end_expr - expr;
- token[len] = '\0';
- ttype = BPF_EXPR;
- str = end_expr;
- }
-
- return_token = 1;
- }
- }
- else if (state == 3) /* *('sym' */
- {
- if ((ttype = is_cast (&token[2])) != BPF_UNKNOWN)
- state = 4; /* *('uXX' */
- else
- {
- ttype = BPF_EXPR;
- return_token = 1;
- }
- }
- else if (state == 6)
- {
- if (ttype == BPF_SUB) /* neg */
- {
- if (is_register (&token[1], len - 1))
- ttype = BPF_NEG;
- else if (valid_expr(expr, &end_expr))
- {
- len = end_expr - expr;
- memcpy(token, expr, len);
- ttype = BPF_EXPR;
- str = end_expr;
- }
- else
- {
- len = 0;
- while (*invalid_expression)
- token[len++] = *invalid_expression++;
- token[len] = 0;
- ttype = BPF_UNKNOWN;
- }
- }
- else if (valid_expr (expr, &end_expr))
- {
- len = end_expr - expr;
- memcpy(token, expr, len);
- ttype = BPF_EXPR;
- str = end_expr;
- }
- else
- ttype = BPF_UNKNOWN;
-
- return_token = 1;
- }
- break;
- }
+ va_list args;
- if (return_token)
- {
- *tlen = len;
- *insn = str;
- break;
- }
+ free (errmsg);
+ va_start (args, fmt);
+ errmsg = xvasprintf (fmt, args);
+ va_end (args);
+ partial_match_length = length;
}
-
- return ttype;
-
-#undef GET
-#undef UNGET
-#undef START_EXPR
-#undef SCANNER_SKIP_WHITESPACE
-#undef BPF_ARITHM_OP
}
-/*
- The parser represent a FSM for the grammar described above. So for example
- the following rule:
-
- ` bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32'
-
- Is parser as follows:
-
- 1. It starts in state 0.
+/* Assemble a machine instruction in STR and emit the frags/bytes it
+ assembles to. */
- 2. Consumes next token, e.g: `BPF_REG' and set `state' variable to a
- particular state to helps to identify, in this case, that a register
- token has been read, a comment surrounded by a single quote in the
- pseudo-c token is added along with the new `state' value to indicate
- what the scanner has read, e.g.:
-
- state = 6; // dst_reg = str_cast ( 'src_reg'
-
- So, in `state 6' the scanner has consumed: a destination register
- (BPF_REG), an equal character (BPF_MOV), a cast token (BPF_CAST), an
- open parenthesis (BPF_CHR_OPEN_BR) and the source register (BPF_REG).
-
- 3. If the accumulated tokens represent a complete BPF pseudo-c syntax
- instruction then, a validation of the terms is made, for example: if
- the registers have the same sizes (32/64 bits), if a specific
- destination register must be used, etc., after that, a builder:
- build_bfp_{non_generic_load,atomic_insn,jmp_insn,arithm_insn,endianness,load_store_insn}
- is invoked, internally, it translates the BPF pseudo-c instruction to
- a BPF GAS instruction using the previous terms recollected by the
- scanner.
-
- 4. If a successful build of BPF GAS instruction was done, a final
- state is set to `ST_EOI' (End Of Instruction) meaning that is not
- expecting for more tokens in such instruction. Otherwise if the
- conditions to calling builder are not satisfied an error is emitted
- and `parse_err' is set.
-*/
-
-static char *
-bpf_pseudoc_to_normal_syntax (const char *str, char **errmsg)
+void
+md_assemble (char *str ATTRIBUTE_UNUSED)
{
-#define syntax_err(format, ...) \
- do \
- { \
- if (! parse_err) \
- { \
- parse_err = 1; \
- errbuf = xasprintf (format, ##__VA_ARGS__); \
- } \
- } while (0)
-
- enum bpf_token_type ttype;
- enum bpf_token_type bpf_endianness = BPF_UNKNOWN,
- bpf_atomic_insn;
- enum bpf_token_type bpf_jmp_op = BPF_JEQ; /* Arbitrary. */
- enum bpf_token_type bpf_cast = BPF_CAST_U8; /* Arbitrary. */
- enum bpf_token_type bpf_arithm_op = BPF_ADD; /* Arbitrary. */
- char *bpf_insn = NULL;
- char *errbuf = NULL;
- char src_reg[3] = {0};
- char dst_reg[3] = {0};
- char str_imm32[40] = {0};
- char str_offset[40] = {0};
- char str_symbol[MAX_TOKEN_SZ] = {0};
- char token[MAX_TOKEN_SZ] = {0};
- int state = 0;
- int parse_err = 0;
- size_t tlen;
-
- while (*str)
+ /* There are two different syntaxes that can be used to write BPF
+ instructions. One is very conventional and like any other
+ assembly language where each instruction is conformed by an
+ instruction mnemonic followed by its operands. This is what we
+ call the "normal" syntax. The other syntax tries to look like C
+ statements. We have to support both syntaxes in this assembler.
+
+ One of the many nuisances introduced by this eccentricity is that
+ in the pseudo-c syntax it is not possible to hash the opcodes
+ table by instruction mnemonic, because there is none. So we have
+ no other choice than to try to parse all instruction opcodes
+ until one matches. This is slow.
+
+ Another problem is that emitting detailed diagnostics becomes
+ tricky, since the lack of mnemonic means it is not clear what
+ instruction was intended by the user, and we cannot emit
+ diagnostics for every attempted template. So if an instruction
+ is not parsed, we report the diagnostic corresponding to the
+ partially parsed instruction that was matched further. */
+
+ unsigned int idx = 0;
+ struct bpf_insn insn;
+ const struct bpf_opcode *opcode;
+
+ /* Initialize the global diagnostic variables. See the parse_error
+ function above. */
+ partial_match_length = 0;
+ errmsg = NULL;
+
+#define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__)
+
+ while ((opcode = bpf_get_opcode (idx++)) != NULL)
{
- ttype = get_token (&str, token, &tlen);
- if (ttype == BPF_UNKNOWN || state == ST_EOI)
- {
- syntax_err ("unexpected token: '%s'", token);
- break;
- }
-
- switch (ttype)
- {
- case BPF_UNKNOWN:
- case BPF_LL:
- break;
-
- case BPF_REG:
- switch (state)
- {
- case 0:
- memcpy (dst_reg, token, tlen);
- state = 1; /* 'dst_reg' */
- break;
-
- case 3:
- /* dst_reg bpf_op 'src_reg' */
- memcpy (src_reg, token, tlen);
- if (*dst_reg == *src_reg)
- bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0,
- NULL, bpf_arithm_op);
- else
- {
- syntax_err ("different register sizes: '%s', '%s'",
- dst_reg, src_reg);
- break;
- }
- state = ST_EOI;
- break;
-
- case 5:
- memcpy (src_reg, token, tlen);
- state = 6; /* dst_reg = str_cast ( 'src_reg' */
- break;
-
- case 9:
- memcpy (dst_reg, token, tlen);
- state = 10; /* str_cast ( 'dst_reg' */
- break;
-
- case 11:
- /* str_cast ( dst_reg offset ) = 'src_reg' */
- memcpy (src_reg, token, tlen);
- bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,
- bpf_cast, str_offset, 0);
- state = ST_EOI;
- break;
-
- case 14:
- memcpy (dst_reg, token, tlen);
- state = 15; /* if 'dst_reg' */
- break;
-
- case 16:
- memcpy (src_reg, token, tlen);
- state = 17; /* if dst_reg jmp_op 'src_reg' */
- break;
-
- case 24:
- /* dst_reg = endianness src_reg */
- memcpy (src_reg, token, tlen);
- if (*dst_reg == 'r' && !strcmp (dst_reg, src_reg))
- bpf_insn = build_bpf_endianness (dst_reg, bpf_endianness);
- else
- syntax_err ("invalid operand for instruction: '%s'", token);
-
- state = ST_EOI;
- break;
-
- case 28:
- memcpy (dst_reg, token, tlen);
- state = 29; /* lock str_cast ( 'dst_reg' */
- break;
-
- case 32:
- {
- /* lock str_cast ( dst_reg offset ) atomic_insn 'src_reg' */
- int with_offset = *str_offset != '\0';
-
- memcpy (src_reg, token, tlen);
- if ((bpf_cast != BPF_CAST_U32
- && bpf_cast != BPF_CAST_U64)
- || *dst_reg != 'r'
- || *src_reg != 'r')
- syntax_err ("invalid wide atomic instruction");
- else
- bpf_insn = build_bpf_atomic_insn (dst_reg, src_reg, bpf_atomic_insn,
- bpf_cast, with_offset ? str_offset : str_symbol);
- }
-
- state = ST_EOI;
- break;
-
- case 33:
- /* callx 'dst_reg' */
- bpf_insn = xasprintf ("%s %%%s", "call", token);
- state = ST_EOI;
- break;
-
- case 35:
- memcpy (src_reg, token, tlen);
- state = 36; /* dst_reg = str_cast skb [ 'src_reg' */
- break;
- }
- break;
-
- case BPF_MOV:
- case BPF_ADD:
- case BPF_SUB:
- case BPF_MUL:
- case BPF_DIV:
- case BPF_OR:
- case BPF_AND:
- case BPF_LSH:
- case BPF_RSH:
- case BPF_MOD:
- case BPF_XOR:
- case BPF_ARSH:
- case BPF_NEG:
- switch (state)
- {
- case 1:
- state = 3; /* dst_reg 'arith_op' */
- bpf_arithm_op = ttype;
- break;
-
- case 3:
- if (ttype == BPF_NEG)
- {
- /* reg = -reg */
- bpf_arithm_op = ttype;
- memcpy (src_reg, token + 1, tlen - 1);
- if (strcmp (dst_reg, src_reg))
- {
- syntax_err ("found: '%s', expected: -%s", token, dst_reg);
- break;
- }
-
- bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0,
- NULL, bpf_arithm_op);
- state = ST_EOI;
- }
- break;
-
- case 23:
- memcpy (src_reg, token, tlen);
- state = 11; /* str_cast ( dst_reg offset ) '=' */
- break;
-
- case 12:
- if (ttype == BPF_MOV)
- state = 13; /* str_cast ( dst_reg offset ) '=' */
- break;
-
- case 31:
- bpf_atomic_insn = ttype;
- state = 32; /* lock str_cast ( dst_reg offset ) 'atomic_insn' */
- break;
-
- default:
- syntax_err ("unexpected '%s'", token);
- state = ST_EOI;
- }
- break;
-
- case BPF_CAST_U8:
- case BPF_CAST_U16:
- case BPF_CAST_U32:
- case BPF_CAST_U64:
- bpf_cast = ttype;
- switch (state)
- {
- case 3:
- state = 4; /* dst_reg = 'str_cast' */
- break;
-
- case 0:
- state = 8; /* 'str_cast' */
- break;
-
- case 26:
- state = 27; /* lock 'str_cast' */
- break;
- }
- break;
-
- case BPF_CHR_OPEN_BR:
- switch (state)
- {
- case 4:
- state = 5; /* dst_reg = str_cast '(' */
- break;
-
- case 8:
- state = 9; /* str_cast '(' */
- break;
-
- case 27:
- state = 28; /* lock str_cast '(' */
- break;
-
- case 34:
- state = 35; /* dst_reg = str_cast skb '[' */
- break;
- }
- break;
+ const char *p;
+ char *s;
+ const char *template
+ = (asm_dialect == DIALECT_PSEUDOC ? opcode->pseudoc : opcode->normal);
+
+ /* Do not try to match opcodes with a higher version than the
+ selected ISA spec. */
+ if (opcode->version > isa_spec)
+ continue;
+
+ memset (&insn, 0, sizeof (struct bpf_insn));
+ insn.size = 8;
+ for (s = str, p = template; *p != '\0';)
+ {
+ if (*p == ' ')
+ {
+ /* Expect zero or more spaces. */
+ while (*s != '\0' && (*s == ' ' || *s == '\t'))
+ s += 1;
+ p += 1;
+ }
+ else if (*p == '%')
+ {
+ if (*(p + 1) == '%')
+ {
+ if (*s != '%')
+ {
+ PARSE_ERROR ("expected '%%'");
+ break;
+ }
+ p += 2;
+ s += 1;
+ }
+ else if (*(p + 1) == 'w')
+ {
+ /* Expect zero or more spaces. */
+ while (*s != '\0' && (*s == ' ' || *s == '\t'))
+ s += 1;
+ p += 2;
+ }
+ else if (*(p + 1) == 'W')
+ {
+ /* Expect one or more spaces. */
+ if (*s != ' ' && *s != '\t')
+ {
+ PARSE_ERROR ("expected white space, got '%s'",
+ s);
+ break;
+ }
+ while (*s != '\0' && (*s == ' ' || *s == '\t'))
+ s += 1;
+ p += 2;
+ }
+ else if (strncmp (p, "%dr", 3) == 0)
+ {
+ uint8_t regno;
+ char *news = parse_bpf_register (s, 'r', ®no);
+
+ if (news == NULL || (insn.has_dst && regno != insn.dst))
+ {
+ if (news != NULL)
+ PARSE_ERROR ("expected register r%d, got r%d",
+ insn.dst, regno);
+ else
+ PARSE_ERROR ("expected register name, got '%s'", s);
+ break;
+ }
+ s = news;
+ insn.dst = regno;
+ insn.has_dst = 1;
+ p += 3;
+ }
+ else if (strncmp (p, "%sr", 3) == 0)
+ {
+ uint8_t regno;
+ char *news = parse_bpf_register (s, 'r', ®no);
+
+ if (news == NULL || (insn.has_src && regno != insn.src))
+ {
+ if (news != NULL)
+ PARSE_ERROR ("expected register r%d, got r%d",
+ insn.dst, regno);
+ else
+ PARSE_ERROR ("expected register name, got '%s'", s);
+ break;
+ }
+ s = news;
+ insn.src = regno;
+ insn.has_src = 1;
+ p += 3;
+ }
+ else if (strncmp (p, "%dw", 3) == 0)
+ {
+ uint8_t regno;
+ char *news = parse_bpf_register (s, 'w', ®no);
+
+ if (news == NULL || (insn.has_dst && regno != insn.dst))
+ {
+ if (news != NULL)
+ PARSE_ERROR ("expected register r%d, got r%d",
+ insn.dst, regno);
+ else
+ PARSE_ERROR ("expected register name, got '%s'", s);
+ break;
+ }
+ s = news;
+ insn.dst = regno;
+ insn.has_dst = 1;
+ p += 3;
+ }
+ else if (strncmp (p, "%sw", 3) == 0)
+ {
+ uint8_t regno;
+ char *news = parse_bpf_register (s, 'w', ®no);
+
+ if (news == NULL || (insn.has_src && regno != insn.src))
+ {
+ if (news != NULL)
+ PARSE_ERROR ("expected register r%d, got r%d",
+ insn.dst, regno);
+ else
+ PARSE_ERROR ("expected register name, got '%s'", s);
+ break;
+ }
+ s = news;
+ insn.src = regno;
+ insn.has_src = 1;
+ p += 3;
+ }
+ else if (strncmp (p, "%i32", 4) == 0
+ || strncmp (p, "%I32", 4) == 0)
+ {
+ if (p[1] == 'I')
+ {
+ while (*s == ' ' || *s == '\t')
+ s += 1;
+ if (*s != '+' && *s != '-')
+ {
+ PARSE_ERROR ("expected `+' or `-', got `%c'", *s);
+ break;
+ }
+ }
+
+ s = parse_expression (s, &insn.imm32);
+ if (s == NULL)
+ {
+ PARSE_ERROR ("expected signed 32-bit immediate");
+ break;
+ }
+ insn.has_imm32 = 1;
+ p += 4;
+ }
+ else if (strncmp (p, "%o16", 4) == 0)
+ {
+ while (*s == ' ' || *s == '\t')
+ s += 1;
+ if (*s != '+' && *s != '-')
+ {
+ PARSE_ERROR ("expected `+' or `-', got `%c'", *s);
+ break;
+ }
+
+ s = parse_expression (s, &insn.offset16);
+ if (s == NULL)
+ {
+ PARSE_ERROR ("expected signed 16-bit offset");
+ break;
+ }
+ insn.has_offset16 = 1;
+ p += 4;
+ }
+ else if (strncmp (p, "%d16", 4) == 0)
+ {
+ s = parse_expression (s, &insn.disp16);
+ if (s == NULL)
+ {
+ PARSE_ERROR ("expected signed 16-bit displacement");
+ break;
+ }
+ insn.has_disp16 = 1;
+ p += 4;
+ }
+ else if (strncmp (p, "%d32", 4) == 0)
+ {
+ s = parse_expression (s, &insn.disp32);
+ if (s == NULL)
+ {
+ PARSE_ERROR ("expected signed 32-bit displacement");
+ break;
+ }
+ insn.has_disp32 = 1;
+ p += 4;
+ }
+ else if (strncmp (p, "%i64", 4) == 0)
+ {
+ s = parse_expression (s, &insn.imm64);
+ if (s == NULL)
+ {
+ PARSE_ERROR ("expected signed 64-bit immediate");
+ break;
+ }
+ insn.has_imm64 = 1;
+ insn.size = 16;
+ p += 4;
+ }
+ else
+ as_fatal (_("invalid %%-tag in BPF opcode '%s'\n"), template);
+ }
+ else
+ {
+ /* Match a literal character. */
+ if (*s != *p)
+ {
+ if (*s == '\0')
+ PARSE_ERROR ("expected '%c'", *p);
+ else if (*s == '%')
+ {
+ /* This is to workaround a bug in as_bad. */
+ char tmp[3];
+
+ tmp[0] = '%';
+ tmp[1] = '%';
+ tmp[2] = '\0';
+
+ PARSE_ERROR ("expected '%c', got '%s'", *p, tmp);
+ }
+ else
+ PARSE_ERROR ("expected '%c', got '%c'", *p, *s);
+ break;
+ }
+ p += 1;
+ s += 1;
+ }
+ }
- case BPF_CHR_CLSE_BR:
- switch (state)
- {
- case 7:
- /* dst_reg = str_cast ( imm32 ')' */
- bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,
- bpf_cast, str_imm32, 1);
- state = ST_EOI;
- break;
-
- case 11:
- state = 12; /* str_cast ( dst_reg imm32 ')' */
- break;
-
- case 21:
- /* dst_reg = str_cast ( src_reg offset ')' */
- bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,
- bpf_cast, str_offset, 1);
- state = ST_EOI;
- break;
-
- case 22:
- state = 23; /* str_cast ( dst_reg offset ')' */
- break;
-
- case 30:
- state = 31; /* lock str_cast ( dst_reg offset ')' */
- break;
-
- case 37:
- /* dst_reg = str_cast skb [ src_reg imm32 ']' */
- if (*dst_reg != 'w' && !strcmp ("r0", dst_reg))
- bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL,
- bpf_cast, str_imm32);
- else
- syntax_err ("invalid register operand: '%s'", dst_reg);
-
- state = ST_EOI;
- break;
- }
- break;
+ if (*p == '\0')
+ {
+ /* Allow white spaces at the end of the line. */
+ while (*s != '\0' && (*s == ' ' || *s == '\t'))
+ s += 1;
+ if (*s == '\0')
+ /* We parsed an instruction successfully. */
+ break;
+ PARSE_ERROR ("extra junk at end of line");
+ }
+ }
- case BPF_EXPR:
- switch (state)
- {
- case 3:
- {
- /* dst_reg bpf_arithm_op 'imm32' */
- int load64 = 0;
-
- memcpy (str_imm32, token, tlen);
- memset (token, 0, tlen);
-
- if ((ttype = get_token (&str, token, &tlen)) == BPF_LL
- && bpf_arithm_op == BPF_MOV)
- load64 = 1;
- else if (ttype != BPF_UNKNOWN)
- syntax_err ("unexpected token: '%s'", token);
-
- if (load64 && *dst_reg == 'w')
- syntax_err ("unexpected register size: '%s'", dst_reg);
-
- if (! parse_err)
- bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64,
- str_imm32, bpf_arithm_op);
- state = ST_EOI;
- }
- break;
-
- case 18:
- {
- /* if dst_reg jmp_op src_reg goto 'offset' */
- int with_src = *src_reg != '\0';
-
- memcpy (str_offset, token, tlen);
- if (with_src && *dst_reg != *src_reg)
- syntax_err ("different register size: '%s', '%s'",
- dst_reg, src_reg);
- else
- bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL,
- with_src ? NULL: str_imm32,
- bpf_jmp_op, NULL, str_offset);
- state = ST_EOI;
- }
- break;
-
- case 19:
- /* goto 'offset' */
- memcpy (str_offset, token, tlen);
- bpf_insn = xasprintf ("%s %s", "ja", str_offset);
- state = ST_EOI;
- break;
-
- case 6:
- memcpy (str_offset, token, tlen);
- state = 21; /* dst_reg = str_cast ( src_reg 'offset' */
- break;
-
- case 10:
- memcpy (str_offset, token, tlen);
- state = 22; /* str_cast ( dst_reg 'offset' */
- break;
-
- case 16:
- memcpy (str_imm32, token, tlen);
- state = 25; /* if dst_reg jmp_op 'imm32' */
- break;
-
- case 29:
- memcpy (str_offset, token, tlen);
- state = 30; /* lock str_cast ( dst_reg 'offset' */
- break;
-
- case 34:
- /* dst_reg = str_cast skb 'imm32' */
- if (*dst_reg != 'w' && !strcmp ("r0", dst_reg))
- {
- memcpy (str_imm32, token, tlen);
- bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL,
- bpf_cast, str_imm32);
- }
- else
- syntax_err ("invalid register operand: '%s'", dst_reg);
-
- state = ST_EOI;
- break;
-
- case 36:
- memcpy (str_imm32, token, tlen);
- state = 37; /* dst_reg = str_cast skb [ src_reg 'imm32' */
- break;
- }
- break;
+ if (opcode == NULL)
+ {
+ as_bad (_("unrecognized instruction `%s'"), str);
+ if (errmsg != NULL)
+ {
+ as_bad (errmsg);
+ free (errmsg);
+ }
- case BPF_IF:
- if (state == 0)
- state = 14;
- break;
+ return;
+ }
+ insn.opcode = opcode->opcode;
- case BPF_JSGT:
- case BPF_JSLT:
- case BPF_JSLE:
- case BPF_JSGE:
- case BPF_JGT:
- case BPF_JGE:
- case BPF_JLE:
- case BPF_JSET:
- case BPF_JNE:
- case BPF_JLT:
- case BPF_JEQ:
- if (state == 15)
- {
- bpf_jmp_op = ttype;
- state = 16; /* if dst_reg 'jmp_op' */
- }
- break;
+#undef PARSE_ERROR
- case BPF_GOTO:
- switch (state)
- {
- case 17:
- case 25:
- state = 18; /* if dst_reg jmp_op src_reg|imm32 'goto' */
- break;
-
- case 0:
- state = 19;
- break;
- }
- break;
+ /* Generate the frags and fixups for the parsed instruction. */
+ {
+ char *this_frag = frag_more (insn.size);
+ char bytes[16];
+ uint8_t src, dst;
+ int i;
+
+ /* Zero all the bytes. */
+ memset (bytes, 0, 16);
+
+ /* First encode the opcodes. Note that we have to handle the
+ endianness groups of the BPF instructions: 8 | 4 | 4 | 16 |
+ 32. */
+ if (target_big_endian)
+ {
+ /* code */
+ bytes[0] = (insn.opcode >> 56) & 0xff;
+ /* regs */
+ bytes[1] = (insn.opcode >> 48) & 0xff;
+ /* offset16 */
+ bytes[2] = (insn.opcode >> 40) & 0xff;
+ bytes[3] = (insn.opcode >> 32) & 0xff;
+ /* imm32 */
+ bytes[4] = (insn.opcode >> 24) & 0xff;
+ bytes[5] = (insn.opcode >> 16) & 0xff;
+ bytes[6] = (insn.opcode >> 8) & 0xff;
+ bytes[7] = insn.opcode & 0xff;
+ }
+ else
+ {
+ /* code */
+ bytes[0] = (insn.opcode >> 56) & 0xff;
+ /* regs */
+ bytes[1] = (((((insn.opcode >> 48) & 0xff) & 0xf) << 4)
+ | (((insn.opcode >> 48) & 0xff) & 0xf));
+ /* offset16 */
+ bytes[3] = (insn.opcode >> 40) & 0xff;
+ bytes[2] = (insn.opcode >> 32) & 0xff;
+ /* imm32 */
+ bytes[7] = (insn.opcode >> 24) & 0xff;
+ bytes[6] = (insn.opcode >> 16) & 0xff;
+ bytes[5] = (insn.opcode >> 8) & 0xff;
+ bytes[4] = insn.opcode & 0xff;
+ }
- case BPF_SYMBOL:
- switch (state)
- {
- case 18:
- {
- /* if dst_reg jmp_op src_reg goto 'sym' */
- int with_src = *src_reg != '\0';
-
- memcpy (str_symbol, token, tlen);
- if (with_src && *dst_reg != *src_reg)
- syntax_err ("different register size: '%s', '%s'",
- dst_reg, src_reg);
- else
- bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL,
- with_src ? NULL: str_imm32,
- bpf_jmp_op, str_symbol, NULL);
- state = ST_EOI;
- }
- break;
-
- case 19:
- /* goto 'sym' */
- memcpy (str_symbol, token, tlen);
- bpf_insn = xasprintf ("%s %s", "ja", str_symbol);
- state = ST_EOI;
- break;
-
- case 0:
- state = ST_EOI;
- break;
-
- case 3:
- {
- /* dst_reg arithm_op 'sym' */
- int load64 = 0;
-
- memcpy (str_symbol, token, tlen);
- memset (token, 0, tlen);
-
- if ((ttype = get_token (&str, token, &tlen)) == BPF_LL
- && bpf_arithm_op == BPF_MOV)
- load64 = 1;
- else if (ttype != BPF_UNKNOWN)
- syntax_err ("unexpected token: '%s'", token);
-
- if (load64 && *dst_reg == 'w')
- syntax_err ("unexpected register size: '%s'", dst_reg);
-
- if (! parse_err)
- bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64,
- str_symbol, bpf_arithm_op);
- state = ST_EOI;
- }
- break;
- }
- break;
+ /* Now the registers. */
+ src = insn.has_src ? insn.src : 0;
+ dst = insn.has_dst ? insn.dst : 0;
- case BPF_LE16:
- case BPF_LE32:
- case BPF_LE64:
- case BPF_BE16:
- case BPF_BE32:
- case BPF_BE64:
- bpf_endianness = ttype;
- state = 24; /* dst_reg = 'endianness' */
- break;
+ if (target_big_endian)
+ bytes[1] = ((dst & 0xf) << 4) | (src & 0xf);
+ else
+ bytes[1] = ((src & 0xf) << 4) | (dst & 0xf);
- case BPF_LOCK:
- state = 26;
- break;
+ /* Now the immediates. */
+ if (insn.has_imm64)
+ {
+ switch (insn.imm64.X_op)
+ {
+ case O_constant:
+ {
+ uint64_t imm64 = insn.imm64.X_add_number;
+
+ if (target_big_endian)
+ {
+ bytes[12] = (imm64 >> 56) & 0xff;
+ bytes[13] = (imm64 >> 48) & 0xff;
+ bytes[14] = (imm64 >> 40) & 0xff;
+ bytes[15] = (imm64 >> 32) & 0xff;
+ bytes[4] = (imm64 >> 24) & 0xff;
+ bytes[5] = (imm64 >> 16) & 0xff;
+ bytes[6] = (imm64 >> 8) & 0xff;
+ bytes[7] = imm64 & 0xff;
+ }
+ else
+ {
+ bytes[15] = (imm64 >> 56) & 0xff;
+ bytes[14] = (imm64 >> 48) & 0xff;
+ bytes[13] = (imm64 >> 40) & 0xff;
+ bytes[12] = (imm64 >> 32) & 0xff;
+ bytes[7] = (imm64 >> 24) & 0xff;
+ bytes[6] = (imm64 >> 16) & 0xff;
+ bytes[5] = (imm64 >> 8) & 0xff;
+ bytes[4] = imm64 & 0xff;
+ }
+ break;
+ }
+ case O_symbol:
+ case O_subtract:
+ case O_add:
+ {
+ reloc_howto_type *reloc_howto;
+ int size;
+
+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_64);
+ if (!reloc_howto)
+ abort ();
+
+ size = bfd_get_reloc_size (reloc_howto);
+
+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+ size, &insn.imm64, reloc_howto->pc_relative,
+ BFD_RELOC_BPF_64);
+ break;
+ }
+ default:
+ abort ();
+ }
+ }
- case BPF_IND_CALL:
- state = 33;
- break;
+ if (insn.has_imm32)
+ {
+ switch (insn.imm32.X_op)
+ {
+ case O_constant:
+ {
+ uint32_t imm32 = insn.imm32.X_add_number;
+
+ if (target_big_endian)
+ {
+ bytes[4] = (imm32 >> 24) & 0xff;
+ bytes[5] = (imm32 >> 16) & 0xff;
+ bytes[6] = (imm32 >> 8) & 0xff;
+ bytes[7] = imm32 & 0xff;
+ }
+ else
+ {
+ bytes[7] = (imm32 >> 24) & 0xff;
+ bytes[6] = (imm32 >> 16) & 0xff;
+ bytes[5] = (imm32 >> 8) & 0xff;
+ bytes[4] = imm32 & 0xff;
+ }
+ break;
+ }
+ case O_symbol:
+ case O_subtract:
+ case O_add:
+ case O_uminus:
+ {
+ reloc_howto_type *reloc_howto;
+ int size;
+
+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
+ if (!reloc_howto)
+ abort ();
+
+ size = bfd_get_reloc_size (reloc_howto);
+
+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal + 4,
+ size, &insn.imm32, reloc_howto->pc_relative,
+ BFD_RELOC_32);
+ break;
+ }
+ default:
+ abort ();
+ }
+ }
- case BPF_LD:
- state = 34; /* dst_reg = str_cast 'skb' */
- break;
- }
+ if (insn.has_disp32)
+ {
+ switch (insn.disp32.X_op)
+ {
+ case O_constant:
+ {
+ uint32_t disp32 = insn.disp32.X_add_number;
+
+ if (target_big_endian)
+ {
+ bytes[4] = (disp32 >> 24) & 0xff;
+ bytes[5] = (disp32 >> 16) & 0xff;
+ bytes[6] = (disp32 >> 8) & 0xff;
+ bytes[7] = disp32 & 0xff;
+ }
+ else
+ {
+ bytes[7] = (disp32 >> 24) & 0xff;
+ bytes[6] = (disp32 >> 16) & 0xff;
+ bytes[5] = (disp32 >> 8) & 0xff;
+ bytes[4] = disp32 & 0xff;
+ }
+ break;
+ }
+ case O_symbol:
+ case O_subtract:
+ case O_add:
+ {
+ reloc_howto_type *reloc_howto;
+ int size;
+
+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP32);
+ if (!reloc_howto)
+ abort ();
+
+ size = bfd_get_reloc_size (reloc_howto);
+
+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+ size, &insn.disp32, reloc_howto->pc_relative,
+ BFD_RELOC_BPF_DISP32);
+ break;
+ }
+ default:
+ abort ();
+ }
+ }
- memset (token, 0, tlen);
- }
+ if (insn.has_offset16)
+ {
+ switch (insn.offset16.X_op)
+ {
+ case O_constant:
+ {
+ uint32_t offset16 = insn.offset16.X_add_number;
+
+ if (target_big_endian)
+ {
+ bytes[2] = (offset16 >> 8) & 0xff;
+ bytes[3] = offset16 & 0xff;
+ }
+ else
+ {
+ bytes[3] = (offset16 >> 8) & 0xff;
+ bytes[2] = offset16 & 0xff;
+ }
+ break;
+ }
+ case O_symbol:
+ case O_subtract:
+ case O_add:
+ {
+ reloc_howto_type *reloc_howto;
+ int size;
+
+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16);
+ if (!reloc_howto)
+ abort ();
+
+ size = bfd_get_reloc_size (reloc_howto);
+
+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+ size, &insn.offset16, reloc_howto->pc_relative,
+ BFD_RELOC_BPF_DISP16);
+ break;
+ }
+ default:
+ abort ();
+ }
+ }
- if (state != ST_EOI)
- syntax_err ("incomplete instruction");
+ if (insn.has_disp16)
+ {
+ switch (insn.disp16.X_op)
+ {
+ case O_constant:
+ {
+ uint32_t disp16 = insn.disp16.X_add_number;
+
+ if (target_big_endian)
+ {
+ bytes[2] = (disp16 >> 8) & 0xff;
+ bytes[3] = disp16 & 0xff;
+ }
+ else
+ {
+ bytes[3] = (disp16 >> 8) & 0xff;
+ bytes[2] = disp16 & 0xff;
+ }
+ break;
+ }
+ case O_symbol:
+ case O_subtract:
+ case O_add:
+ {
+ reloc_howto_type *reloc_howto;
+ int size;
+
+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16);
+ if (!reloc_howto)
+ abort ();
+
+ size = bfd_get_reloc_size (reloc_howto);
+
+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+ size, &insn.disp16, reloc_howto->pc_relative,
+ BFD_RELOC_BPF_DISP16);
+ break;
+ }
+ default:
+ abort ();
+ }
+ }
- *errmsg = errbuf;
- return bpf_insn;
+ /* Emit bytes. */
+ for (i = 0; i < insn.size; ++i)
+ {
+ md_number_to_chars (this_frag, (valueT) bytes[i], 1);
+ this_frag += 1;
+ }
+ }
-#undef syntax_err
+ /* Emit DWARF2 debugging information. */
+ dwarf2_emit_insn (insn.size);
}
-void
-md_assemble (char *str)
-{
- const CGEN_INSN *insn;
- char *errmsg;
- char *a_errmsg;
- CGEN_FIELDS fields;
- char *normal;
-
-#if CGEN_INT_INSN_P
- CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)];
-#else
- unsigned char buffer[CGEN_MAX_INSN_SIZE];
-#endif
-
- gas_cgen_init_parse ();
- insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields,
- buffer, &errmsg);
- if (insn == NULL)
- {
- normal = bpf_pseudoc_to_normal_syntax (str, &a_errmsg);
- if (normal)
- {
- insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, normal, &fields,
- buffer, &a_errmsg);
- xfree (normal);
- }
-
- if (insn == NULL)
- {
- as_bad ("%s", errmsg);
- if (a_errmsg)
- {
- as_bad ("%s", a_errmsg);
- xfree (a_errmsg);
- }
- return;
- }
- }
-
- gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields),
- 0, /* zero to ban relaxable insns. */
- NULL); /* NULL so results not returned here. */
-}
+/* Parse an operand that is machine-specific. */
void
md_operand (expressionS *expressionP)
{
- invalid_expression = input_line_pointer - 1;
- gas_cgen_md_operand (expressionP);
+ /* If this hook is invoked it means GAS failed to parse a generic
+ expression. We should inhibit the as_bad in expr.c, so we can fail
+ while parsing instruction alternatives. To do that, we change the
+ expression to not have an O_absent. But then we also need to set
+ exp_parse_failed to parse_expression above does the right thing. */
+ ++input_line_pointer;
+ expressionP->X_op = O_constant;
+ expressionP->X_add_number = 0;
+ exp_parse_failed = 1;
}
-
symbolS *
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
{
{
return ieee_md_atof (type, litP, sizeP, false);
}
+
+\f
+/* Determine whether the equal sign in the given string corresponds to
+ a BPF instruction, i.e. when it is not to be considered a symbol
+ assignment. */
+
+bool
+bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char *str ATTRIBUTE_UNUSED)
+{
+ uint8_t regno;
+
+ /* Only pseudo-c instructions can have equal signs, and of these,
+ all that could be confused with a symbol assignment all start
+ with a register name. */
+ if (asm_dialect == DIALECT_PSEUDOC)
+ {
+ char *w = parse_bpf_register (str, 'w', ®no);
+ char *r = parse_bpf_register (str, 'r', ®no);
+
+ if ((w != NULL && *w == '\0')
+ || (r != NULL && *r == '\0'))
+ return 1;
+ }
+
+ return 0;
+}
/* .-foo gets turned into PC relative relocs. */
#define DIFF_EXPR_OK 1
-#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
a jump to offset 0 means jump to the next instruction. */
#define md_single_noop_insn "ja 0"
-#define TC_EQUAL_IN_INSN(c, s) 1
+#define TC_EQUAL_IN_INSN(c, s) bpf_tc_equal_in_insn ((c), (s))
+extern bool bpf_tc_equal_in_insn (int, char *);
_ACEOF
fi
- using_cgen=yes
;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
- using_cgen=yes
;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
@cindex BPF support
@menu
-* BPF Options:: Options
-* BPF Syntax:: Syntax
-* BPF Directives:: Machine Directives
-* BPF Opcodes:: Opcodes
-* BPF Pseudo-C Syntax:: Alternative Pseudo-C Assembly Syntax
+* BPF Options:: BPF specific command-line options.
+* BPF Special Characters:: Comments and statements.
+* BPF Registers:: Register names.
+* BPF Directives:: Machine directives.
+* BPF Instructions:: Machine instructions.
@end menu
@node BPF Options
-@section Options
+@section BPF Options
@cindex BPF options (none)
@cindex options for BPF (none)
@item -EL
This option specifies that the assembler should emit little-endian
eBPF.
+
+@cindex @option{-mdialect} command-line options, BPF
+@item -mdialect=@var{dialect}
+This option specifies the assembly language dialect to recognize while
+assembling. The assembler supports @option{normal} and
+@option{pseudoc}.
+
+@cindex @option{-misa-spec} command-line options, BPF
+@item -misa-spec=@var{spec}
+This option specifies the version of the BPF instruction set to use
+when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}.
+
+The value @option{xbpf} can be specified to recognize extra
+instructions that are used by GCC for testing purposes. But beware
+this is not valid BPF.
@end table
Note that if no endianness option is specified in the command line,
the host endianness is used.
@c man end
-@node BPF Syntax
-@section Syntax
-@menu
-* BPF-Chars:: Special Characters
-* BPF-Regs:: Register Names
-* BPF-Pseudo-Maps:: Pseudo map fds
-@end menu
-
-@node BPF-Chars
-@subsection Special Characters
+@node BPF Special Characters
+@section BPF Special Characters
@cindex line comment character, BPF
@cindex BPF line comment character
@cindex statement separator, BPF
Statements and assembly directives are separated by newlines.
-@node BPF-Regs
-@subsection Register Names
+@node BPF Registers
+@section BPF Registers
@cindex BPF register names
@cindex register names, BPF
The eBPF processor provides ten general-purpose 64-bit registers,
which are read-write, and a read-only frame pointer register:
+@noindent
+In normal syntax:
+
@table @samp
@item %r0 .. %r9
General-purpose registers.
@item %r10
-Frame pointer register.
+@itemx %fp
+Read-only frame pointer register.
@end table
-Some registers have additional names, to reflect their role in the
-eBPF ABI:
+All BPF registers are 64-bit long. However, in the Pseudo-C syntax
+registers can be referred using different names, which actually
+reflect the kind of instruction they appear on:
+
+@noindent
+In pseudoc syntax:
@table @samp
-@item %a
-This is @samp{%r0}.
-@item %ctx
-This is @samp{%r6}.
-@item %fp
-This is @samp{%r10}.
+@item r0..r9
+General-purpose register in an instruction that operates on its value
+as if it was a 64-bit value.
+@item w0..w9
+General-purpose register in an instruction that operates on its value
+as if it was a 32-bit value.
+@item r10
+Read-only frame pointer register.
@end table
-@node BPF-Pseudo-Maps
-@subsection Pseudo Maps
-
-@cindex pseudo map fd, BPF
-The @samp{LDDW} instruction can take a literal pseudo map file
-descriptor as its second argument. This uses the syntax
-@samp{%map_fd(N)} where @samp{N} is a signed number.
-
-For example, to load the address of the pseudo map with file
-descriptor @samp{2} in register @samp{r1} we would do:
-
-@smallexample
- lddw %r1, %map_fd(2)
-@end smallexample
+@noindent
+Note that in the Pseudo-C syntax register names are not preceded by
+@code{%} characters.
@node BPF Directives
-@section Machine Directives
+@section BPF Directives
@cindex machine directives, BPF
The @code{.dword} directive produces a 64 bit value.
@end table
-@node BPF Opcodes
-@section Opcodes
+@node BPF Instructions
+@section BPF Instructions
@cindex BPF opcodes
@cindex opcodes for BPF
are used:
@table @code
-@item %d
-Destination general-purpose register whose role is to be destination
-of an operation.
-@item %s
+@item rd
+Destination general-purpose register whose role is to be the
+destination of an operation.
+@item rs
Source general-purpose register whose role is to be the source of an
operation.
@item disp16
32-bit signed PC-relative offset, measured in number of 64-bit words,
minus one.
@item offset16
-Signed 16-bit immediate.
+Signed 16-bit immediate representing an offset in bytes.
+@item disp16
+Signed 16-bit immediate representing a displacement to a target,
+measured in number of 64-bit words @emph{minus one}.
@item imm32
Signed 32-bit immediate.
@item imm64
Signed 64-bit immediate.
@end table
-@subsubsection Arithmetic instructions
+@subsection Arithmetic instructions
The destination register in these instructions act like an
accumulator.
+Note that in pseudoc syntax these instructions should use @code{r}
+registers.
+
@table @code
-@item add %d, (%s|imm32)
+@item add rd, rs
+@itemx add rd, imm32
+@itemx rd += rs
+@itemx rd += imm32
64-bit arithmetic addition.
-@item sub %d, (%s|imm32)
+
+@item sub rd, rs
+@itemx sub rd, rs
+@itemx rd -= rs
+@itemx rd -= imm32
64-bit arithmetic subtraction.
-@item mul %d, (%s|imm32)
+
+@item mul rd, rs
+@itemx mul rd, imm32
+@itemx rd *= rs
+@itemx rd *= imm32
64-bit arithmetic multiplication.
-@item div %d, (%s|imm32)
+
+@item div rd, rs
+@itemx div rd, imm32
+@itemx rd /= rs
+@itemx rd /= imm32
64-bit arithmetic integer division.
-@item mod %d, (%s|imm32)
+
+@item mod rd, rs
+@itemx mod rd, imm32
+@itemx rd %= rs
+@itemx rd %= imm32
64-bit integer remainder.
-@item and %d, (%s|imm32)
+
+@item and rd, rs
+@itemx and rd, imm32
+@itemx rd &= rs
+@itemx rd &= imm32
64-bit bit-wise ``and'' operation.
-@item or %d, (%s|imm32)
+
+@item or rd, rs
+@itemx or rd, imm32
+@itemx rd |= rs
+@itemx rd |= imm32
64-bit bit-wise ``or'' operation.
-@item xor %d, (%s|imm32)
+
+@item xor rd, imm32
+@itemx xor rd, rs
+@itemx rd ^= rs
+@itemx rd ^= imm32
64-bit bit-wise exclusive-or operation.
-@item lsh %d, (%s|imm32)
-64-bit left shift, by @code{%s} or @code{imm32} bits.
-@item rsh %d, (%s|imm32)
-64-bit right logical shift, by @code{%s} or @code{imm32} bits.
-@item arsh %d, (%s|imm32)
-64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
-@item neg %d
+
+@item lsh rd, rs
+@itemx ldh rd, imm32
+@itemx rd <<= rs
+@itemx rd <<= imm32
+64-bit left shift, by @code{rs} or @code{imm32} bits.
+
+@item rsh %d, %s
+@itemx rsh rd, imm32
+@itemx rd >>= rs
+@itemx rd >>= imm32
+64-bit right logical shift, by @code{rs} or @code{imm32} bits.
+
+@item arsh rd, rs
+@itemx arsh rd, imm32
+@itemx rd s>>= rs
+@itemx rd s>>= imm32
+64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
+
+@item neg rd, rs
+@itemx neg rd, imm32
+@itemx rd = - rs
+@itemx rd = - imm32
64-bit arithmetic negation.
-@item mov %d, (%s|imm32)
-Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32}
-in @code{%d}.
+
+Note that in the @code{rd = - imm32} syntax there must be at least
+one white space between @code{-} and @code{imm32}. Otherwise the
+instruction is parsed as a @code{mov rd, imm32} instruction with a
+negative 32-bit immediate. This is a consequence of a syntactic
+ambiguity in the pseudoc syntax.
+
+@item mov rd, rs
+@itemx mov rd, imm32
+@itemx rd = rs
+@itemx rd = imm32
+Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}
+in @code{rd}.
@end table
-@subsubsection 32-bit arithmetic instructions
+@subsection 32-bit arithmetic instructions
The destination register in these instructions act as an accumulator.
+Note that in pseudoc syntax these instructions should use @code{w}
+registers. It is not allowed to mix @code{w} and @code{r} registers
+in the same instruction.
+
@table @code
-@item add32 %d, (%s|imm32)
+@item add32 rd, rs
+@itemx add32 rd, imm32
+@itemx rd += rs
+@itemx rd += imm32
32-bit arithmetic addition.
-@item sub32 %d, (%s|imm32)
+
+@item sub32 rd, rs
+@itemx sub32 rd, imm32
+@itemx rd -= rs
+@itemx rd += imm32
32-bit arithmetic subtraction.
-@item mul32 %d, (%s|imm32)
+
+@item mul32 rd, rs
+@itemx mul32 rd, imm32
+@itemx rd *= rs
+@itemx rd *= imm32
32-bit arithmetic multiplication.
-@item div32 %d, (%s|imm32)
+
+@item div32 rd, rs
+@itemx div32 rd, imm32
+@itemx rd /= rs
+@itemx rd /= imm32
32-bit arithmetic integer division.
-@item mod32 %d, (%s|imm32)
+
+@item mod32 rd, rs
+@itemx mod32 rd, imm32
+@itemx rd %= rs
+@itemx rd %= imm32
32-bit integer remainder.
-@item and32 %d, (%s|imm32)
+
+@item and32 rd, rs
+@itemx and32 rd, imm32
+@itemx rd &= rs
+@itemx rd &= imm32
32-bit bit-wise ``and'' operation.
-@item or32 %d, (%s|imm32)
+
+@item or32 rd, rs
+@itemx or32 rd, imm32
+@itemx rd |= rs
+@itemx rd |= imm32
32-bit bit-wise ``or'' operation.
-@item xor32 %d, (%s|imm32)
+
+@item xor32 rd, rs
+@itemx xor32 rd, imm32
+@itemx rd ^= rs
+@itemx rd ^= imm32
32-bit bit-wise exclusive-or operation.
-@item lsh32 %d, (%s|imm32)
-32-bit left shift, by @code{%s} or @code{imm32} bits.
-@item rsh32 %d, (%s|imm32)
-32-bit right logical shift, by @code{%s} or @code{imm32} bits.
-@item arsh32 %d, (%s|imm32)
-32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
-@item neg32 %d
+
+@item lsh32 rd, rs
+@itemx lsh32 rd, imm32
+@itemx rd <<= rs
+@itemx rd <<= imm32
+32-bit left shift, by @code{rs} or @code{imm32} bits.
+
+@item rsh32 rd, rs
+@itemx rsh32 rd, imm32
+@itemx rd >>= rs
+@itemx rd >>= imm32
+32-bit right logical shift, by @code{rs} or @code{imm32} bits.
+
+@item arsh32 rd, rs
+@itemx arsh32 rd, imm32
+@itemx rd s>>= rs
+@itemx rd s>>= imm32
+32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
+
+@item neg32 rd, rs
+@itemx neg32 rd, imm32
+@itemx rd = - rs
+@itemx rd = - imm32
32-bit arithmetic negation.
-@item mov32 %d, (%s|imm32)
-Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32}
-in @code{%d}.
+
+Note that in the @code{rd = - imm32} syntax there must be at least
+one white space between @code{-} and @code{imm32}. Otherwise the
+instruction is parsed as a @code{mov32 rd, imm32} instruction with a
+negative 32-bit immediate. This is a consequence of a syntactic
+ambiguity in the pseudoc syntax.
+
+@item mov32 rd, rs
+@itemx mov32 rd, imm32
+@itemx rd = rs
+@itemx rd = imm32
+Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}
+in @code{rd}.
@end table
-@subsubsection Endianness conversion instructions
+@subsection Endianness conversion instructions
@table @code
-@item endle %d, (16|32|64)
-Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to
-little-endian.
-@item endbe %d, (16|32|64)
-Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to big-endian.
+@item endle rd, 16
+@itemx endle rd, 32
+@itemx endle rd, 64
+@itemx rd = le16 rd
+@itemx rd = le32 rd
+@itemx rd = le64 rd
+Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to
+little-endian and store it back in @code{rd}.
+@item endbe %d, 16
+@itemx endbe %d, 32
+@itemx endbe %d, 64
+@itemx rd = be16 rd
+@itemx rd = be32 rd
+@itemx rd = be64 rd
+Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
+and store it back in @code{rd}.
@end table
-@subsubsection 64-bit load and pseudo maps
+@subsection 64-bit load and pseudo maps
@table @code
-@item lddw %d, imm64
-Load the given signed 64-bit immediate, or pseudo map descriptor, to
-the destination register @code{%d}.
-@item lddw %d, %map_fd(N)
-Load the address of the given pseudo map fd @emph{N} to the
-destination register @code{%d}.
+@item lddw rd, imm64
+@itemx rd = imm64 ll
+Load the given signed 64-bit immediate to the destination register
+@code{rd}.
@end table
-@subsubsection Load instructions for socket filters
+@subsection Load instructions for socket filters
The following instructions are intended to be used in socket filters,
and are therefore not general-purpose: they make assumptions on the
@table @code
@item ldabsdw imm32
+@itemx r0 = *(u64 *) skb[imm32]
Absolute 64-bit load.
+
@item ldabsw imm32
+@itemx r0 = *(u32 *) skb[imm32]
Absolute 32-bit load.
+
@item ldabsh imm32
+@itemx r0 = *(u16 *) skb[imm32]
Absolute 16-bit load.
+
@item ldabsb imm32
+@itemx r0 = *(u8 *) skb[imm32]
Absolute 8-bit load.
@end table
Indirect loads:
@table @code
-@item ldinddw %s, imm32
+@item ldinddw rs, imm32
+@itemx r0 = *(u64 *) skb[rs + imm32]
Indirect 64-bit load.
-@item ldindw %s, imm32
+
+@item ldindw rs, imm32
+@itemx r0 = *(u32 *) skb[rs + imm32]
Indirect 32-bit load.
-@item ldindh %s, imm32
+
+@item ldindh rs, imm32
+@itemx r0 = *(u16 *) skb[rs + imm32]
Indirect 16-bit load.
+
@item ldindb %s, imm32
+@itemx r0 = *(u8 *) skb[rs + imm32]
Indirect 8-bit load.
@end table
-@subsubsection Generic load/store instructions
+@subsection Generic load/store instructions
General-purpose load and store instructions are provided for several
word sizes.
Load to register instructions:
@table @code
-@item ldxdw %d, [%s+offset16]
+@item ldxdw rd, [rs + offset16]
+@itemx rd = *(u64 *) (rs + offset16)
Generic 64-bit load.
-@item ldxw %d, [%s+offset16]
+
+@item ldxw rd, [rs + offset16]
+@itemx rd = *(u32 *) (rs + offset16)
Generic 32-bit load.
-@item ldxh %d, [%s+offset16]
+
+@item ldxh rd, [rs + offset16]
+@itemx rd = *(u16 *) (rs + offset16)
Generic 16-bit load.
-@item ldxb %d, [%s+offset16]
+
+@item ldxb rd, [rs + offset16]
+@itemx rd = *(u8 *) (rs + offset16)
Generic 8-bit load.
@end table
Store from register instructions:
@table @code
-@item stxdw [%d+offset16], %s
+@item stxdw [rd + offset16], %s
+@itemx *(u64 *) (rd + offset16)
Generic 64-bit store.
-@item stxw [%d+offset16], %s
+
+@item stxw [rd + offset16], %s
+@itemx *(u32 *) (rd + offset16)
Generic 32-bit store.
-@item stxh [%d+offset16], %s
+
+@item stxh [rd + offset16], %s
+@itemx *(u16 *) (rd + offset16)
Generic 16-bit store.
-@item stxb [%d+offset16], %s
+
+@item stxb [rd + offset16], %s
+@itemx *(u8 *) (rd + offset16)
Generic 8-bit store.
@end table
Store from immediates instructions:
@table @code
-@item stddw [%d+offset16], imm32
+@item stdw [rd + offset16], imm32
+@itemx *(u64 *) (rd + offset16) = imm32
Store immediate as 64-bit.
-@item stdw [%d+offset16], imm32
+
+@item stw [rd + offset16], imm32
+@itemx *(u32 *) (rd + offset16) = imm32
Store immediate as 32-bit.
-@item stdh [%d+offset16], imm32
+
+@item sth [rd + offset16], imm32
+@itemx *(u16 *) (rd + offset16) = imm32
Store immediate as 16-bit.
-@item stdb [%d+offset16], imm32
+
+@item stb [rd + offset16], imm32
+@itemx *(u8 *) (rd + offset16) = imm32
Store immediate as 8-bit.
@end table
-@subsubsection Jump instructions
+@subsection Jump instructions
eBPF provides the following compare-and-jump instructions, which
compare the values of the two given registers, or the values of a
holds true.
@table @code
-@item ja %d,(%s|imm32),disp16
+@item ja disp16
+@itemx goto disp16
Jump-always.
-@item jeq %d,(%s|imm32),disp16
+
+@item jeq rd, rs, disp16
+@itemx jeq rd, imm32, disp16
+@itemx if rd == rs goto disp16
+@itemx if rd == imm32 goto disp16
Jump if equal, unsigned.
-@item jgt %d,(%s|imm32),disp16
+
+@item jgt rd, rs, disp16
+@itemx jgt rd, imm32, disp16
+@itemx if rd > rs goto disp16
+@itemx if rd > imm32 goto disp16
Jump if greater, unsigned.
-@item jge %d,(%s|imm32),disp16
+
+@item jge rd, rs, disp16
+@itemx jge rd, imm32, disp16
+@itemx if rd >= rs goto disp16
+@itemx if rd >= imm32 goto disp16
Jump if greater or equal.
-@item jlt %d,(%s|imm32),disp16
+
+@item jlt rd, rs, disp16
+@itemx jlt rd, imm32, disp16
+@itemx if rd < rs goto disp16
+@itemx if rd < imm32 goto disp16
Jump if lesser.
-@item jle %d,(%s|imm32),disp16
+
+@item jle rd , rs, disp16
+@itemx jle rd, imm32, disp16
+@itemx if rd <= rs goto disp16
+@itemx if rd <= imm32 goto disp16
Jump if lesser or equal.
-@item jset %d,(%s|imm32),disp16
+
+@item jset rd, rs, disp16
+@itemx jset rd, imm32, disp16
+@itemx if rd & rs goto disp16
+@itemx if rd & imm32 goto disp16
Jump if signed equal.
-@item jne %d,(%s|imm32),disp16
+
+@item jne rd, rs, disp16
+@itemx jne rd, imm32, disp16
+@itemx if rd != rs goto disp16
+@itemx if rd != imm32 goto disp16
Jump if not equal.
-@item jsgt %d,(%s|imm32),disp16
+
+@item jsgt rd, rs, disp16
+@itemx jsgt rd, imm32, disp16
+@itemx if rd s> rs goto disp16
+@itemx if rd s> imm32 goto disp16
Jump if signed greater.
-@item jsge %d,(%s|imm32),disp16
+
+@item jsge rd, rs, disp16
+@itemx jsge rd, imm32, disp16
+@itemx if rd s>= rd goto disp16
+@itemx if rd s>= imm32 goto disp16
Jump if signed greater or equal.
-@item jslt %d,(%s|imm32),disp16
+
+@item jslt rd, rs, disp16
+@itemx jslt rd, imm32, disp16
+@itemx if rd s< rs goto disp16
+@itemx if rd s< imm32 goto disp16
Jump if signed lesser.
-@item jsle %d,(%s|imm32),disp16
+
+@item jsle rd, rs, disp16
+@itemx jsle rd, imm32, disp16
+@itemx if rd s<= rs goto disp16
+@itemx if rd s<= imm32 goto disp16
Jump if signed lesser or equal.
@end table
functions, or to external kernel helpers:
@table @code
-@item call (disp32|imm32)
+@item call disp32
+@item call imm32
Jump and link to the offset @emph{disp32}, or to the kernel helper
function identified by @emph{imm32}.
@end table
Terminate the eBPF program.
@end table
-@subsubsection Atomic instructions
+@subsection 32-bit jump instructions
-Atomic exchange-and-add instructions are provided in two flavors: one
-for swapping 64-bit quantities and another for 32-bit quantities.
+eBPF provides the following compare-and-jump instructions, which
+compare the 32-bit values of the two given registers, or the values of
+a register and an immediate, and perform a branch in case the
+comparison holds true.
-@table @code
-@item xadddw [%d+offset16],%s
-Exchange-and-add a 64-bit value at the specified location.
-@item xaddw [%d+offset16],%s
-Exchange-and-add a 32-bit value at the specified location.
-@end table
+These instructions are only available in BPF v3 or later.
-@node BPF Pseudo-C Syntax
-@section BPF Pseudo-C Syntax
+@table @code
+@item jeq32 rd, rs, disp16
+@itemx jeq32 rd, imm32, disp16
+@itemx if rd == rs goto disp16
+@itemx if rd == imm32 goto disp16
+Jump if equal, unsigned.
-This assembler supports another syntax to denote BPF instructions,
-which is an alternative to the normal looking syntax documented above.
-This alternatative syntax, which we call @dfn{pseudo-C syntax}, is
-supported by the LLVM/clang integrated assembler.
+@item jgt32 rd, rs, disp16
+@itemx jgt32 rd, imm32, disp16
+@itemx if rd > rs goto disp16
+@itemx if rd > imm32 goto disp16
+Jump if greater, unsigned.
-This syntax is very unconventional, but we need to support it in order
-to support inline assembly in existing BPF programs.
+@item jge32 rd, rs, disp16
+@itemx jge32 rd, imm32, disp16
+@itemx if rd >= rs goto disp16
+@itemx if rd >= imm32 goto disp16
+Jump if greater or equal.
-Note that the assembler is able to parse sources in which both
-syntaxes coexist: some instructions can use the usual assembly like
-syntax, whereas some other instructions in the same file can use the
-pseudo-C syntax.
+@item jlt32 rd, rs, disp16
+@itemx jlt32 rd, imm32, disp16
+@itemx if rd < rs goto disp16
+@itemx if rd < imm32 goto disp16
+Jump if lesser.
-@subsubsection Pseudo-C Register Names
+@item jle32 rd , rs, disp16
+@itemx jle32 rd, imm32, disp16
+@itemx if rd <= rs goto disp16
+@itemx if rd <= imm32 goto disp16
+Jump if lesser or equal.
-All BPF registers are 64-bit long. However, in the Pseudo-C syntax
-registers can be referred using different names, which actually
-reflect the kind of instruction they appear on:
+@item jset32 rd, rs, disp16
+@itemx jset32 rd, imm32, disp16
+@itemx if rd & rs goto disp16
+@itemx if rd & imm32 goto disp16
+Jump if signed equal.
-@table @samp
-@item r0..r9
-General-purpose register in an instruction that operates on its value
-as if it was a 64-bit value.
-@item w0..w9
-General-purpose register in an instruction that operates on its value
-as if it was a 32-bit value.
-@end table
+@item jne32 rd, rs, disp16
+@itemx jne32 rd, imm32, disp16
+@itemx if rd != rs goto disp16
+@itemx if rd != imm32 goto disp16
+Jump if not equal.
-@noindent
-Note that in the Pseudo-C syntax register names are not preceded by
-@code{%} characters.
+@item jsgt32 rd, rs, disp16
+@itemx jsgt32 rd, imm32, disp16
+@itemx if rd s> rs goto disp16
+@itemx if rd s> imm32 goto disp16
+Jump if signed greater.
-@subsubsection Arithmetic instructions
+@item jsge32 rd, rs, disp16
+@itemx jsge32 rd, imm32, disp16
+@itemx if rd s>= rd goto disp16
+@itemx if rd s>= imm32 goto disp16
+Jump if signed greater or equal.
-In all the instructions below, the operations are 64-bit or 32-bit
-depending on the names used to refer to the registers. For example
-@code{r3 += r2} will perform 64-bit addition, whereas @code{w3 += w2}
-will perform 32-bit addition. Mixing register prefixes is an error,
-for example @code{r3 += w2}.
+@item jslt32 rd, rs, disp16
+@itemx jslt32 rd, imm32, disp16
+@itemx if rd s< rs goto disp16
+@itemx if rd s< imm32 goto disp16
+Jump if signed lesser.
-@table @code
-@item dst_reg += (imm32|src_reg)
-Arithmetic addition.
-@item dst_reg -= (imm32|src_reg)
-Arithmetic subtraction.
-@item dst_reg *= (imm32|src_reg)
-Arithmetic multiplication.
-@item dst_reg /= (imm32|src_reg)
-Arithmetic integer unsigned division.
-@item dst_reg %= (imm32|src_reg)
-Arithmetic integer unsigned remainder.
-@item dst_reg &= (imm32|src_reg)
-Bit-wise ``and'' operation.
-@item dst_reg |= (imm32|src_reg)
-Bit-wise ``or'' operation.
-@item dst_reg ^= (imm32|src_reg)
-Bit-wise exclusive-or operation.
-@item dst_reg <<= (imm32|src_reg)
-Left shift, by whatever specified number of bits.
-@item dst_reg >>= (imm32|src_reg)
-Right logical shift, by whatever specified number of bits.
-@item dst_reg s>>= (imm32|src_reg)
-Right arithmetic shift, by whatever specified number of bits.
-@item dst_reg = (imm32|src_reg)
-Move the value in @code{imm32} or @code{src_reg} in @code{dst_reg}.
-@item dst_reg = -dst_reg
-Arithmetic negation.
+@item jsle32 rd, rs, disp16
+@itemx jsle32 rd, imm32, disp16
+@itemx if rd s<= rs goto disp16
+@itemx if rd s<= imm32 goto disp16
+Jump if signed lesser or equal.
@end table
-@subsubsection Endianness conversion instructions
+@subsection Atomic instructions
+
+Atomic exchange-and-add instructions are provided in two flavors: one
+for swapping 64-bit quantities and another for 32-bit quantities.
@table @code
-@item dst_reg = le16 src_reg
-Convert the 16-bit value in @code{src_reg} to little-endian.
-@item dst_reg = le32 src_reg
-Convert the 32-bit value in @code{src_reg} to little-endian.
-@item dst_reg = le64 src_reg
-Convert the 64-bit value in @code{src_reg} to little-endian.
-@item dst_reg = be16 src_reg
-Convert the 16-bit value in @code{src_reg} to big-endian.
-@item dst_reg = be32 src_reg
-Convert the 32-bit value in @code{src_reg} to big-endian.
-@item dst_reg = be64 src_reg
-Convert the 64-bit value in @code{src_reg} to big-endian.
+@item aadd [rd + offset16], rs
+@itemx *(u64 *)(rd + offset16) = rs
+Atomic add instruction.
+
+@item aor [rd + offset16], rs
+@itemx *(u64 *) (rd + offset16) |= rs
+Atomic or instruction.
+
+@item aand [rd + offset16], rs
+@itemx *(u64 *) (rd + offset16) &= rs
+Atomic and instruction.
+
+@item axor [rd + offset16], rs
+@itemx *(u64 *) (rd + offset16) ^= rs
+Atomic xor instruction
+@item xaddw [%d+offset16],%s
+Exchange-and-add a 32-bit value at the specified location.
@end table
-@subsubsection 64-bit load and pseudo maps
+@noindent
+The following variants perform fetching before the atomic operation.
@table @code
-@item dst_reg = imm64 ll
-Load the given signed 64-bit immediate, or pseudo map descriptor, to
-the destination register @code{dst_reg}.
+@item afadd [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-add instruction.
+
+@item afor [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction.
+
+@item afand [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-and instruction.
+
+@item afxor [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction
@end table
-@subsubsection Load instructions for socket filters
+The above instructions were introduced in the V3 of the BPF
+instruction set. The following instruction is supported for backwards
+compatibility:
@table @code
-@item r0 = *(u8 *)skb[imm32]
-Absolute 8-bit load.
-@item r0 = *(u16 *)skb[imm32]
-Absolute 16-bit load.
-@item r0 = *(u32 *)skb[imm32]
-Absolute 32-bit load.
-@item r0 = *(u64 *)skb[imm32]
-Absolute 64-bit load.
-@item r0 = *(u8 *)skb[src_reg + imm32]
-Indirect 8-bit load.
-@item r0 = *(u16 *)skb[src_reg + imm32]
-Indirect 16-bit load.
-@item r0 = *(u32 *)skb[src_reg + imm32]
-Indirect 32-bit load.
-@item r0 = *(u64 *)skb[src_reg + imm32]
-Indirect 64-bit load.
+@item xadddw [rd + offset16], rs
+Alias to @code{aadd}.
@end table
-@subsubsection Generic load/store instructions
+@subsection 32-bit atomic instructions
+
+Atomic exchange-and-add instructions are provided in two flavors: one
+for swapping 32-bit quantities and another for 32-bit quantities.
@table @code
-@item dst_reg = *(u8 *)(src_reg + offset16)
-Generic 8-bit load.
-@item dst_reg = *(u16 *)(src_reg + offset16)
-Generic 16-bit load.
-@item dst_reg = *(u32 *)(src_reg + offset16)
-Generic 32-bit load.
-@item dst_reg = *(u64 *)(src_reg + offset16)
-Generic 64-bit load.
-@c XXX stb
-@c NO PSEUDOC-SYNTAX
-@c XXX sth
-@c NO PSEUDOC-SYNTAX
-@c XXX stw
-@c NO PSEUDOC-SYNTAX
-@c XXX stdw
-@c NO PSEUDOC-SYNTAX
-@item *(u8 *)(dst_reg + offset16) = src_reg
-Generic 8-bit store.
-@item *(u16 *)(dst_reg + offset16) = src_reg
-Generic 16-bit store.
-@item *(u32 *)(dst_reg + offset16) = src_reg
-Generic 32-bit store.
-@item *(u64 *)(dst_reg + offset16) = src_reg
-Generic 64-bit store.
+@item aadd32 [rd + offset16], rs
+@itemx *(u32 *)(rd + offset16) = rs
+Atomic add instruction.
+
+@item aor32 [rd + offset16], rs
+@itemx *(u32 *) (rd + offset16) |= rs
+Atomic or instruction.
+
+@item aand32 [rd + offset16], rs
+@itemx *(u32 *) (rd + offset16) &= rs
+Atomic and instruction.
+
+@item axor32 [rd + offset16], rs
+@itemx *(u32 *) (rd + offset16) ^= rs
+Atomic xor instruction
@end table
-@subsubsection Jump instructions
+@noindent
+The following variants perform fetching before the atomic operation.
@table @code
-@item goto disp16
-Jump-always.
-@item if dst_reg == (imm32|src_reg) goto disp16
-Jump if equal.
-@item if dst_reg & (imm32|src_reg) goto disp16
-Jump if signed equal.
-@item if dst_reg != (imm32|src_reg) goto disp16
-Jump if not equal.
-@item if dst_reg > (imm32|src_reg) goto disp16
-Jump if bigger, unsigned.
-@item if dst_reg < (imm32|src_reg) goto disp16
-Jump if smaller, unsigned.
-@item if dst_reg >= (imm32|src_reg) goto disp16
-Jump if bigger or equal, unsigned.
-@item if dst_reg <= (imm32|src_reg) goto disp16
-Jump if smaller or equal, unsigned.
-@item if dst_reg s> (imm32|src_reg) goto disp16
-Jump if bigger, signed.
-@item if dst_reg s< (imm32|src_reg) goto disp16
-Jump if smaller, signed.
-@item if dst_reg s>= (imm32|src_reg) goto disp16
-Jump if bigger or equal, signed.
-@item if dst_reg s<= (imm32|src_reg) goto disp16
-Jump if smaller or equal, signed.
-@item call imm32
-Jump and link.
-@item exit
-Terminate the eBPF program.
+@item afadd32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-add instruction.
+
+@item afor32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction.
+
+@item afand32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-and instruction.
+
+@item afxor32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction
@end table
-@subsubsection Atomic instructions
+The above instructions were introduced in the V3 of the BPF
+instruction set. The following instruction is supported for backwards
+compatibility:
@table @code
-@item lock *(u64 *)(dst_reg + offset16) += src_reg
-Exchange-and-add a 64-bit value at the specified location.
-@item lock *(u32 *)(dst_reg + offset16) += src_reg
-Exchange-and-add a 32-bit value at the specified location.
+@item xaddw [rd + offset16], rs
+Alias to @code{aadd32}.
@end table
#name: bad recursive assignments
#source: assign-bad-recursive.s
#xfail: bfin-*-*
-#notarget: *bpf-*-*
#error_output: assign-bad-recursive.l
#name: eqv involving dot
# bfin doesn't support 'symbol = expression'
# tic30 and tic4x have 4 octets per byte, tic54x has 2 octets per byte
-#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* *bpf-*-*
+#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-*
# linkrelax targets don't handle equivalence expressions well (nor any
# other forward expression). mep uses complex relocs
#xfail: am33_2.0-*-* crx-*-* h8300-*-* mn10200-*-* mn10300-*-* mep-*-*
run_dump_test eqv-dot
}
-if { ![istarget "bfin-*-*"] && ![istarget "bpf-*-*"] } then {
+if { ![istarget "bfin-*-*"] } then {
gas_test "assign-ok.s" "" "" "== assignment support"
}
gas_test_error "assign-bad.s" "" "== assignment for symbol already set"
gas_test "fastcall.s" "" "" "fastcall labels"
}
-if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] \
- && ![istarget "bpf-*-*"] } then {
+if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] } then {
run_dump_test assign
}
run_dump_test sleb128
-#as: --EB
+#as: -EB -mdialect=pseudoc
#source: alu-pseudoc.s
-#objdump: -dr
-#dump: alu-be.dump
+#objdump: -dr -M hex,pseudoc
#name: eBPF ALU64 instructions, big endian, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 20 00 00 00 00 02 9a r2\+=0x29a
+ 8: 07 30 00 00 ff ff fd 66 r3\+=0xfffffd66
+ 10: 07 40 00 00 7e ad be ef r4\+=0x7eadbeef
+ 18: 0f 56 00 00 00 00 00 00 r5\+=r6
+ 20: 17 20 00 00 00 00 02 9a r2-=0x29a
+ 28: 17 30 00 00 ff ff fd 66 r3-=0xfffffd66
+ 30: 17 40 00 00 7e ad be ef r4-=0x7eadbeef
+ 38: 1f 56 00 00 00 00 00 00 r5-=r6
+ 40: 27 20 00 00 00 00 02 9a r2\*=0x29a
+ 48: 27 30 00 00 ff ff fd 66 r3\*=0xfffffd66
+ 50: 27 40 00 00 7e ad be ef r4\*=0x7eadbeef
+ 58: 2f 56 00 00 00 00 00 00 r5\*=r6
+ 60: 37 20 00 00 00 00 02 9a r2/=0x29a
+ 68: 37 30 00 00 ff ff fd 66 r3/=0xfffffd66
+ 70: 37 40 00 00 7e ad be ef r4/=0x7eadbeef
+ 78: 3f 56 00 00 00 00 00 00 r5/=r6
+ 80: 47 20 00 00 00 00 02 9a r2|=0x29a
+ 88: 47 30 00 00 ff ff fd 66 r3|=0xfffffd66
+ 90: 47 40 00 00 7e ad be ef r4|=0x7eadbeef
+ 98: 4f 56 00 00 00 00 00 00 r5|=r6
+ a0: 57 20 00 00 00 00 02 9a r2&=0x29a
+ a8: 57 30 00 00 ff ff fd 66 r3&=0xfffffd66
+ b0: 57 40 00 00 7e ad be ef r4&=0x7eadbeef
+ b8: 5f 56 00 00 00 00 00 00 r5&=r6
+ c0: 67 20 00 00 00 00 02 9a r2<<=0x29a
+ c8: 67 30 00 00 ff ff fd 66 r3<<=0xfffffd66
+ d0: 67 40 00 00 7e ad be ef r4<<=0x7eadbeef
+ d8: 6f 56 00 00 00 00 00 00 r5<<=r6
+ e0: 77 20 00 00 00 00 02 9a r2>>=0x29a
+ e8: 77 30 00 00 ff ff fd 66 r3>>=0xfffffd66
+ f0: 77 40 00 00 7e ad be ef r4>>=0x7eadbeef
+ f8: 7f 56 00 00 00 00 00 00 r5>>=r6
+ 100: 97 20 00 00 00 00 02 9a r2%=0x29a
+ 108: 97 30 00 00 ff ff fd 66 r3%=0xfffffd66
+ 110: 97 40 00 00 7e ad be ef r4%=0x7eadbeef
+ 118: 9f 56 00 00 00 00 00 00 r5%=r6
+ 120: a7 20 00 00 00 00 02 9a r2\^=0x29a
+ 128: a7 30 00 00 ff ff fd 66 r3\^=0xfffffd66
+ 130: a7 40 00 00 7e ad be ef r4\^=0x7eadbeef
+ 138: af 56 00 00 00 00 00 00 r5\^=r6
+ 140: b7 20 00 00 00 00 02 9a r2=0x29a
+ 148: b7 30 00 00 ff ff fd 66 r3=0xfffffd66
+ 150: b7 40 00 00 7e ad be ef r4=0x7eadbeef
+ 158: bf 56 00 00 00 00 00 00 r5=r6
+ 160: c7 20 00 00 00 00 02 9a r2 s>>=0x29a
+ 168: c7 30 00 00 ff ff fd 66 r3 s>>=0xfffffd66
+ 170: c7 40 00 00 7e ad be ef r4 s>>=0x7eadbeef
+ 178: cf 56 00 00 00 00 00 00 r5 s>>=r6
+ 180: 8f 23 00 00 00 00 00 00 r2=-r3
+ 188: d4 90 00 00 00 00 00 10 r9=le16 r9
+ 190: d4 80 00 00 00 00 00 20 r8=le32 r8
+ 198: d4 70 00 00 00 00 00 40 r7=le64 r7
+ 1a0: dc 60 00 00 00 00 00 10 r6=be16 r6
+ 1a8: dc 50 00 00 00 00 00 20 r5=be32 r5
+ 1b0: dc 40 00 00 00 00 00 40 r4=be64 r4
-#as: --EB
+#as: -EB -mdialect=normal
#source: alu.s
-#objdump: -dr
-#dump: alu-be.dump
-#name: eBPF ALU64 instructions, big endian, normal syntax
+#objdump: -dr -M hex
+#name: eBPF ALU instructions, big endian, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 20 00 00 00 00 02 9a add %r2,0x29a
+ 8: 07 30 00 00 ff ff fd 66 add %r3,0xfffffd66
+ 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
+ 18: 0f 56 00 00 00 00 00 00 add %r5,%r6
+ 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
+ 28: 17 30 00 00 ff ff fd 66 sub %r3,0xfffffd66
+ 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
+ 38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
+ 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
+ 48: 27 30 00 00 ff ff fd 66 mul %r3,0xfffffd66
+ 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
+ 58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
+ 60: 37 20 00 00 00 00 02 9a div %r2,0x29a
+ 68: 37 30 00 00 ff ff fd 66 div %r3,0xfffffd66
+ 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
+ 78: 3f 56 00 00 00 00 00 00 div %r5,%r6
+ 80: 47 20 00 00 00 00 02 9a or %r2,0x29a
+ 88: 47 30 00 00 ff ff fd 66 or %r3,0xfffffd66
+ 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
+ 98: 4f 56 00 00 00 00 00 00 or %r5,%r6
+ a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
+ a8: 57 30 00 00 ff ff fd 66 and %r3,0xfffffd66
+ b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
+ b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
+ c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
+ c8: 67 30 00 00 ff ff fd 66 lsh %r3,0xfffffd66
+ d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
+ d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
+ e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
+ e8: 77 30 00 00 ff ff fd 66 rsh %r3,0xfffffd66
+ f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
+ f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
+ 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
+ 108: 97 30 00 00 ff ff fd 66 mod %r3,0xfffffd66
+ 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
+ 118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
+ 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
+ 128: a7 30 00 00 ff ff fd 66 xor %r3,0xfffffd66
+ 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
+ 138: af 56 00 00 00 00 00 00 xor %r5,%r6
+ 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
+ 148: b7 30 00 00 ff ff fd 66 mov %r3,0xfffffd66
+ 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
+ 158: bf 56 00 00 00 00 00 00 mov %r5,%r6
+ 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
+ 168: c7 30 00 00 ff ff fd 66 arsh %r3,0xfffffd66
+ 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
+ 178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
+ 180: 8f 23 00 00 00 00 00 00 neg %r2,%r3
+ 188: d4 90 00 00 00 00 00 10 endle %r9,16
+ 190: d4 80 00 00 00 00 00 20 endle %r8,32
+ 198: d4 70 00 00 00 00 00 40 endle %r7,64
+ 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
+ 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
+ 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 07 20 00 00 00 00 02 9a add %r2,0x29a
- 8: 07 30 00 00 ff ff fd 66 add %r3,-666
- 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
- 18: 0f 56 00 00 00 00 00 00 add %r5,%r6
- 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
- 28: 17 30 00 00 ff ff fd 66 sub %r3,-666
- 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
- 38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
- 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
- 48: 27 30 00 00 ff ff fd 66 mul %r3,-666
- 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
- 58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
- 60: 37 20 00 00 00 00 02 9a div %r2,0x29a
- 68: 37 30 00 00 ff ff fd 66 div %r3,-666
- 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
- 78: 3f 56 00 00 00 00 00 00 div %r5,%r6
- 80: 47 20 00 00 00 00 02 9a or %r2,0x29a
- 88: 47 30 00 00 ff ff fd 66 or %r3,-666
- 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
- 98: 4f 56 00 00 00 00 00 00 or %r5,%r6
- a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
- a8: 57 30 00 00 ff ff fd 66 and %r3,-666
- b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
- b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
- c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
- c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
- d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
- d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
- e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
- e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
- f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
- f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
- 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
- 108: 97 30 00 00 ff ff fd 66 mod %r3,-666
- 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
- 118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
- 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
- 128: a7 30 00 00 ff ff fd 66 xor %r3,-666
- 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
- 138: af 56 00 00 00 00 00 00 xor %r5,%r6
- 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
- 148: b7 30 00 00 ff ff fd 66 mov %r3,-666
- 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
- 158: bf 56 00 00 00 00 00 00 mov %r5,%r6
- 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
- 168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
- 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
- 178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
- 180: 87 20 00 00 00 00 00 00 neg %r2
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
#source: alu-pseudoc.s
-#dump: alu.dump
-#name: eBPF ALU64 instructions, pseudo-c syntax
+#name: eBPF ALU instructions, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 02 00 00 9a 02 00 00 r2\+=0x29a
+ 8: 07 03 00 00 66 fd ff ff r3\+=0xfffffd66
+ 10: 07 04 00 00 ef be ad 7e r4\+=0x7eadbeef
+ 18: 0f 65 00 00 00 00 00 00 r5\+=r6
+ 20: 17 02 00 00 9a 02 00 00 r2-=0x29a
+ 28: 17 03 00 00 66 fd ff ff r3-=0xfffffd66
+ 30: 17 04 00 00 ef be ad 7e r4-=0x7eadbeef
+ 38: 1f 65 00 00 00 00 00 00 r5-=r6
+ 40: 27 02 00 00 9a 02 00 00 r2\*=0x29a
+ 48: 27 03 00 00 66 fd ff ff r3\*=0xfffffd66
+ 50: 27 04 00 00 ef be ad 7e r4\*=0x7eadbeef
+ 58: 2f 65 00 00 00 00 00 00 r5\*=r6
+ 60: 37 02 00 00 9a 02 00 00 r2/=0x29a
+ 68: 37 03 00 00 66 fd ff ff r3/=0xfffffd66
+ 70: 37 04 00 00 ef be ad 7e r4/=0x7eadbeef
+ 78: 3f 65 00 00 00 00 00 00 r5/=r6
+ 80: 47 02 00 00 9a 02 00 00 r2|=0x29a
+ 88: 47 03 00 00 66 fd ff ff r3|=0xfffffd66
+ 90: 47 04 00 00 ef be ad 7e r4|=0x7eadbeef
+ 98: 4f 65 00 00 00 00 00 00 r5|=r6
+ a0: 57 02 00 00 9a 02 00 00 r2&=0x29a
+ a8: 57 03 00 00 66 fd ff ff r3&=0xfffffd66
+ b0: 57 04 00 00 ef be ad 7e r4&=0x7eadbeef
+ b8: 5f 65 00 00 00 00 00 00 r5&=r6
+ c0: 67 02 00 00 9a 02 00 00 r2<<=0x29a
+ c8: 67 03 00 00 66 fd ff ff r3<<=0xfffffd66
+ d0: 67 04 00 00 ef be ad 7e r4<<=0x7eadbeef
+ d8: 6f 65 00 00 00 00 00 00 r5<<=r6
+ e0: 77 02 00 00 9a 02 00 00 r2>>=0x29a
+ e8: 77 03 00 00 66 fd ff ff r3>>=0xfffffd66
+ f0: 77 04 00 00 ef be ad 7e r4>>=0x7eadbeef
+ f8: 7f 65 00 00 00 00 00 00 r5>>=r6
+ 100: 97 02 00 00 9a 02 00 00 r2%=0x29a
+ 108: 97 03 00 00 66 fd ff ff r3%=0xfffffd66
+ 110: 97 04 00 00 ef be ad 7e r4%=0x7eadbeef
+ 118: 9f 65 00 00 00 00 00 00 r5%=r6
+ 120: a7 02 00 00 9a 02 00 00 r2\^=0x29a
+ 128: a7 03 00 00 66 fd ff ff r3\^=0xfffffd66
+ 130: a7 04 00 00 ef be ad 7e r4\^=0x7eadbeef
+ 138: af 65 00 00 00 00 00 00 r5\^=r6
+ 140: b7 02 00 00 9a 02 00 00 r2=0x29a
+ 148: b7 03 00 00 66 fd ff ff r3=0xfffffd66
+ 150: b7 04 00 00 ef be ad 7e r4=0x7eadbeef
+ 158: bf 65 00 00 00 00 00 00 r5=r6
+ 160: c7 02 00 00 9a 02 00 00 r2 s>>=0x29a
+ 168: c7 03 00 00 66 fd ff ff r3 s>>=0xfffffd66
+ 170: c7 04 00 00 ef be ad 7e r4 s>>=0x7eadbeef
+ 178: cf 65 00 00 00 00 00 00 r5 s>>=r6
+ 180: 8f 32 00 00 00 00 00 00 r2=-r3
+ 188: d4 09 00 00 10 00 00 00 r9=le16 r9
+ 190: d4 08 00 00 20 00 00 00 r8=le32 r8
+ 198: d4 07 00 00 40 00 00 00 r7=le64 r7
+ 1a0: dc 06 00 00 10 00 00 00 r6=be16 r6
+ 1a8: dc 05 00 00 20 00 00 00 r5=be32 r5
+ 1b0: dc 04 00 00 40 00 00 00 r4=be64 r4
r3 s>>= -666
r4 s>>= 2125315823
r5 s>>= r6
- r2 = -r2
+ r2 = - r3
+ r9 = le16 r9
+ r8 = le32 r8
+ r7 = le64 r7
+ r6 = be16 r6
+ r5 = be32 r5
+ r4 = be64 r4
+++ /dev/null
-#as: --EL -mxbpf
-#objdump: -dr -mxbpf
-#name: xBPF ALU64 insns
-
-.*: +file format .*bpf.*
-
-Disassembly of section \.text:
-
-0+ <\.text>:
- 0: e7 02 00 00 02 00 00 00 sdiv %r2,2
- 8: e7 03 00 00 fd ff ff ff sdiv %r3,-3
- 10: e7 04 00 00 ef be ad 7e sdiv %r4,0x7eadbeef
- 18: ef 25 00 00 00 00 00 00 sdiv %r5,%r2
- 20: f7 02 00 00 03 00 00 00 smod %r2,3
- 28: f7 03 00 00 fc ff ff ff smod %r3,-4
- 30: f7 04 00 00 ef be ad 7e smod %r4,0x7eadbeef
- 38: ff 25 00 00 00 00 00 00 smod %r5,%r2
+++ /dev/null
- # Tests for xBPF-specific alu instructions
- .text
- sdiv %r2, 2
- sdiv %r3, -3
- sdiv %r4, 0x7eadbeef
- sdiv %r5, %r2
-
- smod %r2, 3
- smod %r3, -4
- smod %r4, 0x7eadbeef
- smod %r5, %r2
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
#source: alu.s
-#dump: alu.dump
-#name: eBPF ALU64 instructions, normal syntax
+#name: eBPF ALU instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
+ 8: 07 03 00 00 66 fd ff ff add %r3,0xfffffd66
+ 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
+ 18: 0f 65 00 00 00 00 00 00 add %r5,%r6
+ 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
+ 28: 17 03 00 00 66 fd ff ff sub %r3,0xfffffd66
+ 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
+ 38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
+ 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
+ 48: 27 03 00 00 66 fd ff ff mul %r3,0xfffffd66
+ 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
+ 58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
+ 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
+ 68: 37 03 00 00 66 fd ff ff div %r3,0xfffffd66
+ 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
+ 78: 3f 65 00 00 00 00 00 00 div %r5,%r6
+ 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
+ 88: 47 03 00 00 66 fd ff ff or %r3,0xfffffd66
+ 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
+ 98: 4f 65 00 00 00 00 00 00 or %r5,%r6
+ a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
+ a8: 57 03 00 00 66 fd ff ff and %r3,0xfffffd66
+ b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
+ b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
+ c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
+ c8: 67 03 00 00 66 fd ff ff lsh %r3,0xfffffd66
+ d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
+ d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
+ e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
+ e8: 77 03 00 00 66 fd ff ff rsh %r3,0xfffffd66
+ f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
+ f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
+ 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
+ 108: 97 03 00 00 66 fd ff ff mod %r3,0xfffffd66
+ 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
+ 118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
+ 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
+ 128: a7 03 00 00 66 fd ff ff xor %r3,0xfffffd66
+ 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
+ 138: af 65 00 00 00 00 00 00 xor %r5,%r6
+ 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
+ 148: b7 03 00 00 66 fd ff ff mov %r3,0xfffffd66
+ 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
+ 158: bf 65 00 00 00 00 00 00 mov %r5,%r6
+ 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
+ 168: c7 03 00 00 66 fd ff ff arsh %r3,0xfffffd66
+ 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
+ 178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
+ 180: 8f 32 00 00 00 00 00 00 neg %r2,%r3
+ 188: d4 09 00 00 10 00 00 00 endle %r9,16
+ 190: d4 08 00 00 20 00 00 00 endle %r8,32
+ 198: d4 07 00 00 40 00 00 00 endle %r7,64
+ 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
+ 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
+ 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
- 8: 07 03 00 00 66 fd ff ff add %r3,-666
- 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
- 18: 0f 65 00 00 00 00 00 00 add %r5,%r6
- 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
- 28: 17 03 00 00 66 fd ff ff sub %r3,-666
- 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
- 38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
- 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
- 48: 27 03 00 00 66 fd ff ff mul %r3,-666
- 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
- 58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
- 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
- 68: 37 03 00 00 66 fd ff ff div %r3,-666
- 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
- 78: 3f 65 00 00 00 00 00 00 div %r5,%r6
- 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
- 88: 47 03 00 00 66 fd ff ff or %r3,-666
- 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
- 98: 4f 65 00 00 00 00 00 00 or %r5,%r6
- a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
- a8: 57 03 00 00 66 fd ff ff and %r3,-666
- b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
- b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
- c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
- c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
- d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
- d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
- e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
- e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
- f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
- f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
- 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
- 108: 97 03 00 00 66 fd ff ff mod %r3,-666
- 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
- 118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
- 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
- 128: a7 03 00 00 66 fd ff ff xor %r3,-666
- 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
- 138: af 65 00 00 00 00 00 00 xor %r5,%r6
- 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
- 148: b7 03 00 00 66 fd ff ff mov %r3,-666
- 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
- 158: bf 65 00 00 00 00 00 00 mov %r5,%r6
- 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
- 168: c7 03 00 00 66 fd ff ff arsh %r3,-666
- 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
- 178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
- 180: 87 02 00 00 00 00 00 00 neg %r2
arsh %r3, -666
arsh %r4, 0x7eadbeef
arsh %r5, %r6
- neg %r2
+ neg %r2, %r3
+ endle %r9,16
+ endle %r8,32
+ endle %r7,64
+ endbe %r6,16
+ endbe %r5,32
+ endbe %r4,64
-#as: --EB
-#objdump: -dr
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
#source: alu32-pseudoc.s
-#dump: alu32-be.dump
-#name: eBPF ALU instructions, big-endian, pseudo-c syntax
+#name: eBPF ALU32 instructions, big-endian, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 20 00 00 00 00 02 9a w2\+=0x29a
+ 8: 04 30 00 00 ff ff fd 66 w3\+=0xfffffd66
+ 10: 04 40 00 00 7e ad be ef w4\+=0x7eadbeef
+ 18: 0c 56 00 00 00 00 00 00 w5\+=w6
+ 20: 14 20 00 00 00 00 02 9a w2-=0x29a
+ 28: 14 30 00 00 ff ff fd 66 w3-=0xfffffd66
+ 30: 14 40 00 00 7e ad be ef w4-=0x7eadbeef
+ 38: 1c 56 00 00 00 00 00 00 w5-=w6
+ 40: 24 20 00 00 00 00 02 9a w2\*=0x29a
+ 48: 24 30 00 00 ff ff fd 66 w3\*=0xfffffd66
+ 50: 24 40 00 00 7e ad be ef w4\*=0x7eadbeef
+ 58: 2c 56 00 00 00 00 00 00 w5\*=w6
+ 60: 34 20 00 00 00 00 02 9a w2/=0x29a
+ 68: 34 30 00 00 ff ff fd 66 w3/=0xfffffd66
+ 70: 34 40 00 00 7e ad be ef w4/=0x7eadbeef
+ 78: 3c 56 00 00 00 00 00 00 w5/=w6
+ 80: 44 20 00 00 00 00 02 9a w2|=0x29a
+ 88: 44 30 00 00 ff ff fd 66 w3|=0xfffffd66
+ 90: 44 40 00 00 7e ad be ef w4|=0x7eadbeef
+ 98: 4c 56 00 00 00 00 00 00 w5|=w6
+ a0: 54 20 00 00 00 00 02 9a w2&=0x29a
+ a8: 54 30 00 00 ff ff fd 66 w3&=0xfffffd66
+ b0: 54 40 00 00 7e ad be ef w4&=0x7eadbeef
+ b8: 5c 56 00 00 00 00 00 00 w5&=w6
+ c0: 64 20 00 00 00 00 02 9a w2<<=0x29a
+ c8: 64 30 00 00 ff ff fd 66 w3<<=0xfffffd66
+ d0: 64 40 00 00 7e ad be ef w4<<=0x7eadbeef
+ d8: 6c 56 00 00 00 00 00 00 w5<<=w6
+ e0: 74 20 00 00 00 00 02 9a w2>>=0x29a
+ e8: 74 30 00 00 ff ff fd 66 w3>>=0xfffffd66
+ f0: 74 40 00 00 7e ad be ef w4>>=0x7eadbeef
+ f8: 7c 56 00 00 00 00 00 00 w5>>=w6
+ 100: 94 20 00 00 00 00 02 9a w2%=0x29a
+ 108: 94 30 00 00 ff ff fd 66 w3%=0xfffffd66
+ 110: 94 40 00 00 7e ad be ef w4%=0x7eadbeef
+ 118: 9c 56 00 00 00 00 00 00 w5%=w6
+ 120: a4 20 00 00 00 00 02 9a w2\^=0x29a
+ 128: a4 30 00 00 ff ff fd 66 w3\^=0xfffffd66
+ 130: a4 40 00 00 7e ad be ef w4\^=0x7eadbeef
+ 138: ac 56 00 00 00 00 00 00 w5\^=w6
+ 140: b4 20 00 00 00 00 02 9a w2=0x29a
+ 148: b4 30 00 00 ff ff fd 66 w3=0xfffffd66
+ 150: b4 40 00 00 7e ad be ef w4=0x7eadbeef
+ 158: bc 56 00 00 00 00 00 00 w5=w6
+ 160: c4 20 00 00 00 00 02 9a w2 s>>=0x29a
+ 168: c4 30 00 00 ff ff fd 66 w3 s>>=0xfffffd66
+ 170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef
+ 178: cc 56 00 00 00 00 00 00 w5 s>>=w6
+ 180: 8c 23 00 00 00 00 00 00 w2=-w3
-#as: --EB
-#objdump: -dr
-#source: alu32-pseudoc.s
-#dump: alu32-be.dump
-#name: eBPF ALU instructions, big-endian, normal syntax
+#as: -EB -mdialect=normal
+#objdump: -dr -M hex
+#source: alu32.s
+#name: eBPF ALU32 instructions, big-endian, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
+ 8: 04 30 00 00 ff ff fd 66 add32 %r3,0xfffffd66
+ 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
+ 18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
+ 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
+ 28: 14 30 00 00 ff ff fd 66 sub32 %r3,0xfffffd66
+ 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
+ 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
+ 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
+ 48: 24 30 00 00 ff ff fd 66 mul32 %r3,0xfffffd66
+ 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
+ 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
+ 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
+ 68: 34 30 00 00 ff ff fd 66 div32 %r3,0xfffffd66
+ 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
+ 78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
+ 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
+ 88: 44 30 00 00 ff ff fd 66 or32 %r3,0xfffffd66
+ 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
+ 98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
+ a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
+ a8: 54 30 00 00 ff ff fd 66 and32 %r3,0xfffffd66
+ b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
+ b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
+ c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
+ c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,0xfffffd66
+ d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
+ d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
+ e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
+ e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,0xfffffd66
+ f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
+ f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
+ 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
+ 108: 94 30 00 00 ff ff fd 66 mod32 %r3,0xfffffd66
+ 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
+ 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
+ 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
+ 128: a4 30 00 00 ff ff fd 66 xor32 %r3,0xfffffd66
+ 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
+ 138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
+ 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
+ 148: b4 30 00 00 ff ff fd 66 mov32 %r3,0xfffffd66
+ 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
+ 158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
+ 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
+ 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,0xfffffd66
+ 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
+ 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
+ 180: 8c 23 00 00 00 00 00 00 neg32 %r2,%r3
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
- 8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
- 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
- 18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
- 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
- 28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
- 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
- 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
- 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
- 48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
- 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
- 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
- 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
- 68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
- 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
- 78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
- 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
- 88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
- 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
- 98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
- a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
- a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
- b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
- b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
- c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
- c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
- d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
- d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
- e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
- e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
- f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
- f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
- 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
- 108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
- 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
- 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
- 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
- 128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
- 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
- 138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
- 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
- 148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
- 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
- 158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
- 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
- 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
- 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
- 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
- 180: 84 20 00 00 00 00 00 00 neg32 %r2
- 188: d4 90 00 00 00 00 00 10 endle %r9,16
- 190: d4 80 00 00 00 00 00 20 endle %r8,32
- 198: d4 70 00 00 00 00 00 40 endle %r7,64
- 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
- 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
- 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
#source: alu32-pseudoc.s
-#dump: alu32.dump
-#name: eBPF ALU instructions, pseudo-c syntax
+#name: eBPF ALU32 instructions, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 02 00 00 9a 02 00 00 w2\+=0x29a
+ 8: 04 03 00 00 66 fd ff ff w3\+=0xfffffd66
+ 10: 04 04 00 00 ef be ad 7e w4\+=0x7eadbeef
+ 18: 0c 65 00 00 00 00 00 00 w5\+=w6
+ 20: 14 02 00 00 9a 02 00 00 w2-=0x29a
+ 28: 14 03 00 00 66 fd ff ff w3-=0xfffffd66
+ 30: 14 04 00 00 ef be ad 7e w4-=0x7eadbeef
+ 38: 1c 65 00 00 00 00 00 00 w5-=w6
+ 40: 24 02 00 00 9a 02 00 00 w2\*=0x29a
+ 48: 24 03 00 00 66 fd ff ff w3\*=0xfffffd66
+ 50: 24 04 00 00 ef be ad 7e w4\*=0x7eadbeef
+ 58: 2c 65 00 00 00 00 00 00 w5\*=w6
+ 60: 34 02 00 00 9a 02 00 00 w2/=0x29a
+ 68: 34 03 00 00 66 fd ff ff w3/=0xfffffd66
+ 70: 34 04 00 00 ef be ad 7e w4/=0x7eadbeef
+ 78: 3c 65 00 00 00 00 00 00 w5/=w6
+ 80: 44 02 00 00 9a 02 00 00 w2|=0x29a
+ 88: 44 03 00 00 66 fd ff ff w3|=0xfffffd66
+ 90: 44 04 00 00 ef be ad 7e w4|=0x7eadbeef
+ 98: 4c 65 00 00 00 00 00 00 w5|=w6
+ a0: 54 02 00 00 9a 02 00 00 w2&=0x29a
+ a8: 54 03 00 00 66 fd ff ff w3&=0xfffffd66
+ b0: 54 04 00 00 ef be ad 7e w4&=0x7eadbeef
+ b8: 5c 65 00 00 00 00 00 00 w5&=w6
+ c0: 64 02 00 00 9a 02 00 00 w2<<=0x29a
+ c8: 64 03 00 00 66 fd ff ff w3<<=0xfffffd66
+ d0: 64 04 00 00 ef be ad 7e w4<<=0x7eadbeef
+ d8: 6c 65 00 00 00 00 00 00 w5<<=w6
+ e0: 74 02 00 00 9a 02 00 00 w2>>=0x29a
+ e8: 74 03 00 00 66 fd ff ff w3>>=0xfffffd66
+ f0: 74 04 00 00 ef be ad 7e w4>>=0x7eadbeef
+ f8: 7c 65 00 00 00 00 00 00 w5>>=w6
+ 100: 94 02 00 00 9a 02 00 00 w2%=0x29a
+ 108: 94 03 00 00 66 fd ff ff w3%=0xfffffd66
+ 110: 94 04 00 00 ef be ad 7e w4%=0x7eadbeef
+ 118: 9c 65 00 00 00 00 00 00 w5%=w6
+ 120: a4 02 00 00 9a 02 00 00 w2\^=0x29a
+ 128: a4 03 00 00 66 fd ff ff w3\^=0xfffffd66
+ 130: a4 04 00 00 ef be ad 7e w4\^=0x7eadbeef
+ 138: ac 65 00 00 00 00 00 00 w5\^=w6
+ 140: b4 02 00 00 9a 02 00 00 w2=0x29a
+ 148: b4 03 00 00 66 fd ff ff w3=0xfffffd66
+ 150: b4 04 00 00 ef be ad 7e w4=0x7eadbeef
+ 158: bc 65 00 00 00 00 00 00 w5=w6
+ 160: c4 02 00 00 9a 02 00 00 w2 s>>=0x29a
+ 168: c4 03 00 00 66 fd ff ff w3 s>>=0xfffffd66
+ 170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef
+ 178: cc 65 00 00 00 00 00 00 w5 s>>=w6
+ 180: 8c 32 00 00 00 00 00 00 w2=-w3
# Tests for the ALU eBPF pseudo-C instructions
.text
- W2 += 666
- W3 += -666
- W4 += 2125315823
- W5 += w6
- W2 -= 666
- W3 -= -666
- W4 -= 2125315823
- W5 -= w6
- W2 *= 666
- W3 *= -666
- W4 *= 2125315823
+ w2 += 666
+ w3 += -666
+ w4 += 2125315823
+ w5 += w6
+ w2 -= 666
+ w3 -= -666
+ w4 -= 2125315823
+ w5 -= w6
+ w2 *= 666
+ w3 *= -666
+ w4 *= 2125315823
w5 *= w6
w2 /= 666
w3 /= -666
w3 s>>= -666
w4 s>>= 2125315823
w5 s>>= w6
- w2 = -w2
- r9 = le16 r9
- r8 = le32 r8
- r7 = le64 r7
- r6 = be16 r6
- r5 = be32 r5
- r4 = be64 r4
+ w2 = - w3
+++ /dev/null
-#as: --EL -mxbpf
-#objdump: -dr -mxbpf
-#name: xBPF ALU32 insns
-
-.*: +file format .*bpf.*
-
-Disassembly of section \.text:
-
-0+ <\.text>:
- 0: e4 02 00 00 02 00 00 00 sdiv32 %r2,2
- 8: e4 03 00 00 fd ff ff ff sdiv32 %r3,-3
- 10: e4 04 00 00 ef be ad 7e sdiv32 %r4,0x7eadbeef
- 18: ec 25 00 00 00 00 00 00 sdiv32 %r5,%r2
- 20: f4 02 00 00 03 00 00 00 smod32 %r2,3
- 28: f4 03 00 00 fc ff ff ff smod32 %r3,-4
- 30: f4 04 00 00 ef be ad 7e smod32 %r4,0x7eadbeef
- 38: fc 25 00 00 00 00 00 00 smod32 %r5,%r2
+++ /dev/null
- # Tests for xBPF-specific alu instructions
- .text
- sdiv32 %r2, 2
- sdiv32 %r3, -3
- sdiv32 %r4, 0x7eadbeef
- sdiv32 %r5, %r2
-
- smod32 %r2, 3
- smod32 %r3, -4
- smod32 %r4, 0x7eadbeef
- smod32 %r5, %r2
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
#source: alu32.s
-#dump: alu32.dump
-#name: eBPF ALU instructions, normal syntax
+#name: eBPF ALU32 instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
+ 8: 04 03 00 00 66 fd ff ff add32 %r3,0xfffffd66
+ 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
+ 18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
+ 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
+ 28: 14 03 00 00 66 fd ff ff sub32 %r3,0xfffffd66
+ 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
+ 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
+ 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
+ 48: 24 03 00 00 66 fd ff ff mul32 %r3,0xfffffd66
+ 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
+ 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
+ 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
+ 68: 34 03 00 00 66 fd ff ff div32 %r3,0xfffffd66
+ 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
+ 78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
+ 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
+ 88: 44 03 00 00 66 fd ff ff or32 %r3,0xfffffd66
+ 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
+ 98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
+ a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
+ a8: 54 03 00 00 66 fd ff ff and32 %r3,0xfffffd66
+ b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
+ b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
+ c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
+ c8: 64 03 00 00 66 fd ff ff lsh32 %r3,0xfffffd66
+ d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
+ d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
+ e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
+ e8: 74 03 00 00 66 fd ff ff rsh32 %r3,0xfffffd66
+ f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
+ f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
+ 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
+ 108: 94 03 00 00 66 fd ff ff mod32 %r3,0xfffffd66
+ 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
+ 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
+ 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
+ 128: a4 03 00 00 66 fd ff ff xor32 %r3,0xfffffd66
+ 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
+ 138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
+ 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
+ 148: b4 03 00 00 66 fd ff ff mov32 %r3,0xfffffd66
+ 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
+ 158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
+ 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
+ 168: c4 03 00 00 66 fd ff ff arsh32 %r3,0xfffffd66
+ 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
+ 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
+ 180: 8c 32 00 00 00 00 00 00 neg32 %r2,%r3
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
- 8: 04 03 00 00 66 fd ff ff add32 %r3,-666
- 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
- 18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
- 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
- 28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
- 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
- 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
- 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
- 48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
- 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
- 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
- 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
- 68: 34 03 00 00 66 fd ff ff div32 %r3,-666
- 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
- 78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
- 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
- 88: 44 03 00 00 66 fd ff ff or32 %r3,-666
- 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
- 98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
- a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
- a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
- b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
- b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
- c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
- c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
- d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
- d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
- e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
- e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
- f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
- f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
- 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
- 108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
- 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
- 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
- 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
- 128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
- 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
- 138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
- 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
- 148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
- 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
- 158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
- 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
- 168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
- 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
- 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
- 180: 84 02 00 00 00 00 00 00 neg32 %r2
- 188: d4 09 00 00 10 00 00 00 endle %r9,16
- 190: d4 08 00 00 20 00 00 00 endle %r8,32
- 198: d4 07 00 00 40 00 00 00 endle %r7,64
- 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
- 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
- 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64
arsh32 %r3, -666
arsh32 %r4, 0x7eadbeef
arsh32 %r5, %r6
- neg32 %r2
- endle %r9,16
- endle %r8,32
- endle %r7,64
- endbe %r6,16
- endbe %r5,32
- endbe %r4,64
+ neg32 %r2, %r3
--- /dev/null
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
+#source: atomic-pseudoc.s
+#name: eBPF atomic instructions, pseudoc syntax, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 12 1e ef 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2
+ 8: c3 12 1e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2
-#as: --EB
+#as: -EB -mdialect=normal
#source: atomic.s
-#source: atomic-pseudoc.s
-#objdump: -dr
+#objdump: -dr -M hex,v1
#name: eBPF atomic instructions, big endian
.*: +file format .*bpf.*
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
#source: atomic-pseudoc.s
-#dump: atomic.dump
-#name: eBPF atomic instructions, normal syntax
+#name: eBPF atomic instructions, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 21 ef 1e 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2
+ 8: c3 21 ef 1e 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2
# Test for eBPF ADDW and ADDDW pseudo-C instructions
.text
- lock *(u64 *)(r1 + 7919) += r2
- lock *(u32 *)(r1 + 7919) += r2
+ *(u64 *)(r1 + 7919) += r2
+ *(u32 *)(r1 + 7919) += r2
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
#source: atomic.s
-#dump: atomic.dump
#name: eBPF atomic instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 21 ef 1e 00 00 00 00 aadd \[%r1\+0x1eef\],%r2
+ 8: c3 21 ef 1e 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
- 8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
# Test for eBPF ADDW and ADDDW instructions
.text
- xadddw [%r1+0x1eef], %r2
- xaddw [%r1+0x1eef], %r2
+ aadd [%r1+0x1eef], %r2
+ aadd32 [%r1+0x1eef], %r2
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
if {[istarget bpf*-*-*]} {
+ # Little-endian BPF tests
+ run_dump_test call
+ run_dump_test exit
+ run_dump_test data
run_dump_test lddw
run_dump_test lddw-pseudoc
run_dump_test alu
run_dump_test jump-pseudoc
run_dump_test jump32
run_dump_test jump32-pseudoc
- run_dump_test call
- run_dump_test exit
run_dump_test atomic
run_dump_test atomic-pseudoc
- run_dump_test data
- run_dump_test pseudoc-normal
+ run_dump_test indcall-1
+ run_dump_test indcall-1-pseudoc
+ # Big-endian BPF tests
+ run_dump_test call-be
+ run_dump_test exit-be
+ run_dump_test data-be
run_dump_test lddw-be
run_dump_test lddw-be-pseudoc
run_dump_test alu-be
run_dump_test alu32-be
run_dump_test alu32-be-pseudoc
run_dump_test mem-be
+ run_dump_test mem-be-pseudoc
run_dump_test jump-be
- run_dump_test call-be
- run_dump_test exit-be
+ run_dump_test jump-be-pseudoc
+ run_dump_test jump32-be
+ run_dump_test jump32-be-pseudoc
run_dump_test atomic-be
- run_dump_test data-be
- run_dump_test pseudoc-normal-be
-
- run_dump_test indcall-1
- run_dump_test indcall-1-pseudoc
- run_list_test indcall-bad-1
-
- run_dump_test alu-xbpf
- run_dump_test alu32-xbpf
+ run_dump_test atomic-be-pseudoc
}
-#as: --EB
+#as: -EB -mdialect=normal
#source: call.s
-#objdump: -dr
+#objdump: -dr -M dec
#name: eBPF CALL instruction, big endian
.*: +file format .*bpf.*
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M dec
#name: eBPF CALL instruction
.*: +file format .*bpf.*
-#as: --EB
+#as: -EB -mdialect=normal
#source: data.s
#objdump: -s -j .data
#name: eBPF data directives, big endian
-#as: --EL
+#as: -EL -mdialect=normal
#objdump: -s -j .data
#name: eBPF data directives
-#as: --EB
+#as: -EB -mdialect=normal
#source: exit.s
-#objdump: -dr
+#objdump: -dr -M hex
#name: eBPF EXIT instruction, big endian
.*: +file format .*bpf.*
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
#name: eBPF EXIT instruction
.*: +file format .*bpf.*
-#as: -mxbpf --EL
-#objdump: -mxbpf -dr
+#as: -EL -mdialect=pseudoc -misa-spec=xbpf
+#objdump: -M xbpf,pseudoc,dec -dr
#source: indcall-1-pseudoc.s
-#dump: indcall-1.dump
#name: BPF indirect call 1, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0000000000000000 <main>:
+ 0: b7 00 00 00 01 00 00 00 r0=1
+ 8: b7 01 00 00 01 00 00 00 r1=1
+ 10: b7 02 00 00 02 00 00 00 r2=2
+ 18: 18 06 00 00 38 00 00 00 r6=56 ll
+ 20: 00 00 00 00 00 00 00 00[ ]*
+ 18: R_BPF_64_64 .text
+ 28: 8d 06 00 00 00 00 00 00 callx r6
+ 30: 95 00 00 00 00 00 00 00 exit
+
+0000000000000038 <bar>:
+ 38: b7 00 00 00 00 00 00 00 r0=0
+ 40: 95 00 00 00 00 00 00 00 exit
+#pass
-#as: -mxbpf --EL
-#objdump: -mxbpf -dr
+#as: -EL -misa-spec=xbpf
+#objdump: -dr -M xbpf,dec
#source: indcall-1.s
-#dump: indcall-1.dump
#name: BPF indirect call 1, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0000000000000000 <main>:
+ 0: b7 00 00 00 01 00 00 00 mov %r0,1
+ 8: b7 01 00 00 01 00 00 00 mov %r1,1
+ 10: b7 02 00 00 02 00 00 00 mov %r2,2
+ 18: 18 06 00 00 38 00 00 00 lddw %r6,56
+ 20: 00 00 00 00 00 00 00 00[ ]*
+ 18: R_BPF_64_64 .text
+ 28: 8d 06 00 00 00 00 00 00 call %r6
+ 30: 95 00 00 00 00 00 00 00 exit
+
+0000000000000038 <bar>:
+ 38: b7 00 00 00 00 00 00 00 mov %r0,0
+ 40: 95 00 00 00 00 00 00 00 exit
+#pass
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section \.text:
-
-0000000000000000 <main>:
- 0: b7 00 00 00 01 00 00 00 mov %r0,1
- 8: b7 01 00 00 01 00 00 00 mov %r1,1
- 10: b7 02 00 00 02 00 00 00 mov %r2,2
- 18: 18 06 00 00 38 00 00 00 lddw %r6,0x38
- 20: 00 00 00 00 00 00 00 00[ ]*
- 18: R_BPF_64_64 .text
- 28: 8d 06 00 00 00 00 00 00 call %r6
- 30: 95 00 00 00 00 00 00 00 exit
-
-0000000000000038 <bar>:
- 38: b7 00 00 00 00 00 00 00 mov %r0,0
- 40: 95 00 00 00 00 00 00 00 exit
-#pass
+++ /dev/null
-.*: Assembler messages:
-.* Error: bad expression
-.* Error: illegal operand `call %r6'
-.* Error: unexpected token: '%r6'
-#pass
--- /dev/null
+#as: -EB -mdialect=pseudoc
+#source: jump-pseudoc.s
+#objdump: -dr -M dec,pseudoc
+#name: eBPF JUMP instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 00 03 00 00 00 00 goto 3
+ 8: 0f 11 00 00 00 00 00 00 r1\+=r1
+ 10: 15 30 00 01 00 00 00 03 if r3==3 goto 1
+ 18: 1d 34 00 00 00 00 00 00 if r3==r4 goto 0
+ 20: 35 30 ff fd 00 00 00 03 if r3>=3 goto -3
+ 28: 3d 34 ff fc 00 00 00 00 if r3>=r4 goto -4
+ 30: a5 30 00 01 00 00 00 03 if r3<3 goto 1
+ 38: ad 34 00 00 00 00 00 00 if r3<r4 goto 0
+ 40: b5 30 00 01 00 00 00 03 if r3<=3 goto 1
+ 48: bd 34 00 00 00 00 00 00 if r3<=r4 goto 0
+ 50: 45 30 00 01 00 00 00 03 if r3&3 goto 1
+ 58: 4d 34 00 00 00 00 00 00 if r3&r4 goto 0
+ 60: 55 30 00 01 00 00 00 03 if r3!=3 goto 1
+ 68: 5d 34 00 00 00 00 00 00 if r3!=r4 goto 0
+ 70: 65 30 00 01 00 00 00 03 if r3s>3 goto 1
+ 78: 6d 34 00 00 00 00 00 00 if r3s>r4 goto 0
+ 80: 75 30 00 01 00 00 00 03 if r3s>=3 goto 1
+ 88: 7d 34 00 00 00 00 00 00 if r3s>=r4 goto 0
+ 90: c5 30 00 01 00 00 00 03 if r3s<3 goto 1
+ 98: cd 34 00 00 00 00 00 00 if r3s<r4 goto 0
+ a0: d5 30 00 01 00 00 00 03 if r3s<=3 goto 1
+ a8: dd 34 00 00 00 00 00 00 if r3s<=r4 goto 0
-#as: --EB
+#as: -EB -mdialect=normal
#source: jump.s
-#source: jump-pseudoc.s
-#objdump: -dr
+#objdump: -dr -M dec
#name: eBPF JUMP instructions, big endian
.*: +file format .*bpf.*
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M dec,pseudoc
#source: jump-pseudoc.s
-#dump: jump.dump
#name: eBPF JUMP instructions, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 goto 3
+ 8: 0f 11 00 00 00 00 00 00 r1\+=r1
+ 10: 15 03 01 00 03 00 00 00 if r3==3 goto 1
+ 18: 1d 43 00 00 00 00 00 00 if r3==r4 goto 0
+ 20: 35 03 fd ff 03 00 00 00 if r3>=3 goto -3
+ 28: 3d 43 fc ff 00 00 00 00 if r3>=r4 goto -4
+ 30: a5 03 01 00 03 00 00 00 if r3<3 goto 1
+ 38: ad 43 00 00 00 00 00 00 if r3<r4 goto 0
+ 40: b5 03 01 00 03 00 00 00 if r3<=3 goto 1
+ 48: bd 43 00 00 00 00 00 00 if r3<=r4 goto 0
+ 50: 45 03 01 00 03 00 00 00 if r3&3 goto 1
+ 58: 4d 43 00 00 00 00 00 00 if r3&r4 goto 0
+ 60: 55 03 01 00 03 00 00 00 if r3!=3 goto 1
+ 68: 5d 43 00 00 00 00 00 00 if r3!=r4 goto 0
+ 70: 65 03 01 00 03 00 00 00 if r3s>3 goto 1
+ 78: 6d 43 00 00 00 00 00 00 if r3s>r4 goto 0
+ 80: 75 03 01 00 03 00 00 00 if r3s>=3 goto 1
+ 88: 7d 43 00 00 00 00 00 00 if r3s>=r4 goto 0
+ 90: c5 03 01 00 03 00 00 00 if r3s<3 goto 1
+ 98: cd 43 00 00 00 00 00 00 if r3s<r4 goto 0
+ a0: d5 03 01 00 03 00 00 00 if r3s<=3 goto 1
+ a8: dd 43 00 00 00 00 00 00 if r3s<=r4 goto 0
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M dec
#source: jump.s
-#dump: jump.dump
#name: eBPF JUMP instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
+ 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
+ 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
+ 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
+ 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
+ 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
+ 40: b5 03 01 00 03 00 00 00 jle %r3,3,1
+ 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
+ 50: 45 03 01 00 03 00 00 00 jset %r3,3,1
+ 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
+ 60: 55 03 01 00 03 00 00 00 jne %r3,3,1
+ 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
+ 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
+ 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
+ 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
+ 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
+ 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
+ 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
+ a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
+ a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 05 00 03 00 00 00 00 00 ja 3
- 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
- 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
- 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
- 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
- 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
- 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
- 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
- 40: b5 03 01 00 03 00 00 00 jle %r3,3,1
- 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
- 50: 45 03 01 00 03 00 00 00 jset %r3,3,1
- 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
- 60: 55 03 01 00 03 00 00 00 jne %r3,3,1
- 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
- 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
- 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
- 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
- 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
- 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
- 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
- a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
- a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0
--- /dev/null
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M dec,pseudoc
+#source: jump32-pseudoc.s
+#name: eBPF JUMP32 instructions, pseudoc syntax, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 00 03 00 00 00 00 goto 3
+ 8: 0f 11 00 00 00 00 00 00 r1\+=r1
+ 10: 16 30 00 01 00 00 00 03 if w3==3 goto 1
+ 18: 1e 34 00 00 00 00 00 00 if w3==w4 goto 0
+ 20: 36 30 ff fd 00 00 00 03 if w3>=3 goto -3
+ 28: 3e 34 ff fc 00 00 00 00 if w3>=w4 goto -4
+ 30: a6 30 00 01 00 00 00 03 if w3<3 goto 1
+ 38: ae 34 00 00 00 00 00 00 if w3<w4 goto 0
+ 40: b6 30 00 01 00 00 00 03 if w3<=3 goto 1
+ 48: be 34 00 00 00 00 00 00 if w3<=w4 goto 0
+ 50: 46 30 00 01 00 00 00 03 if w3&3 goto 1
+ 58: 4e 34 00 00 00 00 00 00 if w3&w4 goto 0
+ 60: 56 30 00 01 00 00 00 03 if w3!=3 goto 1
+ 68: 5e 34 00 00 00 00 00 00 if w3!=w4 goto 0
+ 70: 66 30 00 01 00 00 00 03 if w3s>3 goto 1
+ 78: 6e 34 00 00 00 00 00 00 if w3s>w4 goto 0
+ 80: 76 30 00 01 00 00 00 03 if w3s>=3 goto 1
+ 88: 7e 34 00 00 00 00 00 00 if w3s>=w4 goto 0
+ 90: c6 30 00 01 00 00 00 03 if w3s<3 goto 1
+ 98: ce 34 00 00 00 00 00 00 if w3s<w4 goto 0
+ a0: d6 30 00 01 00 00 00 03 if w3s<=3 goto 1
+ a8: de 34 00 00 00 00 00 00 if w3s<=w4 goto 0
--- /dev/null
+#as: -EB -mdialect=normal
+#objdump: -dr -M dec
+#source: jump32.s
+#name: eBPF JUMP32 instructions, normal syntax, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 00 03 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 16 30 00 01 00 00 00 03 jeq32 %r3,3,1
+ 18: 1e 34 00 00 00 00 00 00 jeq32 %r3,%r4,0
+ 20: 36 30 ff fd 00 00 00 03 jge32 %r3,3,-3
+ 28: 3e 34 ff fc 00 00 00 00 jge32 %r3,%r4,-4
+ 30: a6 30 00 01 00 00 00 03 jlt32 %r3,3,1
+ 38: ae 34 00 00 00 00 00 00 jlt32 %r3,%r4,0
+ 40: b6 30 00 01 00 00 00 03 jle32 %r3,3,1
+ 48: be 34 00 00 00 00 00 00 jle32 %r3,%r4,0
+ 50: 46 30 00 01 00 00 00 03 jset32 %r3,3,1
+ 58: 4e 34 00 00 00 00 00 00 jset32 %r3,%r4,0
+ 60: 56 30 00 01 00 00 00 03 jne32 %r3,3,1
+ 68: 5e 34 00 00 00 00 00 00 jne32 %r3,%r4,0
+ 70: 66 30 00 01 00 00 00 03 jsgt32 %r3,3,1
+ 78: 6e 34 00 00 00 00 00 00 jsgt32 %r3,%r4,0
+ 80: 76 30 00 01 00 00 00 03 jsge32 %r3,3,1
+ 88: 7e 34 00 00 00 00 00 00 jsge32 %r3,%r4,0
+ 90: c6 30 00 01 00 00 00 03 jslt32 %r3,3,1
+ 98: ce 34 00 00 00 00 00 00 jslt32 %r3,%r4,0
+ a0: d6 30 00 01 00 00 00 03 jsle32 %r3,3,1
+ a8: de 34 00 00 00 00 00 00 jsle32 %r3,%r4,0
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M dec,pseudoc
#source: jump32-pseudoc.s
-#dump: jump32.dump
#name: eBPF JUMP32 instructions, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 goto 3
+ 8: 0f 11 00 00 00 00 00 00 r1\+=r1
+ 10: 16 03 01 00 03 00 00 00 if w3==3 goto 1
+ 18: 1e 43 00 00 00 00 00 00 if w3==w4 goto 0
+ 20: 36 03 fd ff 03 00 00 00 if w3>=3 goto -3
+ 28: 3e 43 fc ff 00 00 00 00 if w3>=w4 goto -4
+ 30: a6 03 01 00 03 00 00 00 if w3<3 goto 1
+ 38: ae 43 00 00 00 00 00 00 if w3<w4 goto 0
+ 40: b6 03 01 00 03 00 00 00 if w3<=3 goto 1
+ 48: be 43 00 00 00 00 00 00 if w3<=w4 goto 0
+ 50: 46 03 01 00 03 00 00 00 if w3&3 goto 1
+ 58: 4e 43 00 00 00 00 00 00 if w3&w4 goto 0
+ 60: 56 03 01 00 03 00 00 00 if w3!=3 goto 1
+ 68: 5e 43 00 00 00 00 00 00 if w3!=w4 goto 0
+ 70: 66 03 01 00 03 00 00 00 if w3s>3 goto 1
+ 78: 6e 43 00 00 00 00 00 00 if w3s>w4 goto 0
+ 80: 76 03 01 00 03 00 00 00 if w3s>=3 goto 1
+ 88: 7e 43 00 00 00 00 00 00 if w3s>=w4 goto 0
+ 90: c6 03 01 00 03 00 00 00 if w3s<3 goto 1
+ 98: ce 43 00 00 00 00 00 00 if w3s<w4 goto 0
+ a0: d6 03 01 00 03 00 00 00 if w3s<=3 goto 1
+ a8: de 43 00 00 00 00 00 00 if w3s<=w4 goto 0
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M dec
#source: jump32.s
-#dump: jump32.dump
#name: eBPF JUMP32 instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
+ 18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
+ 20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
+ 28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
+ 30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
+ 38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
+ 40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
+ 48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
+ 50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
+ 58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
+ 60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
+ 68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
+ 70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
+ 78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
+ 80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
+ 88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
+ 90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
+ 98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
+ a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
+ a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 05 00 03 00 00 00 00 00 ja 3
- 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
- 10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
- 18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
- 20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
- 28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
- 30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
- 38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
- 40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
- 48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
- 50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
- 58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
- 60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
- 68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
- 70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
- 78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
- 80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
- 88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
- 90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
- 98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
- a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
- a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0
-#as: --EB
+#as: -EB -mdialect=pseudoc
#source: lddw-pseudoc.s
-#objdump: -dr
-#dump: lddw-be.dump
+#objdump: -dr -M hex,pseudoc
#name: eBPF LDDW, big-endian, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 30 00 00 00 00 00 01 r3=0x1 ll
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 40 00 00 de ad be ef r4=0xdeadbeef ll
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 50 00 00 55 66 77 88 r5=0x1122334455667788 ll
+ 28: 00 00 00 00 11 22 33 44
+ 30: 18 60 00 00 ff ff ff fe r6=0xfffffffffffffffe ll
+ 38: 00 00 00 00 ff ff ff ff
-#as: --EB
+#as: -EB -mdialect=normal
#source: lddw.s
-#objdump: -dr
-#dump: lddw-be.dump
+#objdump: -dr -M hex
#name: eBPF LDDW, big-endian, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 30 00 00 00 00 00 01 lddw %r3,0x1
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
+ 28: 00 00 00 00 11 22 33 44
+ 30: 18 60 00 00 ff ff ff fe lddw %r6,0xfffffffffffffffe
+ 38: 00 00 00 00 ff ff ff ff
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 18 30 00 00 00 00 00 01 lddw %r3,1
- 8: 00 00 00 00 00 00 00 00
- 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
- 18: 00 00 00 00 00 00 00 00
- 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
- 28: 00 00 00 00 11 22 33 44
- 30: 18 60 00 00 ff ff ff fe lddw %r6,-2
- 38: 00 00 00 00 ff ff ff ff
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
#source: lddw-pseudoc.s
-#dump: lddw.dump
#name: eBPF LDDW, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 03 00 00 01 00 00 00 r3=0x1 ll
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 04 00 00 ef be ad de r4=0xdeadbeef ll
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 05 00 00 88 77 66 55 r5=0x1122334455667788 ll
+ 28: 00 00 00 00 44 33 22 11
+ 30: 18 06 00 00 fe ff ff ff r6=0xfffffffffffffffe ll
+ 38: 00 00 00 00 ff ff ff ff
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
#source: lddw.s
-#dump: lddw.dump
#name: eBPF LDDW, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 03 00 00 01 00 00 00 lddw %r3,0x1
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
+ 28: 00 00 00 00 44 33 22 11
+ 30: 18 06 00 00 fe ff ff ff lddw %r6,0xfffffffffffffffe
+ 38: 00 00 00 00 ff ff ff ff
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 18 03 00 00 01 00 00 00 lddw %r3,1
- 8: 00 00 00 00 00 00 00 00
- 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
- 18: 00 00 00 00 00 00 00 00
- 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
- 28: 00 00 00 00 44 33 22 11
- 30: 18 06 00 00 fe ff ff ff lddw %r6,-2
- 38: 00 00 00 00 ff ff ff ff
--- /dev/null
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
+#source: mem-pseudoc.s
+#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 00 00 00 00 00 be ef r0=\*\(u32\*\)skb\[0xbeef\]
+ 8: 28 00 00 00 00 00 be ef r0=\*\(u16\*\)skb\[0xbeef\]
+ 10: 30 00 00 00 00 00 be ef r0=\*\(u8\*\)skb\[0xbeef\]
+ 18: 38 00 00 00 00 00 be ef r0=\*\(u64\*\)skb\[0xbeef\]
+ 20: 40 03 00 00 00 00 be ef r0=\*\(u32\*\)skb\[r3\+0xbeef\]
+ 28: 48 05 00 00 00 00 be ef r0=\*\(u16\*\)skb\[r5\+0xbeef\]
+ 30: 50 07 00 00 00 00 be ef r0=\*\(u8\*\)skb\[r7\+0xbeef\]
+ 38: 58 09 00 00 00 00 be ef r0=\*\(u64\*\)skb\[r9\+0xbeef\]
+ 40: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
+ 48: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
+ 50: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
+ 58: 79 21 ff fe 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\)
+ 60: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
+ 68: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
+ 70: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
+ 78: 7b 12 ff fe 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2
+ 80: 72 10 7e ef 11 22 33 44 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344
+ 88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
+ 90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
+ 98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344
-#as: --EB
+#as: -EB -mdialect=normal
#source: mem.s
-#source: mem-pseudoc.s
-#objdump: -dr
+#objdump: -dr -M hex
#name: eBPF MEM instructions, modulus lddw, big endian
.*: +file format .*bpf.*
40: 61 21 7e ef 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
48: 69 21 7e ef 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
50: 71 21 7e ef 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
- 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
+ 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\]
60: 63 12 7e ef 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
68: 6b 12 7e ef 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
70: 73 12 7e ef 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
- 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+-2\],%r2
+ 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2
80: 72 10 7e ef 11 22 33 44 stb \[%r1\+0x7eef\],0x11223344
88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344
90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344
- 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+-2\],0x11223344
+ 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
#source: mem-pseudoc.s
-#dump: mem.dump
#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 00 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[0xbeef\]
+ 8: 28 00 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[0xbeef\]
+ 10: 30 00 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[0xbeef\]
+ 18: 38 00 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[0xbeef\]
+ 20: 40 30 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[r3\+0xbeef\]
+ 28: 48 50 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[r5\+0xbeef\]
+ 30: 50 70 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[r7\+0xbeef\]
+ 38: 58 90 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[r9\+0xbeef\]
+ 40: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
+ 48: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
+ 50: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
+ 58: 79 12 fe ff 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\)
+ 60: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
+ 68: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
+ 70: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
+ 78: 7b 21 fe ff 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2
+ 80: 72 01 ef 7e 44 33 22 11 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344
+ 88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
+ 90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
+ 98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344
*(u16 *)(r1 + 32495) = r2
*(u8 *)(r1 + 32495) = r2
*(u64 *)(r1 - 2) = r2
- stb [%r1+0x7eef], 0x11223344
- sth [%r1+0x7eef], 0x11223344
- stw [%r1+0x7eef], 0x11223344
- stdw [%r1+-2], 0x11223344
+ *(u8 *)(r1 + 0x7eef) = 0x11223344
+ *(u16 *)(r1 + 0x7eef) = 0x11223344
+ *(u32 *)(r1 + 0x7eef) = 0x11223344
+ *(u64 *)(r1 + -2) = 0x11223344
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
#source: mem.s
-#dump: mem.dump
#name: eBPF MEM instructions, modulus lddw, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
+ 8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
+ 10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
+ 18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
+ 20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
+ 28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
+ 30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
+ 38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef
+ 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
+ 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
+ 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
+ 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\]
+ 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
+ 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
+ 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
+ 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2
+ 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
+ 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
+ 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
+ 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344
+++ /dev/null
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <.text>:
- 0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
- 8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
- 10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
- 18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
- 20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
- 28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
- 30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
- 38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef
- 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
- 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
- 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
- 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
- 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
- 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
- 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
- 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2
- 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
- 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
- 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
- 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344
stb [%r1+0x7eef], 0x11223344
sth [%r1+0x7eef], 0x11223344
stw [%r1+0x7eef], 0x11223344
- stdw [%r1+-2], 0x11223344
+ stdw [%r1-2], 0x11223344
+++ /dev/null
-#as: --EB
-#objdump: -dr
-#source: pseudoc-normal.s
-#name: eBPF clang (pseudo-C)/gas (normal) instructions
-
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <beg>:
- 0: 07 10 00 00 00 00 00 aa add %r1,0xaa
- 8: 07 10 00 00 00 00 00 aa add %r1,0xaa
- 10: 0f 12 00 00 00 00 00 00 add %r1,%r2
- 18: 0f 12 00 00 00 00 00 00 add %r1,%r2
- 20: 17 10 00 00 00 00 00 aa sub %r1,0xaa
- 28: 17 10 00 00 00 00 00 aa sub %r1,0xaa
- 30: 1f 12 00 00 00 00 00 00 sub %r1,%r2
- 38: 1f 12 00 00 00 00 00 00 sub %r1,%r2
- 40: 27 10 00 00 00 00 00 aa mul %r1,0xaa
- 48: 27 10 00 00 00 00 00 aa mul %r1,0xaa
- 50: 2f 12 00 00 00 00 00 00 mul %r1,%r2
- 58: 2f 12 00 00 00 00 00 00 mul %r1,%r2
- 60: 37 10 00 00 00 00 00 aa div %r1,0xaa
- 68: 37 10 00 00 00 00 00 aa div %r1,0xaa
- 70: 3f 12 00 00 00 00 00 00 div %r1,%r2
- 78: 3f 12 00 00 00 00 00 00 div %r1,%r2
- 80: 47 10 00 00 00 00 00 aa or %r1,0xaa
- 88: 47 10 00 00 00 00 00 aa or %r1,0xaa
- 90: 4f 12 00 00 00 00 00 00 or %r1,%r2
- 98: 4f 12 00 00 00 00 00 00 or %r1,%r2
- a0: 57 10 00 00 00 00 00 aa and %r1,0xaa
- a8: 57 10 00 00 00 00 00 aa and %r1,0xaa
- b0: 5f 12 00 00 00 00 00 00 and %r1,%r2
- b8: 5f 12 00 00 00 00 00 00 and %r1,%r2
- c0: 67 10 00 00 00 00 00 aa lsh %r1,0xaa
- c8: 67 10 00 00 00 00 00 aa lsh %r1,0xaa
- d0: 6f 12 00 00 00 00 00 00 lsh %r1,%r2
- d8: 6f 12 00 00 00 00 00 00 lsh %r1,%r2
- e0: 77 10 00 00 00 00 00 aa rsh %r1,0xaa
- e8: 77 10 00 00 00 00 00 aa rsh %r1,0xaa
- f0: 7f 12 00 00 00 00 00 00 rsh %r1,%r2
- f8: 7f 12 00 00 00 00 00 00 rsh %r1,%r2
- 100: a7 10 00 00 00 00 00 aa xor %r1,0xaa
- 108: a7 10 00 00 00 00 00 aa xor %r1,0xaa
- 110: af 12 00 00 00 00 00 00 xor %r1,%r2
- 118: af 12 00 00 00 00 00 00 xor %r1,%r2
- 120: b7 10 00 00 00 00 00 aa mov %r1,0xaa
- 128: b7 10 00 00 00 00 00 aa mov %r1,0xaa
- 130: bf 12 00 00 00 00 00 00 mov %r1,%r2
- 138: bf 12 00 00 00 00 00 00 mov %r1,%r2
- 140: c7 10 00 00 00 00 00 aa arsh %r1,0xaa
- 148: c7 10 00 00 00 00 00 aa arsh %r1,0xaa
- 150: cf 12 00 00 00 00 00 00 arsh %r1,%r2
- 158: cf 12 00 00 00 00 00 00 arsh %r1,%r2
- 160: 87 10 00 00 00 00 00 00 neg %r1
- 168: 87 10 00 00 00 00 00 00 neg %r1
- 170: 04 10 00 00 00 00 00 aa add32 %r1,0xaa
- 178: 04 10 00 00 00 00 00 aa add32 %r1,0xaa
- 180: 0c 12 00 00 00 00 00 00 add32 %r1,%r2
- 188: 0c 12 00 00 00 00 00 00 add32 %r1,%r2
- 190: 14 10 00 00 00 00 00 aa sub32 %r1,0xaa
- 198: 14 10 00 00 00 00 00 aa sub32 %r1,0xaa
- 1a0: 1c 12 00 00 00 00 00 00 sub32 %r1,%r2
- 1a8: 1c 12 00 00 00 00 00 00 sub32 %r1,%r2
- 1b0: 24 10 00 00 00 00 00 aa mul32 %r1,0xaa
- 1b8: 24 10 00 00 00 00 00 aa mul32 %r1,0xaa
- 1c0: 2c 12 00 00 00 00 00 00 mul32 %r1,%r2
- 1c8: 2c 12 00 00 00 00 00 00 mul32 %r1,%r2
- 1d0: 34 10 00 00 00 00 00 aa div32 %r1,0xaa
- 1d8: 34 10 00 00 00 00 00 aa div32 %r1,0xaa
- 1e0: 3c 12 00 00 00 00 00 00 div32 %r1,%r2
- 1e8: 3c 12 00 00 00 00 00 00 div32 %r1,%r2
- 1f0: 44 10 00 00 00 00 00 aa or32 %r1,0xaa
- 1f8: 44 10 00 00 00 00 00 aa or32 %r1,0xaa
- 200: 4c 12 00 00 00 00 00 00 or32 %r1,%r2
- 208: 4c 12 00 00 00 00 00 00 or32 %r1,%r2
- 210: 54 10 00 00 00 00 00 aa and32 %r1,0xaa
- 218: 54 10 00 00 00 00 00 aa and32 %r1,0xaa
- 220: 5c 12 00 00 00 00 00 00 and32 %r1,%r2
- 228: 5c 12 00 00 00 00 00 00 and32 %r1,%r2
- 230: 64 10 00 00 00 00 00 aa lsh32 %r1,0xaa
- 238: 64 10 00 00 00 00 00 aa lsh32 %r1,0xaa
- 240: 6c 12 00 00 00 00 00 00 lsh32 %r1,%r2
- 248: 6c 12 00 00 00 00 00 00 lsh32 %r1,%r2
- 250: 74 10 00 00 00 00 00 aa rsh32 %r1,0xaa
- 258: 74 10 00 00 00 00 00 aa rsh32 %r1,0xaa
- 260: 7c 12 00 00 00 00 00 00 rsh32 %r1,%r2
- 268: 7c 12 00 00 00 00 00 00 rsh32 %r1,%r2
- 270: a4 10 00 00 00 00 00 aa xor32 %r1,0xaa
- 278: a4 10 00 00 00 00 00 aa xor32 %r1,0xaa
- 280: ac 12 00 00 00 00 00 00 xor32 %r1,%r2
- 288: ac 12 00 00 00 00 00 00 xor32 %r1,%r2
- 290: b4 10 00 00 00 00 00 aa mov32 %r1,0xaa
- 298: b4 10 00 00 00 00 00 aa mov32 %r1,0xaa
- 2a0: bc 12 00 00 00 00 00 00 mov32 %r1,%r2
- 2a8: bc 12 00 00 00 00 00 00 mov32 %r1,%r2
- 2b0: c4 10 00 00 00 00 00 aa arsh32 %r1,0xaa
- 2b8: c4 10 00 00 00 00 00 aa arsh32 %r1,0xaa
- 2c0: cc 12 00 00 00 00 00 00 arsh32 %r1,%r2
- 2c8: cc 12 00 00 00 00 00 00 arsh32 %r1,%r2
- 2d0: 84 10 00 00 00 00 00 00 neg32 %r1
- 2d8: 84 10 00 00 00 00 00 00 neg32 %r1
- 2e0: d4 10 00 00 00 00 00 10 endle %r1,16
- 2e8: d4 10 00 00 00 00 00 10 endle %r1,16
- 2f0: d4 10 00 00 00 00 00 20 endle %r1,32
- 2f8: d4 10 00 00 00 00 00 20 endle %r1,32
- 300: d4 10 00 00 00 00 00 40 endle %r1,64
- 308: d4 10 00 00 00 00 00 40 endle %r1,64
- 310: dc 10 00 00 00 00 00 10 endbe %r1,16
- 318: dc 10 00 00 00 00 00 10 endbe %r1,16
- 320: dc 10 00 00 00 00 00 20 endbe %r1,32
- 328: dc 10 00 00 00 00 00 20 endbe %r1,32
- 330: dc 10 00 00 00 00 00 40 endbe %r1,64
- 338: dc 10 00 00 00 00 00 40 endbe %r1,64
- 340: 71 12 00 aa 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
- 348: 71 12 00 aa 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
- 350: 69 12 00 aa 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
- 358: 69 12 00 aa 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
- 360: 61 12 00 aa 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
- 368: 61 12 00 aa 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
- 370: 79 12 00 aa 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
- 378: 79 12 00 aa 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
- 380: 73 12 00 aa 00 00 00 00 stxb \[%r1\+0xaa\],%r2
- 388: 73 12 00 aa 00 00 00 00 stxb \[%r1\+0xaa\],%r2
- 390: 6b 12 00 aa 00 00 00 00 stxh \[%r1\+0xaa\],%r2
- 398: 6b 12 00 aa 00 00 00 00 stxh \[%r1\+0xaa\],%r2
- 3a0: 63 12 00 aa 00 00 00 00 stxw \[%r1\+0xaa\],%r2
- 3a8: 63 12 00 aa 00 00 00 00 stxw \[%r1\+0xaa\],%r2
- 3b0: 7b 12 00 aa 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
- 3b8: 7b 12 00 aa 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
- 3c0: 05 00 00 bb 00 00 00 00 ja 187
- 3c8: 05 00 00 bb 00 00 00 00 ja 187
- 3d0: 15 10 00 bb 00 00 00 aa jeq %r1,0xaa,187
- 3d8: 15 10 00 bb 00 00 00 aa jeq %r1,0xaa,187
- 3e0: 1d 12 00 bb 00 00 00 00 jeq %r1,%r2,187
- 3e8: 1d 12 00 bb 00 00 00 00 jeq %r1,%r2,187
- 3f0: 25 10 00 bb 00 00 00 aa jgt %r1,0xaa,187
- 3f8: 25 10 00 bb 00 00 00 aa jgt %r1,0xaa,187
- 400: 2d 12 00 bb 00 00 00 00 jgt %r1,%r2,187
- 408: 2d 12 00 bb 00 00 00 00 jgt %r1,%r2,187
- 410: 35 10 00 bb 00 00 00 aa jge %r1,0xaa,187
- 418: 35 10 00 bb 00 00 00 aa jge %r1,0xaa,187
- 420: 3d 12 00 bb 00 00 00 00 jge %r1,%r2,187
- 428: 3d 12 00 bb 00 00 00 00 jge %r1,%r2,187
- 430: a5 10 00 bb 00 00 00 aa jlt %r1,0xaa,187
- 438: a5 10 00 bb 00 00 00 aa jlt %r1,0xaa,187
- 440: ad 12 00 bb 00 00 00 00 jlt %r1,%r2,187
- 448: ad 12 00 bb 00 00 00 00 jlt %r1,%r2,187
- 450: b5 10 00 bb 00 00 00 aa jle %r1,0xaa,187
- 458: b5 10 00 bb 00 00 00 aa jle %r1,0xaa,187
- 460: bd 12 00 bb 00 00 00 00 jle %r1,%r2,187
- 468: bd 12 00 bb 00 00 00 00 jle %r1,%r2,187
- 470: 45 10 00 bb 00 00 00 aa jset %r1,0xaa,187
- 478: 45 10 00 bb 00 00 00 aa jset %r1,0xaa,187
- 480: 4d 12 00 bb 00 00 00 00 jset %r1,%r2,187
- 488: 4d 12 00 bb 00 00 00 00 jset %r1,%r2,187
- 490: 55 10 00 bb 00 00 00 aa jne %r1,0xaa,187
- 498: 55 10 00 bb 00 00 00 aa jne %r1,0xaa,187
- 4a0: 5d 12 00 bb 00 00 00 00 jne %r1,%r2,187
- 4a8: 5d 12 00 bb 00 00 00 00 jne %r1,%r2,187
- 4b0: 65 10 00 bb 00 00 00 aa jsgt %r1,0xaa,187
- 4b8: 65 10 00 bb 00 00 00 aa jsgt %r1,0xaa,187
- 4c0: 6d 12 00 bb 00 00 00 00 jsgt %r1,%r2,187
- 4c8: 6d 12 00 bb 00 00 00 00 jsgt %r1,%r2,187
- 4d0: 75 10 00 bb 00 00 00 aa jsge %r1,0xaa,187
- 4d8: 75 10 00 bb 00 00 00 aa jsge %r1,0xaa,187
- 4e0: 7d 12 00 bb 00 00 00 00 jsge %r1,%r2,187
- 4e8: 7d 12 00 bb 00 00 00 00 jsge %r1,%r2,187
- 4f0: c5 10 00 bb 00 00 00 aa jslt %r1,0xaa,187
- 4f8: c5 10 00 bb 00 00 00 aa jslt %r1,0xaa,187
- 500: cd 12 00 bb 00 00 00 00 jslt %r1,%r2,187
- 508: cd 12 00 bb 00 00 00 00 jslt %r1,%r2,187
- 510: d5 10 00 bb 00 00 00 aa jsle %r1,0xaa,187
- 518: d5 10 00 bb 00 00 00 aa jsle %r1,0xaa,187
- 520: dd 12 00 bb 00 00 00 00 jsle %r1,%r2,187
- 528: dd 12 00 bb 00 00 00 00 jsle %r1,%r2,187
- 530: 85 00 00 00 00 00 00 aa call 170
- 538: 85 00 00 00 00 00 00 aa call 170
- 540: 95 00 00 00 00 00 00 00 exit
- 548: 95 00 00 00 00 00 00 00 exit
- 550: b7 60 00 00 00 00 06 20 mov %r6,0x620
- 558: 95 00 00 00 00 00 00 00 exit
- 560: 20 00 00 00 00 00 00 aa ldabsw 0xaa
- 568: 20 00 00 00 00 00 00 aa ldabsw 0xaa
- 570: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
- 578: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
- 580: 20 00 00 00 00 00 00 aa ldabsw 0xaa
- 588: 20 00 00 00 00 00 00 aa ldabsw 0xaa
- 590: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
- 598: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
- 5a0: 18 30 00 00 00 00 00 01 lddw %r3,1
- 5a8: 00 00 00 00 00 00 00 00
- 5b0: 18 30 00 00 00 00 00 01 lddw %r3,1
- 5b8: 00 00 00 00 00 00 00 00
- 5c0: 18 40 00 00 ee ff 77 88 lddw %r4,-6144092013047351416
- 5c8: 00 00 00 00 aa bb cc dd
- 5d0: 18 40 00 00 ee ff 77 88 lddw %r4,-6144092013047351416
- 5d8: 00 00 00 00 aa bb cc dd
- 5e0: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
- 5e8: 00 00 00 00 11 22 33 44
- 5f0: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
- 5f8: 00 00 00 00 11 22 33 44
- 600: 18 60 00 00 00 00 06 20 lddw %r6,0x620
- 608: 00 00 00 00 00 00 00 00
- 600: R_BPF_64_64 .text
- 610: 18 60 00 00 00 00 06 20 lddw %r6,0x620
- 618: 00 00 00 00 00 00 00 00
- 610: R_BPF_64_64 .text
-
-0000000000000620 <main>:
- 620: c3 12 00 aa 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
- 628: c3 12 00 aa 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
- 630: db 12 00 aa 00 00 00 00 xadddw \[%r1\+0xaa\],%r2
- 638: db 12 00 aa 00 00 00 00 xadddw \[%r1\+0xaa\],%r2
+++ /dev/null
-#as: --EL
-#objdump: -dr
-#source: pseudoc-normal.s
-#name: eBPF clang (pseudo-C)/gas (normal) instructions
-
-.*: +file format .*bpf.*
-
-Disassembly of section .text:
-
-0+ <beg>:
- 0: 07 01 00 00 aa 00 00 00 add %r1,0xaa
- 8: 07 01 00 00 aa 00 00 00 add %r1,0xaa
- 10: 0f 21 00 00 00 00 00 00 add %r1,%r2
- 18: 0f 21 00 00 00 00 00 00 add %r1,%r2
- 20: 17 01 00 00 aa 00 00 00 sub %r1,0xaa
- 28: 17 01 00 00 aa 00 00 00 sub %r1,0xaa
- 30: 1f 21 00 00 00 00 00 00 sub %r1,%r2
- 38: 1f 21 00 00 00 00 00 00 sub %r1,%r2
- 40: 27 01 00 00 aa 00 00 00 mul %r1,0xaa
- 48: 27 01 00 00 aa 00 00 00 mul %r1,0xaa
- 50: 2f 21 00 00 00 00 00 00 mul %r1,%r2
- 58: 2f 21 00 00 00 00 00 00 mul %r1,%r2
- 60: 37 01 00 00 aa 00 00 00 div %r1,0xaa
- 68: 37 01 00 00 aa 00 00 00 div %r1,0xaa
- 70: 3f 21 00 00 00 00 00 00 div %r1,%r2
- 78: 3f 21 00 00 00 00 00 00 div %r1,%r2
- 80: 47 01 00 00 aa 00 00 00 or %r1,0xaa
- 88: 47 01 00 00 aa 00 00 00 or %r1,0xaa
- 90: 4f 21 00 00 00 00 00 00 or %r1,%r2
- 98: 4f 21 00 00 00 00 00 00 or %r1,%r2
- a0: 57 01 00 00 aa 00 00 00 and %r1,0xaa
- a8: 57 01 00 00 aa 00 00 00 and %r1,0xaa
- b0: 5f 21 00 00 00 00 00 00 and %r1,%r2
- b8: 5f 21 00 00 00 00 00 00 and %r1,%r2
- c0: 67 01 00 00 aa 00 00 00 lsh %r1,0xaa
- c8: 67 01 00 00 aa 00 00 00 lsh %r1,0xaa
- d0: 6f 21 00 00 00 00 00 00 lsh %r1,%r2
- d8: 6f 21 00 00 00 00 00 00 lsh %r1,%r2
- e0: 77 01 00 00 aa 00 00 00 rsh %r1,0xaa
- e8: 77 01 00 00 aa 00 00 00 rsh %r1,0xaa
- f0: 7f 21 00 00 00 00 00 00 rsh %r1,%r2
- f8: 7f 21 00 00 00 00 00 00 rsh %r1,%r2
- 100: a7 01 00 00 aa 00 00 00 xor %r1,0xaa
- 108: a7 01 00 00 aa 00 00 00 xor %r1,0xaa
- 110: af 21 00 00 00 00 00 00 xor %r1,%r2
- 118: af 21 00 00 00 00 00 00 xor %r1,%r2
- 120: b7 01 00 00 aa 00 00 00 mov %r1,0xaa
- 128: b7 01 00 00 aa 00 00 00 mov %r1,0xaa
- 130: bf 21 00 00 00 00 00 00 mov %r1,%r2
- 138: bf 21 00 00 00 00 00 00 mov %r1,%r2
- 140: c7 01 00 00 aa 00 00 00 arsh %r1,0xaa
- 148: c7 01 00 00 aa 00 00 00 arsh %r1,0xaa
- 150: cf 21 00 00 00 00 00 00 arsh %r1,%r2
- 158: cf 21 00 00 00 00 00 00 arsh %r1,%r2
- 160: 87 01 00 00 00 00 00 00 neg %r1
- 168: 87 01 00 00 00 00 00 00 neg %r1
- 170: 04 01 00 00 aa 00 00 00 add32 %r1,0xaa
- 178: 04 01 00 00 aa 00 00 00 add32 %r1,0xaa
- 180: 0c 21 00 00 00 00 00 00 add32 %r1,%r2
- 188: 0c 21 00 00 00 00 00 00 add32 %r1,%r2
- 190: 14 01 00 00 aa 00 00 00 sub32 %r1,0xaa
- 198: 14 01 00 00 aa 00 00 00 sub32 %r1,0xaa
- 1a0: 1c 21 00 00 00 00 00 00 sub32 %r1,%r2
- 1a8: 1c 21 00 00 00 00 00 00 sub32 %r1,%r2
- 1b0: 24 01 00 00 aa 00 00 00 mul32 %r1,0xaa
- 1b8: 24 01 00 00 aa 00 00 00 mul32 %r1,0xaa
- 1c0: 2c 21 00 00 00 00 00 00 mul32 %r1,%r2
- 1c8: 2c 21 00 00 00 00 00 00 mul32 %r1,%r2
- 1d0: 34 01 00 00 aa 00 00 00 div32 %r1,0xaa
- 1d8: 34 01 00 00 aa 00 00 00 div32 %r1,0xaa
- 1e0: 3c 21 00 00 00 00 00 00 div32 %r1,%r2
- 1e8: 3c 21 00 00 00 00 00 00 div32 %r1,%r2
- 1f0: 44 01 00 00 aa 00 00 00 or32 %r1,0xaa
- 1f8: 44 01 00 00 aa 00 00 00 or32 %r1,0xaa
- 200: 4c 21 00 00 00 00 00 00 or32 %r1,%r2
- 208: 4c 21 00 00 00 00 00 00 or32 %r1,%r2
- 210: 54 01 00 00 aa 00 00 00 and32 %r1,0xaa
- 218: 54 01 00 00 aa 00 00 00 and32 %r1,0xaa
- 220: 5c 21 00 00 00 00 00 00 and32 %r1,%r2
- 228: 5c 21 00 00 00 00 00 00 and32 %r1,%r2
- 230: 64 01 00 00 aa 00 00 00 lsh32 %r1,0xaa
- 238: 64 01 00 00 aa 00 00 00 lsh32 %r1,0xaa
- 240: 6c 21 00 00 00 00 00 00 lsh32 %r1,%r2
- 248: 6c 21 00 00 00 00 00 00 lsh32 %r1,%r2
- 250: 74 01 00 00 aa 00 00 00 rsh32 %r1,0xaa
- 258: 74 01 00 00 aa 00 00 00 rsh32 %r1,0xaa
- 260: 7c 21 00 00 00 00 00 00 rsh32 %r1,%r2
- 268: 7c 21 00 00 00 00 00 00 rsh32 %r1,%r2
- 270: a4 01 00 00 aa 00 00 00 xor32 %r1,0xaa
- 278: a4 01 00 00 aa 00 00 00 xor32 %r1,0xaa
- 280: ac 21 00 00 00 00 00 00 xor32 %r1,%r2
- 288: ac 21 00 00 00 00 00 00 xor32 %r1,%r2
- 290: b4 01 00 00 aa 00 00 00 mov32 %r1,0xaa
- 298: b4 01 00 00 aa 00 00 00 mov32 %r1,0xaa
- 2a0: bc 21 00 00 00 00 00 00 mov32 %r1,%r2
- 2a8: bc 21 00 00 00 00 00 00 mov32 %r1,%r2
- 2b0: c4 01 00 00 aa 00 00 00 arsh32 %r1,0xaa
- 2b8: c4 01 00 00 aa 00 00 00 arsh32 %r1,0xaa
- 2c0: cc 21 00 00 00 00 00 00 arsh32 %r1,%r2
- 2c8: cc 21 00 00 00 00 00 00 arsh32 %r1,%r2
- 2d0: 84 01 00 00 00 00 00 00 neg32 %r1
- 2d8: 84 01 00 00 00 00 00 00 neg32 %r1
- 2e0: d4 01 00 00 10 00 00 00 endle %r1,16
- 2e8: d4 01 00 00 10 00 00 00 endle %r1,16
- 2f0: d4 01 00 00 20 00 00 00 endle %r1,32
- 2f8: d4 01 00 00 20 00 00 00 endle %r1,32
- 300: d4 01 00 00 40 00 00 00 endle %r1,64
- 308: d4 01 00 00 40 00 00 00 endle %r1,64
- 310: dc 01 00 00 10 00 00 00 endbe %r1,16
- 318: dc 01 00 00 10 00 00 00 endbe %r1,16
- 320: dc 01 00 00 20 00 00 00 endbe %r1,32
- 328: dc 01 00 00 20 00 00 00 endbe %r1,32
- 330: dc 01 00 00 40 00 00 00 endbe %r1,64
- 338: dc 01 00 00 40 00 00 00 endbe %r1,64
- 340: 71 21 aa 00 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
- 348: 71 21 aa 00 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
- 350: 69 21 aa 00 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
- 358: 69 21 aa 00 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
- 360: 61 21 aa 00 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
- 368: 61 21 aa 00 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
- 370: 79 21 aa 00 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
- 378: 79 21 aa 00 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
- 380: 73 21 aa 00 00 00 00 00 stxb \[%r1\+0xaa\],%r2
- 388: 73 21 aa 00 00 00 00 00 stxb \[%r1\+0xaa\],%r2
- 390: 6b 21 aa 00 00 00 00 00 stxh \[%r1\+0xaa\],%r2
- 398: 6b 21 aa 00 00 00 00 00 stxh \[%r1\+0xaa\],%r2
- 3a0: 63 21 aa 00 00 00 00 00 stxw \[%r1\+0xaa\],%r2
- 3a8: 63 21 aa 00 00 00 00 00 stxw \[%r1\+0xaa\],%r2
- 3b0: 7b 21 aa 00 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
- 3b8: 7b 21 aa 00 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
- 3c0: 05 00 bb 00 00 00 00 00 ja 187
- 3c8: 05 00 bb 00 00 00 00 00 ja 187
- 3d0: 15 01 bb 00 aa 00 00 00 jeq %r1,0xaa,187
- 3d8: 15 01 bb 00 aa 00 00 00 jeq %r1,0xaa,187
- 3e0: 1d 21 bb 00 00 00 00 00 jeq %r1,%r2,187
- 3e8: 1d 21 bb 00 00 00 00 00 jeq %r1,%r2,187
- 3f0: 25 01 bb 00 aa 00 00 00 jgt %r1,0xaa,187
- 3f8: 25 01 bb 00 aa 00 00 00 jgt %r1,0xaa,187
- 400: 2d 21 bb 00 00 00 00 00 jgt %r1,%r2,187
- 408: 2d 21 bb 00 00 00 00 00 jgt %r1,%r2,187
- 410: 35 01 bb 00 aa 00 00 00 jge %r1,0xaa,187
- 418: 35 01 bb 00 aa 00 00 00 jge %r1,0xaa,187
- 420: 3d 21 bb 00 00 00 00 00 jge %r1,%r2,187
- 428: 3d 21 bb 00 00 00 00 00 jge %r1,%r2,187
- 430: a5 01 bb 00 aa 00 00 00 jlt %r1,0xaa,187
- 438: a5 01 bb 00 aa 00 00 00 jlt %r1,0xaa,187
- 440: ad 21 bb 00 00 00 00 00 jlt %r1,%r2,187
- 448: ad 21 bb 00 00 00 00 00 jlt %r1,%r2,187
- 450: b5 01 bb 00 aa 00 00 00 jle %r1,0xaa,187
- 458: b5 01 bb 00 aa 00 00 00 jle %r1,0xaa,187
- 460: bd 21 bb 00 00 00 00 00 jle %r1,%r2,187
- 468: bd 21 bb 00 00 00 00 00 jle %r1,%r2,187
- 470: 45 01 bb 00 aa 00 00 00 jset %r1,0xaa,187
- 478: 45 01 bb 00 aa 00 00 00 jset %r1,0xaa,187
- 480: 4d 21 bb 00 00 00 00 00 jset %r1,%r2,187
- 488: 4d 21 bb 00 00 00 00 00 jset %r1,%r2,187
- 490: 55 01 bb 00 aa 00 00 00 jne %r1,0xaa,187
- 498: 55 01 bb 00 aa 00 00 00 jne %r1,0xaa,187
- 4a0: 5d 21 bb 00 00 00 00 00 jne %r1,%r2,187
- 4a8: 5d 21 bb 00 00 00 00 00 jne %r1,%r2,187
- 4b0: 65 01 bb 00 aa 00 00 00 jsgt %r1,0xaa,187
- 4b8: 65 01 bb 00 aa 00 00 00 jsgt %r1,0xaa,187
- 4c0: 6d 21 bb 00 00 00 00 00 jsgt %r1,%r2,187
- 4c8: 6d 21 bb 00 00 00 00 00 jsgt %r1,%r2,187
- 4d0: 75 01 bb 00 aa 00 00 00 jsge %r1,0xaa,187
- 4d8: 75 01 bb 00 aa 00 00 00 jsge %r1,0xaa,187
- 4e0: 7d 21 bb 00 00 00 00 00 jsge %r1,%r2,187
- 4e8: 7d 21 bb 00 00 00 00 00 jsge %r1,%r2,187
- 4f0: c5 01 bb 00 aa 00 00 00 jslt %r1,0xaa,187
- 4f8: c5 01 bb 00 aa 00 00 00 jslt %r1,0xaa,187
- 500: cd 21 bb 00 00 00 00 00 jslt %r1,%r2,187
- 508: cd 21 bb 00 00 00 00 00 jslt %r1,%r2,187
- 510: d5 01 bb 00 aa 00 00 00 jsle %r1,0xaa,187
- 518: d5 01 bb 00 aa 00 00 00 jsle %r1,0xaa,187
- 520: dd 21 bb 00 00 00 00 00 jsle %r1,%r2,187
- 528: dd 21 bb 00 00 00 00 00 jsle %r1,%r2,187
- 530: 85 00 00 00 aa 00 00 00 call 170
- 538: 85 00 00 00 aa 00 00 00 call 170
- 540: 95 00 00 00 00 00 00 00 exit
- 548: 95 00 00 00 00 00 00 00 exit
- 550: b7 06 00 00 20 06 00 00 mov %r6,0x620
- 558: 95 00 00 00 00 00 00 00 exit
- 560: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
- 568: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
- 570: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
- 578: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
- 580: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
- 588: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
- 590: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
- 598: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
- 5a0: 18 03 00 00 01 00 00 00 lddw %r3,1
- 5a8: 00 00 00 00 00 00 00 00
- 5b0: 18 03 00 00 01 00 00 00 lddw %r3,1
- 5b8: 00 00 00 00 00 00 00 00
- 5c0: 18 04 00 00 88 77 ff ee lddw %r4,-6144092013047351416
- 5c8: 00 00 00 00 dd cc bb aa
- 5d0: 18 04 00 00 88 77 ff ee lddw %r4,-6144092013047351416
- 5d8: 00 00 00 00 dd cc bb aa
- 5e0: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
- 5e8: 00 00 00 00 44 33 22 11
- 5f0: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
- 5f8: 00 00 00 00 44 33 22 11
- 600: 18 06 00 00 20 06 00 00 lddw %r6,0x620
- 608: 00 00 00 00 00 00 00 00
- 600: R_BPF_64_64 .text
- 610: 18 06 00 00 20 06 00 00 lddw %r6,0x620
- 618: 00 00 00 00 00 00 00 00
- 610: R_BPF_64_64 .text
-
-0000000000000620 <main>:
- 620: c3 21 aa 00 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
- 628: c3 21 aa 00 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
- 630: db 21 aa 00 00 00 00 00 xadddw \[%r1\+0xaa\],%r2
- 638: db 21 aa 00 00 00 00 00 xadddw \[%r1\+0xaa\],%r2
+++ /dev/null
-# Tests for mixing pseudo-C and normal eBPF instructions
-beg:
- .text
- add %r1,0xaa
- r1 += 0xaa
- add %r1,%r2
- r1 += r2
- sub %r1,0xaa
- r1 -= 0xaa
- sub %r1,%r2
- r1 -= r2
- mul %r1,0xaa
- r1 *= 0xaa
- mul %r1,%r2
- r1 *= r2
- div %r1,0xaa
- r1 /= 0xaa
- div %r1,%r2
- r1 /= r2
- or %r1,0xaa
- r1 |= 0xaa
- or %r1,%r2
- r1 |= r2
- and %r1,0xaa
- r1 &= 0xaa
- and %r1,%r2
- r1 &= r2
- lsh %r1,0xaa
- r1 <<= 0xaa
- lsh %r1,%r2
- r1 <<= r2
- rsh %r1,0xaa
- r1 >>= 0xaa
- rsh %r1,%r2
- r1 >>= r2
- xor %r1,0xaa
- r1 ^= 0xaa
- xor %r1,%r2
- r1 ^= r2
- mov %r1,0xaa
- r1 = 0xaa
- mov %r1,%r2
- r1 = r2
- arsh %r1,0xaa
- r1 s>>= 0xaa
- arsh %r1,%r2
- r1 s>>= r2
- neg %r1
- r1 = -r1
- add32 %r1,0xaa
- w1 += 0xaa
- add32 %r1,%r2
- w1 += w2
- sub32 %r1,0xaa
- w1 -= 0xaa
- sub32 %r1,%r2
- w1 -= w2
- mul32 %r1,0xaa
- w1 *= 0xaa
- mul32 %r1,%r2
- w1 *= w2
- div32 %r1,0xaa
- w1 /= 0xaa
- div32 %r1,%r2
- w1 /= w2
- or32 %r1,0xaa
- w1 |= 0xaa
- or32 %r1,%r2
- w1 |= w2
- and32 %r1,0xaa
- w1 &= 0xaa
- and32 %r1,%r2
- w1 &= w2
- lsh32 %r1,0xaa
- w1 <<= 0xaa
- lsh32 %r1,%r2
- w1 <<= w2
- rsh32 %r1,0xaa
- w1 >>= 0xaa
- rsh32 %r1,%r2
- w1 >>= w2
- xor32 %r1,0xaa
- w1 ^= 0xaa
- xor32 %r1,%r2
- w1 ^= w2
- mov32 %r1,0xaa
- w1 = 0xaa
- mov32 %r1,%r2
- w1 = w2
- arsh32 %r1,0xaa
- w1 s>>= 0xaa
- arsh32 %r1,%r2
- w1 s>>= w2
- neg32 %r1
- w1 = -w1
- endle %r1,16
- r1 = le16 r1
- endle %r1,32
- r1 = le32 r1
- endle %r1,64
- r1 = le64 r1
- endbe %r1,16
- r1 = be16 r1
- endbe %r1,32
- r1 = be32 r1
- endbe %r1,64
- r1 = be64 r1
- ldxb %r1,[%r2+0xaa]
- r1 = *(u8 *)(r2 + 0xaa)
- ldxh %r1,[%r2+0xaa]
- r1 = *(u16 *)(r2 + 0xaa)
- ldxw %r1,[%r2+0xaa]
- r1 = *(u32 *)(r2 + 0xaa)
- ldxdw %r1,[%r2+0xaa]
- r1 = *(u64 *)(r2 + 0xaa)
- stxb [%r1+0xaa],%r2
- *(u8 *)(r1 + 0xaa) = r2
- stxh [%r1+0xaa],%r2
- *(u16 *)(r1 + 0xaa) = r2
- stxw [%r1+0xaa],%r2
- *(u32 *)(r1 + 0xaa) = r2
- stxdw [%r1+0xaa],%r2
- *(u64 *)(r1 + 0xaa) = r2
- ja 187
- goto 0xbb
- jeq %r1,0xaa,187
- if r1 == 0xaa goto 0xbb
- jeq %r1,%r2,187
- if r1 == r2 goto 0xbb
- jgt %r1,0xaa,187
- if r1 > 0xaa goto 0xbb
- jgt %r1,%r2,187
- if r1 > r2 goto 0xbb
- jge %r1,0xaa,187
- if r1 >= 0xaa goto 0xbb
- jge %r1,%r2,187
- if r1 >= r2 goto 0xbb
- jlt %r1,0xaa,187
- if r1 < 0xaa goto 0xbb
- jlt %r1,%r2,187
- if r1 < r2 goto 0xbb
- jle %r1,0xaa,187
- if r1 <= 0xaa goto 0xbb
- jle %r1,%r2,187
- if r1 <= r2 goto 0xbb
- jset %r1,0xaa,187
- if r1 & 0xaa goto 0xbb
- jset %r1,%r2,187
- if r1 & r2 goto 0xbb
- jne %r1,0xaa,187
- if r1 != 0xaa goto 0xbb
- jne %r1,%r2,187
- if r1 != r2 goto 0xbb
- jsgt %r1,0xaa,187
- if r1 s> 0xaa goto 0xbb
- jsgt %r1,%r2,187
- if r1 s> r2 goto 0xbb
- jsge %r1,0xaa,187
- if r1 s>= 0xaa goto 0xbb
- jsge %r1,%r2,187
- if r1 s>= r2 goto 0xbb
- jslt %r1,0xaa,187
- if r1 s< 0xaa goto 0xbb
- jslt %r1,%r2,187
- if r1 s< r2 goto 0xbb
- jsle %r1,0xaa,187
- if r1 s<= 0xaa goto 0xbb
- jsle %r1,%r2,187
- if r1 s<= r2 goto 0xbb
- call 170
- call 0xaa
- exit
- exit
- mov %r6,main - beg
- exit
- ldabsw 0xaa
- r0 = *(u32 *)skb[0xaa]
- ldindb %r7,0xaa
- r0 = *(u8 *)skb[r7 + 0xaa]
- ldabsw 0xaa
- r0 = *(u32 *)skb[0xaa]
- ldindb %r7,0xaa
- r0 = *(u8 *)skb[r7 + 0xaa]
- lddw %r3,1
- r3 = 1 ll
- lddw %r4,0xaabbccddeeff7788
- r4 = 0xaabbccddeeff7788 ll
- r5 = 0x1122334455667788 ll
- lddw %r5,0x1122334455667788
- lddw %r6,main
- r6 = main ll
- main:
- lock *(u32 *)(r1 + 0xaa) += r2
- xaddw [%r1+0xaa],%r2
- lock *(u64 *)(r1 + 0xaa) += r2
- xadddw [%r1+0xaa],%r2
--- /dev/null
+#as: -EB -mdialect=pseudoc
+#source: spacing-pseudoc.s
+#objdump: -dr -M hex,pseudoc
+#name: spacing, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: b7 04 00 00 ef be ad de r4=0xdeadbeef
+ 8: 18 04 00 00 ef be ad de r4=0xdeadbeef ll
+ 10: 00 00 00 00 00 00 00 00
+ 18: 05 00 01 00 00 00 00 00 goto 0x1
+ 20: 05 00 01 00 00 00 00 00 goto 0x1
+ 28: 05 00 01 00 00 00 00 00 goto 0x1
+ 30: 16 03 01 00 03 00 00 00 if w3==0x3 goto 0x1
+ 38: 16 03 01 00 03 00 00 00 if w3==0x3 goto 0x1
--- /dev/null
+ ;; This test checks that flexible spacing is supported in the
+ ;; pseudoc syntax.
+ r4 = 0xdeadbeefll
+ r4 = 0xdeadbeef ll
+ goto +1
+ goto+1
+ goto1
+ if w3==3 goto+1
+ if w3==3 goto1
extern void print_s390_disassembler_options (FILE *);
extern void print_wasm32_disassembler_options (FILE *);
extern void print_loongarch_disassembler_options (FILE *);
+extern void print_bpf_disassembler_options (FILE *);
extern bool aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *);
extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *);
* It is kept in this file to remind that the value is already taken. */
RELOC_NUMBER (R_BPF_64_NODYLD32, 4)
RELOC_NUMBER (R_BPF_64_32, 10)
+ RELOC_NUMBER (R_BPF_GNU_64_16, 256)
END_RELOC_NUMBERS (R_BPF_max)
#endif /* _ELF_BPF_H */
--- /dev/null
+/* bpf.h - BPF opcode list for binutils.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Oracle Inc.
+
+ This file is part of the GNU binutils.
+
+ This is free software; you can redistribute them and/or modify them
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#ifndef _BPF_H_
+#define _BPF_H_
+
+#include <stdint.h>
+
+/* The BPF ISA has little-endian and big-endian variants. */
+
+enum bpf_endian
+{
+ BPF_ENDIAN_LITTLE,
+ BPF_ENDIAN_BIG
+};
+
+/* Most BPF instructions are conformed by a single 64-bit instruction
+ word. The lddw instruction is conformed by two consecutive 64-bit
+ instruction words. */
+
+typedef uint64_t bpf_insn_word;
+
+/* There are several versions of the BPF ISA. */
+
+#define BPF_V1 0x1
+#define BPF_V2 0x2
+#define BPF_V3 0x3
+#define BPF_V4 0x4
+#define BPF_XBPF 0xff
+
+/* Masks for the several instruction fields in a BPF instruction.
+ These assume big-endian BPF instructions. */
+
+#define BPF_CODE 0xff00000000000000UL
+#define BPF_REGS 0x00ff000000000000UL
+#define BPF_DST 0x00f0000000000000UL
+#define BPF_SRC 0x000f000000000000UL
+#define BPF_OFFSET16 0x0000ffff00000000UL
+#define BPF_IMM32 0x00000000ffffffffUL
+
+/* The BPF opcode instruction field is eight bits long and its
+ interpretation depends on the instruction class.
+
+ For arithmetic and jump instructions the 8-bit opcode field is
+ subdivided in:
+
+ op-code:4 op-src:1 op-class:3
+
+ For load/store instructions, the 8-bit opcode field is subdivided
+ in:
+
+ op-mode:3 op-size:2 op-class:3
+
+ All the constants defined below are to be applied on the first
+ 64-bit word of a BPF instruction. Please define them assuming
+ big-endian instructions; the matching and writing routines using
+ the instruction table know how to handle the endianness groups. */
+
+#define BPF_SRC_X ((uint64_t)0x08 << 56)
+#define BPF_SRC_K ((uint64_t)0x00 << 56)
+
+#define BPF_CODE_ADD ((uint64_t)0x00 << 56)
+#define BPF_CODE_SUB ((uint64_t)0x10 << 56)
+#define BPF_CODE_MUL ((uint64_t)0x20 << 56)
+#define BPF_CODE_DIV ((uint64_t)0x30 << 56)
+#define BPF_CODE_OR ((uint64_t)0x40 << 56)
+#define BPF_CODE_AND ((uint64_t)0x50 << 56)
+#define BPF_CODE_LSH ((uint64_t)0x60 << 56)
+#define BPF_CODE_RSH ((uint64_t)0x70 << 56)
+#define BPF_CODE_NEG ((uint64_t)0x80 << 56)
+#define BPF_CODE_MOD ((uint64_t)0x90 << 56)
+#define BPF_CODE_XOR ((uint64_t)0xa0 << 56)
+#define BPF_CODE_MOV ((uint64_t)0xb0 << 56)
+#define BPF_CODE_ARSH ((uint64_t)0xc0 << 56)
+#define BPF_CODE_END ((uint64_t)0xd0 << 56)
+
+#define BPF_CODE_JA ((uint64_t)0x00 << 56)
+#define BPF_CODE_JEQ ((uint64_t)0x10 << 56)
+#define BPF_CODE_JGT ((uint64_t)0x20 << 56)
+#define BPF_CODE_JGE ((uint64_t)0x30 << 56)
+#define BPF_CODE_JSET ((uint64_t)0x40 << 56)
+#define BPF_CODE_JNE ((uint64_t)0x50 << 56)
+#define BPF_CODE_JSGT ((uint64_t)0x60 << 56)
+#define BPF_CODE_JSGE ((uint64_t)0x70 << 56)
+#define BPF_CODE_CALL ((uint64_t)0x80 << 56)
+#define BPF_CODE_EXIT ((uint64_t)0x90 << 56)
+#define BPF_CODE_JLT ((uint64_t)0xa0 << 56)
+#define BPF_CODE_JLE ((uint64_t)0xb0 << 56)
+#define BPF_CODE_JSLT ((uint64_t)0xc0 << 56)
+#define BPF_CODE_JSLE ((uint64_t)0xd0 << 56)
+
+#define BPF_MODE_IMM ((uint64_t)0x00 << 56)
+#define BPF_MODE_ABS ((uint64_t)0x20 << 56)
+#define BPF_MODE_IND ((uint64_t)0x40 << 56)
+#define BPF_MODE_MEM ((uint64_t)0x60 << 56)
+#define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56)
+
+#define BPF_SIZE_W ((uint64_t)0x00 << 56)
+#define BPF_SIZE_H ((uint64_t)0x08 << 56)
+#define BPF_SIZE_B ((uint64_t)0x10 << 56)
+#define BPF_SIZE_DW ((uint64_t)0x18 << 56)
+
+#define BPF_CLASS_LD ((uint64_t)0x00 << 56)
+#define BPF_CLASS_LDX ((uint64_t)0x01 << 56)
+#define BPF_CLASS_ST ((uint64_t)0x02 << 56)
+#define BPF_CLASS_STX ((uint64_t)0x03 << 56)
+#define BPF_CLASS_ALU ((uint64_t)0x04 << 56)
+#define BPF_CLASS_JMP ((uint64_t)0x05 << 56)
+#define BPF_CLASS_JMP32 ((uint64_t)0x06 << 56)
+#define BPF_CLASS_ALU64 ((uint64_t)0x07 << 56)
+
+/* Certain instructions (ab)use other instruction fields as opcodes,
+ even if these are multi-byte or infra-byte. Bleh. */
+
+#define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32)
+
+#define BPF_IMM32_END16 ((uint64_t)0x00000010)
+#define BPF_IMM32_END32 ((uint64_t)0x00000020)
+#define BPF_IMM32_END64 ((uint64_t)0x00000040)
+
+#define BPF_IMM32_AADD ((uint64_t)0x00000000)
+#define BPF_IMM32_AOR ((uint64_t)0x00000040)
+#define BPF_IMM32_AAND ((uint64_t)0x00000050)
+#define BPF_IMM32_AXOR ((uint64_t)0x000000a0)
+#define BPF_IMM32_AFADD ((uint64_t)0x00000001)
+#define BPF_IMM32_AFOR ((uint64_t)0x00000041)
+#define BPF_IMM32_AFAND ((uint64_t)0x00000051)
+#define BPF_IMM32_AFXOR ((uint64_t)0x000000a1)
+#define BPF_IMM32_AXCHG ((uint64_t)0x000000e1)
+#define BPF_IMM32_ACMP ((uint64_t)b0x000000f1)
+
+/* Unique identifiers for BPF instructions. */
+
+enum bpf_insn_id
+{
+ BPF_NOINSN = 0,
+ /* 64-bit load instruction. */
+ BPF_INSN_LDDW,
+ /* ALU instructions. */
+ BPF_INSN_ADDR, BPF_INSN_ADDI, BPF_INSN_SUBR, BPF_INSN_SUBI,
+ BPF_INSN_MULR, BPF_INSN_MULI, BPF_INSN_SDIVR, BPF_INSN_SDIVI,
+ BPF_INSN_SMODR, BPF_INSN_SMODI, BPF_INSN_DIVR, BPF_INSN_DIVI,
+ BPF_INSN_MODR, BPF_INSN_MODI, BPF_INSN_ORR, BPF_INSN_ORI,
+ BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI,
+ BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI,
+ BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI,
+ BPF_INSN_MOVR, BPF_INSN_MOVI,
+ /* ALU32 instructions. */
+ BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I,
+ BPF_INSN_MUL32R, BPF_INSN_MUL32I, BPF_INSN_SDIV32R, BPF_INSN_SDIV32I,
+ BPF_INSN_SMOD32R, BPF_INSN_SMOD32I, BPF_INSN_DIV32R, BPF_INSN_DIV32I,
+ BPF_INSN_MOD32R, BPF_INSN_MOD32I, BPF_INSN_OR32R, BPF_INSN_OR32I,
+ BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I,
+ BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I,
+ BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
+ BPF_INSN_MOV32R, BPF_INSN_MOV32I,
+ /* Endianness conversion instructions. */
+ BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,
+ BPF_INSN_ENDBE16, BPF_INSN_ENDBE32, BPF_INSN_ENDBE64,
+ /* Absolute load instructions. */
+ BPF_INSN_LDABSB, BPF_INSN_LDABSH, BPF_INSN_LDABSW, BPF_INSN_LDABSDW,
+ /* Indirect load instructions. */
+ BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW,
+ /* Generic load instructions (to register.) */
+ BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
+ /* Generic store instructions (from register.) */
+ BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR,
+ BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI,
+ /* Compare-and-jump instructions (reg OP reg.) */
+ BPF_INSN_JAR, BPF_INSN_JEQR, BPF_INSN_JGTR, BPF_INSN_JSGTR,
+ BPF_INSN_JGER, BPF_INSN_JSGER, BPF_INSN_JLTR, BPF_INSN_JSLTR,
+ BPF_INSN_JSLER, BPF_INSN_JLER, BPF_INSN_JSETR, BPF_INSN_JNER,
+ BPF_INSN_CALLR, BPF_INSN_CALL, BPF_INSN_EXIT,
+ /* Compare-and-jump instructions (reg OP imm.) */
+ BPF_INSN_JEQI, BPF_INSN_JGTI, BPF_INSN_JSGTI,
+ BPF_INSN_JGEI, BPF_INSN_JSGEI, BPF_INSN_JLTI, BPF_INSN_JSLTI,
+ BPF_INSN_JSLEI, BPF_INSN_JLEI, BPF_INSN_JSETI, BPF_INSN_JNEI,
+ BPF_INSN_CALLI,
+ /* 32-bit compare-and-jump instructions (reg OP reg.) */
+ BPF_INSN_JEQ32R, BPF_INSN_JGT32R, BPF_INSN_JSGT32R,
+ BPF_INSN_JGE32R, BPF_INSN_JSGE32R, BPF_INSN_JLT32R, BPF_INSN_JSLT32R,
+ BPF_INSN_JSLE32R, BPF_INSN_JLE32R, BPF_INSN_JSET32R, BPF_INSN_JNE32R,
+ /* 32-bit compare-and-jump instructions (reg OP imm.) */
+ BPF_INSN_JEQ32I, BPF_INSN_JGT32I, BPF_INSN_JSGT32I,
+ BPF_INSN_JGE32I, BPF_INSN_JSGE32I, BPF_INSN_JLT32I, BPF_INSN_JSLT32I,
+ BPF_INSN_JSLE32I, BPF_INSN_JLE32I, BPF_INSN_JSET32I, BPF_INSN_JNE32I,
+ /* Atomic instructions. */
+ BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR,
+ /* Atomic instructions with fetching. */
+ BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR,
+ /* Atomic instructions (32-bit.) */
+ BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32,
+ /* Atomic instructions with fetching (32-bit.) */
+ BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, BPF_INSN_AFXOR32,
+ /* GNU simulator specific instruction. */
+ BPF_INSN_BRKPT,
+};
+
+/* Entry for a BPF instruction in the opcodes table. */
+
+struct bpf_opcode
+{
+ /* Unique numerical code for the instruction. */
+ enum bpf_insn_id id;
+
+ /* The instruction template defines both the syntax of the
+ instruction and the set of the different operands that appear in
+ the instruction.
+
+ Tags:
+ %% - literal %.
+ %dr - destination 64-bit register.
+ %dw - destination 32-bit register.
+ %sr - source 64-bit register.
+ %sw - source 32-bit register.
+ %d32 - 32-bit signed displacement (in 64-bit words minus one.)
+ %d16 - 16-bit signed displacement (in 64-bit words minus one.)
+ %o16 - 16-bit signed offset (in bytes.)
+ %i32 - 32-bit signed immediate.
+ %I32 - Like %i32.
+ %i64 - 64-bit signed immediate.
+ %w - expect zero or more white spaces and print a single space.
+ %W - expect one or more white spaces and print a single space.
+
+ When parsing and printing %o16 and %I32 (but not %i32) an
+ explicit sign is always expected and included. Therefore, to
+ denote something like `[%r3 + 10]', please use a template like `[
+ %sr %o16]' instead of `[ %sr + %o16 ]'.
+
+ If %dr, %dw, %sr or %sw are found multiple times in a template,
+ they refer to the same register, i.e. `%rd = le64 %rd' denotes
+ `r2 = le64 r2', but not `r2 = le64 r1'.
+
+ If %i64 appears in a template then the instruction is 128-bits
+ long and composed by two consecutive 64-bit instruction words.
+
+ A white space character means to expect zero or more white
+ spaces, and to print no space.
+
+ There are two templates defined per instruction, corresponding to
+ two used different dialects: a "normal" assembly-like syntax and
+ a "pseudo-c" syntax. Some toolchains support just one of these
+ dialects. The GNU Toolchain supports both. */
+ const char *normal;
+ const char *pseudoc;
+
+ /* The version that introduced this instruction. Instructions are
+ generally not removed once they get introduced. */
+ uint8_t version;
+
+ /* Maks marking the opcode fields in the instruction, and the
+ opcodes characterizing it.
+
+ In multi-word instructions these apply to the first word in the
+ instruction. Note that these values assumes big-endian
+ instructions; code using these field must be aware of the
+ endianness groups to which BPF instructions must conform to and
+ DTRT. */
+ bpf_insn_word mask;
+ bpf_insn_word opcode;
+};
+
+/* Try to match a BPF instruction given its first instruction word.
+ If no matching instruction is found, return NULL. */
+
+const struct bpf_opcode *bpf_match_insn (bpf_insn_word word,
+ enum bpf_endian endian,
+ int version);
+
+/* Operand extractors.
+
+ These all get big-endian instruction words. Note how the extractor
+ for 64-bit signed immediates requires two instruction words. */
+
+uint8_t bpf_extract_src (bpf_insn_word word, enum bpf_endian endian);
+uint8_t bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian);
+int16_t bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian);
+int32_t bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian);
+int64_t bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,
+ enum bpf_endian endian);
+
+/* Get the opcode occupying the INDEX position in the opcodes table.
+ The INDEX is zero based. If the provided index overflows the
+ opcodes table then NULL is returned. */
+
+const struct bpf_opcode *bpf_get_opcode (unsigned int index);
+
+#endif /* !_BPF_H_ */
-#as: --EL
+#as: --EL -mdialect=normal
#source: foo.s
#source: bar.s
-#objdump: -dr
+#objdump: -dr -M dec
#ld: -EL
#name: CALL with 64_32 reloc
#as: --EL
#source: call-2.s
#source: bar.s
-#objdump: -dr
+#objdump: -dr -M dec
#ld: -EL
#name: CALL with disp32 reloc and addend
-#as: --EB
+#as: -EB -mdialect=normal
#source: reloc-data.s
#source: reloc-insn-external.s
-#objdump: -dr
+#objdump: -dr -M hex
#ld: -Tdata=0x20 -EB
#name: reloc insn external BE
-#as: --EL
+#as: -EL -mdialect=normal
#source: reloc-data.s
#source: reloc-insn-external.s
-#objdump: -dr
+#objdump: -dr -M hex
#ld: -Tdata=0x20 -EL
#name: reloc insn external LE
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
- bpf-desc.h bpf-opc.h \
cris-desc.h cris-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
- bpf-asm.c \
- bpf-desc.c \
- bpf-dis.c \
- bpf-ibld.c \
bpf-opc.c \
ia64-dis.c \
ia64-opc.c \
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
if CGEN_MAINT
-BPF_DEPS = stamp-bpf
CRIS_DEPS = stamp-cris
EPIPHANY_DEPS = stamp-epiphany
FR30_DEPS = stamp-fr30
OR1K_DEPS = stamp-or1k
XSTORMY16_DEPS = stamp-xstormy16
else
-BPF_DEPS =
CRIS_DEPS =
EPIPHANY_DEPS =
FR30_DEPS =
# For now, require developers to configure with --enable-cgen-maint.
-$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
- $(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
- $(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
- @true
-
-stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
- $(MAKE) run-cgen arch=bpf prefix=bpf \
- archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
-
$(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)
@true
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
- bpf-desc.h bpf-opc.h \
cris-desc.h cris-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
- bpf-asm.c \
- bpf-desc.c \
- bpf-dis.c \
- bpf-ibld.c \
bpf-opc.c \
ia64-dis.c \
ia64-opc.c \
cgen-asm.in cgen-dis.in cgen-ibld.in
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
-@CGEN_MAINT_FALSE@BPF_DEPS =
-@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
@CGEN_MAINT_FALSE@CRIS_DEPS =
@CGEN_MAINT_TRUE@CRIS_DEPS = stamp-cris
@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-asm.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-desc.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-ibld.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-bitset.Plo@am__quote@
# For now, require developers to configure with --enable-cgen-maint.
-$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
- $(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
- $(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
- @true
-
-stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
- $(MAKE) run-cgen arch=bpf prefix=bpf \
- archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
-
$(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)
@true
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Assembler interface for targets using CGEN. -*- C -*-
- CGEN: Cpu tools GENerator
-
- THIS FILE IS MACHINE GENERATED WITH CGEN.
- - the resultant file is machine generated, cgen-asm.in isn't
-
- Copyright (C) 1996-2023 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
-#include "opintl.h"
-#include "xregex.h"
-#include "libiberty.h"
-#include "safe-ctype.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
-#define max(a,b) ((a) > (b) ? (a) : (b))
-
-static const char * parse_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
-\f
-/* -- assembler routines inserted here. */
-
-/* -- asm.c */
-
-/* Parse a signed 64-bit immediate. */
-
-static const char *
-parse_imm64 (CGEN_CPU_DESC cd,
- const char **strp,
- int opindex,
- int64_t *valuep)
-{
- bfd_vma value;
- enum cgen_parse_operand_result result;
- const char *errmsg;
-
- errmsg = (* cd->parse_operand_fn)
- (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
- &result, &value);
- if (!errmsg)
- *valuep = value;
-
- return errmsg;
-}
-
-/* Endianness size operands are integer immediates whose values can be
- 16, 32 or 64. */
-
-static const char *
-parse_endsize (CGEN_CPU_DESC cd,
- const char **strp,
- int opindex,
- unsigned long *valuep)
-{
- const char *errmsg;
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
- if (errmsg)
- return errmsg;
-
- switch (*valuep)
- {
- case 16:
- case 32:
- case 64:
- break;
- default:
- return _("expected 16, 32 or 64 in");
- }
-
- return NULL;
-}
-
-/* Special check to ensure that the right instruction variant is used
- for the given endianness induced by the ISA selected in the CPU.
- See bpf.cpu for a discussion on how eBPF is really two instruction
- sets. */
-
-int
-bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
-{
- CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
-
- return cgen_bitset_intersect_p (&isas, cd->isas);
-}
-
-\f
-/* -- dis.c */
-
-const char * bpf_cgen_parse_operand
- (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
-
-/* Main entry point for operand parsing.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `parse_insn_normal', but keeping it
- separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. */
-
-const char *
-bpf_cgen_parse_operand (CGEN_CPU_DESC cd,
- int opindex,
- const char ** strp,
- CGEN_FIELDS * fields)
-{
- const char * errmsg = NULL;
- /* Used by scalar operands that still need to be parsed. */
- long junk ATTRIBUTE_UNUSED;
-
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP16, (long *) (& fields->f_offset16));
- break;
- case BPF_OPERAND_DISP32 :
- errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP32, (long *) (& fields->f_imm32));
- break;
- case BPF_OPERAND_DSTBE :
- errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstbe);
- break;
- case BPF_OPERAND_DSTLE :
- errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstle);
- break;
- case BPF_OPERAND_ENDSIZE :
- errmsg = parse_endsize (cd, strp, BPF_OPERAND_ENDSIZE, (unsigned long *) (& fields->f_imm32));
- break;
- case BPF_OPERAND_IMM32 :
- errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_IMM32, (long *) (& fields->f_imm32));
- break;
- case BPF_OPERAND_IMM64 :
- errmsg = parse_imm64 (cd, strp, BPF_OPERAND_IMM64, (int64_t *) (& fields->f_imm64));
- break;
- case BPF_OPERAND_OFFSET16 :
- errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_OFFSET16, (long *) (& fields->f_offset16));
- break;
- case BPF_OPERAND_SRCBE :
- errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcbe);
- break;
- case BPF_OPERAND_SRCLE :
- errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcle);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while parsing"),
- opindex);
- abort ();
- }
-
- return errmsg;
-}
-
-cgen_parse_fn * const bpf_cgen_parse_handlers[] =
-{
- parse_insn_normal,
-};
-
-void
-bpf_cgen_init_asm (CGEN_CPU_DESC cd)
-{
- bpf_cgen_init_opcode_table (cd);
- bpf_cgen_init_ibld_table (cd);
- cd->parse_handlers = & bpf_cgen_parse_handlers[0];
- cd->parse_operand = bpf_cgen_parse_operand;
-#ifdef CGEN_ASM_INIT_HOOK
-CGEN_ASM_INIT_HOOK
-#endif
-}
-
-\f
-
-/* Regex construction routine.
-
- This translates an opcode syntax string into a regex string,
- by replacing any non-character syntax element (such as an
- opcode) with the pattern '.*'
-
- It then compiles the regex and stores it in the opcode, for
- later use by bpf_cgen_assemble_insn
-
- Returns NULL for success, an error message for failure. */
-
-char *
-bpf_cgen_build_insn_regex (CGEN_INSN *insn)
-{
- CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
- const char *mnem = CGEN_INSN_MNEMONIC (insn);
- char rxbuf[CGEN_MAX_RX_ELEMENTS];
- char *rx = rxbuf;
- const CGEN_SYNTAX_CHAR_TYPE *syn;
- int reg_err;
-
- syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
-
- /* Mnemonics come first in the syntax string. */
- if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
- return _("missing mnemonic in syntax string");
- ++syn;
-
- /* Generate a case sensitive regular expression that emulates case
- insensitive matching in the "C" locale. We cannot generate a case
- insensitive regular expression because in Turkish locales, 'i' and 'I'
- are not equal modulo case conversion. */
-
- /* Copy the literal mnemonic out of the insn. */
- for (; *mnem; mnem++)
- {
- char c = *mnem;
-
- if (ISALPHA (c))
- {
- *rx++ = '[';
- *rx++ = TOLOWER (c);
- *rx++ = TOUPPER (c);
- *rx++ = ']';
- }
- else
- *rx++ = c;
- }
-
- /* Copy any remaining literals from the syntax string into the rx. */
- for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
- {
- if (CGEN_SYNTAX_CHAR_P (* syn))
- {
- char c = CGEN_SYNTAX_CHAR (* syn);
-
- switch (c)
- {
- /* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
-
-#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
- case '(': case ')': case '*':
- case '|': case '+': case ']':
-#endif
- *rx++ = '\\';
- *rx++ = c;
- break;
-
- default:
- if (ISALPHA (c))
- {
- *rx++ = '[';
- *rx++ = TOLOWER (c);
- *rx++ = TOUPPER (c);
- *rx++ = ']';
- }
- else
- *rx++ = c;
- break;
- }
- }
- else
- {
- /* Replace non-syntax fields with globs. */
- *rx++ = '.';
- *rx++ = '*';
- }
- }
-
- /* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
-
- /* But anchor it after that. */
- * rx++ = '$';
- * rx = '\0';
-
- CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
- reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
-
- if (reg_err == 0)
- return NULL;
- else
- {
- static char msg[80];
-
- regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
- regfree ((regex_t *) CGEN_INSN_RX (insn));
- free (CGEN_INSN_RX (insn));
- (CGEN_INSN_RX (insn)) = NULL;
- return msg;
- }
-}
-
-\f
-/* Default insn parser.
-
- The syntax string is scanned and operands are parsed and stored in FIELDS.
- Relocs are queued as we go via other callbacks.
-
- ??? Note that this is currently an all-or-nothing parser. If we fail to
- parse the instruction, we return 0 and the caller will start over from
- the beginning. Backtracking will be necessary in parsing subexpressions,
- but that can be handled there. Not handling backtracking here may get
- expensive in the case of the m68k. Deal with later.
-
- Returns NULL for success, an error message for failure. */
-
-static const char *
-parse_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn,
- const char **strp,
- CGEN_FIELDS *fields)
-{
- /* ??? Runtime added insns not handled yet. */
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- const char *str = *strp;
- const char *errmsg;
- const char *p;
- const CGEN_SYNTAX_CHAR_TYPE * syn;
-#ifdef CGEN_MNEMONIC_OPERANDS
- /* FIXME: wip */
- int past_opcode_p;
-#endif
-
- /* For now we assume the mnemonic is first (there are no leading operands).
- We can parse it without needing to set up operand parsing.
- GAS's input scrubber will ensure mnemonics are lowercase, but we may
- not be called from GAS. */
- p = CGEN_INSN_MNEMONIC (insn);
- while (*p && TOLOWER (*p) == TOLOWER (*str))
- ++p, ++str;
-
- if (* p)
- return _("unrecognized instruction");
-
-#ifndef CGEN_MNEMONIC_OPERANDS
- if (* str && ! ISSPACE (* str))
- return _("unrecognized instruction");
-#endif
-
- CGEN_INIT_PARSE (cd);
- cgen_init_parse_operand (cd);
-#ifdef CGEN_MNEMONIC_OPERANDS
- past_opcode_p = 0;
-#endif
-
- /* We don't check for (*str != '\0') here because we want to parse
- any trailing fake arguments in the syntax string. */
- syn = CGEN_SYNTAX_STRING (syntax);
-
- /* Mnemonics come first for now, ensure valid string. */
- if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
- abort ();
-
- ++syn;
-
- while (* syn != 0)
- {
- /* Non operand chars must match exactly. */
- if (CGEN_SYNTAX_CHAR_P (* syn))
- {
- /* FIXME: While we allow for non-GAS callers above, we assume the
- first char after the mnemonic part is a space. */
- /* FIXME: We also take inappropriate advantage of the fact that
- GAS's input scrubber will remove extraneous blanks. */
- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
- {
-#ifdef CGEN_MNEMONIC_OPERANDS
- if (CGEN_SYNTAX_CHAR(* syn) == ' ')
- past_opcode_p = 1;
-#endif
- ++ syn;
- ++ str;
- }
- else if (*str)
- {
- /* Syntax char didn't match. Can't be this insn. */
- static char msg [80];
-
- /* xgettext:c-format */
- sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
- CGEN_SYNTAX_CHAR(*syn), *str);
- return msg;
- }
- else
- {
- /* Ran out of input. */
- static char msg [80];
-
- /* xgettext:c-format */
- sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
- CGEN_SYNTAX_CHAR(*syn));
- return msg;
- }
- continue;
- }
-
-#ifdef CGEN_MNEMONIC_OPERANDS
- (void) past_opcode_p;
-#endif
- /* We have an operand of some sort. */
- errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
- if (errmsg)
- return errmsg;
-
- /* Done with this operand, continue with next one. */
- ++ syn;
- }
-
- /* If we're at the end of the syntax string, we're done. */
- if (* syn == 0)
- {
- /* FIXME: For the moment we assume a valid `str' can only contain
- blanks now. IE: We needn't try again with a longer version of
- the insn and it is assumed that longer versions of insns appear
- before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
- while (ISSPACE (* str))
- ++ str;
-
- if (* str != '\0')
- return _("junk at end of line"); /* FIXME: would like to include `str' */
-
- return NULL;
- }
-
- /* We couldn't parse it. */
- return _("unrecognized instruction");
-}
-\f
-/* Main entry point.
- This routine is called for each instruction to be assembled.
- STR points to the insn to be assembled.
- We assume all necessary tables have been initialized.
- The assembled instruction, less any fixups, is stored in BUF.
- Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
- still needs to be converted to target byte order, otherwise BUF is an array
- of bytes in target byte order.
- The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
- printed).
-
- Note that when processing (non-alias) macro-insns,
- this function recurses.
-
- ??? It's possible to make this cpu-independent.
- One would have to deal with a few minor things.
- At this point in time doing so would be more of a curiosity than useful
- [for example this file isn't _that_ big], but keeping the possibility in
- mind helps keep the design clean. */
-
-const CGEN_INSN *
-bpf_cgen_assemble_insn (CGEN_CPU_DESC cd,
- const char *str,
- CGEN_FIELDS *fields,
- CGEN_INSN_BYTES_PTR buf,
- char **errmsg)
-{
- const char *start;
- CGEN_INSN_LIST *ilist;
- const char *parse_errmsg = NULL;
- const char *insert_errmsg = NULL;
- int recognized_mnemonic = 0;
-
- /* Skip leading white space. */
- while (ISSPACE (* str))
- ++ str;
-
- /* The instructions are stored in hashed lists.
- Get the first in the list. */
- ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
-
- /* Keep looking until we find a match. */
- start = str;
- for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
- {
- const CGEN_INSN *insn = ilist->insn;
- recognized_mnemonic = 1;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* Not usually needed as unsupported opcodes
- shouldn't be in the hash lists. */
- /* Is this insn supported by the selected cpu? */
- if (! bpf_cgen_insn_supported (cd, insn))
- continue;
-#endif
- /* If the RELAXED attribute is set, this is an insn that shouldn't be
- chosen immediately. Instead, it is used during assembler/linker
- relaxation if possible. */
- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
- continue;
-
- str = start;
-
- /* Skip this insn if str doesn't look right lexically. */
- if (CGEN_INSN_RX (insn) != NULL &&
- regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
- continue;
-
- /* Allow parse/insert handlers to obtain length of insn. */
- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
-
- parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
- if (parse_errmsg != NULL)
- continue;
-
- /* ??? 0 is passed for `pc'. */
- insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
- (bfd_vma) 0);
- if (insert_errmsg != NULL)
- continue;
-
- /* It is up to the caller to actually output the insn and any
- queued relocs. */
- return insn;
- }
-
- {
- static char errbuf[150];
- const char *tmp_errmsg;
-#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
-#define be_verbose 1
-#else
-#define be_verbose 0
-#endif
-
- if (be_verbose)
- {
- /* If requesting verbose error messages, use insert_errmsg.
- Failing that, use parse_errmsg. */
- tmp_errmsg = (insert_errmsg ? insert_errmsg :
- parse_errmsg ? parse_errmsg :
- recognized_mnemonic ?
- _("unrecognized form of instruction") :
- _("unrecognized instruction"));
-
- if (strlen (start) > 50)
- /* xgettext:c-format */
- sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
- /* xgettext:c-format */
- sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
- }
- else
- {
- if (strlen (start) > 50)
- /* xgettext:c-format */
- sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
- /* xgettext:c-format */
- sprintf (errbuf, _("bad instruction `%.50s'"), start);
- }
-
- *errmsg = errbuf;
- return NULL;
- }
-}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* CPU data for bpf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2023 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
-#include "opintl.h"
-#include "libiberty.h"
-#include "xregex.h"
-
-/* Attributes. */
-
-static const CGEN_ATTR_ENTRY bool_attr[] =
-{
- { "#f", 0 },
- { "#t", 1 },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
-{
- { "base", MACH_BASE },
- { "bpf", MACH_BPF },
- { "xbpf", MACH_XBPF },
- { "max", MACH_MAX },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
-{
- { "ebpfle", ISA_EBPFLE },
- { "ebpfbe", ISA_EBPFBE },
- { "xbpfle", ISA_XBPFLE },
- { "xbpfbe", ISA_XBPFBE },
- { "max", ISA_MAX },
- { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "ISA", & ISA_attr[0], & ISA_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "RESERVED", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "ISA", & ISA_attr[0], & ISA_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
- { "PC", &bool_attr[0], &bool_attr[0] },
- { "PROFILE", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "ISA", & ISA_attr[0], & ISA_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
- { "RELAX", &bool_attr[0], &bool_attr[0] },
- { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "ISA", & ISA_attr[0], & ISA_attr[0] },
- { "ALIAS", &bool_attr[0], &bool_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
- { "COND-CTI", &bool_attr[0], &bool_attr[0] },
- { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
- { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
- { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
- { "RELAXED", &bool_attr[0], &bool_attr[0] },
- { "NO-DIS", &bool_attr[0], &bool_attr[0] },
- { "PBB", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-/* Instruction set variants. */
-
-static const CGEN_ISA bpf_cgen_isa_table[] = {
- { "ebpfle", 64, 64, 64, 128 },
- { "ebpfbe", 64, 64, 64, 128 },
- { "xbpfle", 64, 64, 64, 128 },
- { "xbpfbe", 64, 64, 64, 128 },
- { 0, 0, 0, 0, 0 }
-};
-
-/* Machine variants. */
-
-static const CGEN_MACH bpf_cgen_mach_table[] = {
- { "bpf", "bpf", MACH_BPF, 0 },
- { "xbpf", "xbpf", MACH_XBPF, 0 },
- { 0, 0, 0, 0 }
-};
-
-static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
-{
- { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD bpf_cgen_opval_h_gpr =
-{
- & bpf_cgen_opval_h_gpr_entries[0],
- 14,
- 0, 0, 0, 0, ""
-};
-
-
-/* The hardware table. */
-
-#define A(a) (1 << CGEN_HW_##a)
-
-const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
-{
- { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } },
- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
-};
-
-#undef A
-
-
-/* The instruction field table. */
-
-#define A(a) (1 << CGEN_IFLD_##a)
-
-const CGEN_IFLD bpf_cgen_ifld_table[] =
-{
- { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
- { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
- { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
- { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
- { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
- { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
-};
-
-#undef A
-
-
-
-/* multi ifield declarations */
-
-const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
-
-
-/* multi ifield definitions */
-
-const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
-{
- { 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
- { 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
- { 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
- { 0, { 0 } }
-};
-
-/* The operand table. */
-
-#define A(a) (1 << CGEN_OPERAND_##a)
-#define OPERAND(op) BPF_OPERAND_##op
-
-const CGEN_OPERAND bpf_cgen_operand_table[] =
-{
-/* pc: program counter */
- { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { &bpf_cgen_ifld_table[BPF_F_NIL] } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* dstle: destination register */
- { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
- { 0, { &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
-/* srcle: source register */
- { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
- { 0, { &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
-/* dstbe: destination register */
- { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
- { 0, { &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
-/* srcbe: source register */
- { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
- { 0, { &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
-/* disp16: 16-bit PC-relative address */
- { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
- { 0, { &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
- { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* disp32: 32-bit PC-relative address */
- { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
- { 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
- { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* imm32: 32-bit immediate */
- { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
- { 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* offset16: 16-bit offset */
- { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
- { 0, { &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* imm64: 64-bit immediate */
- { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
- { 3, { &BPF_F_IMM64_MULTI_IFIELD[0] } },
- { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* endsize: endianness size immediate: 16, 32 or 64 */
- { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
- { 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
-/* sentinel */
- { 0, 0, 0, 0, 0,
- { 0, { 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
-};
-
-#undef A
-
-
-/* The instruction table. */
-
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#define A(a) (1 << CGEN_INSN_##a)
-
-static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
-{
- /* Special null first entry.
- A `num' value of zero is thus invalid.
- Also, the special `invalid' insn resides here. */
- { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
-/* add $dstle,$imm32 */
- {
- BPF_INSN_ADDILE, "addile", "add", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* add $dstle,$srcle */
- {
- BPF_INSN_ADDRLE, "addrle", "add", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* add32 $dstle,$imm32 */
- {
- BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* add32 $dstle,$srcle */
- {
- BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* sub $dstle,$imm32 */
- {
- BPF_INSN_SUBILE, "subile", "sub", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* sub $dstle,$srcle */
- {
- BPF_INSN_SUBRLE, "subrle", "sub", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* sub32 $dstle,$imm32 */
- {
- BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* sub32 $dstle,$srcle */
- {
- BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mul $dstle,$imm32 */
- {
- BPF_INSN_MULILE, "mulile", "mul", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mul $dstle,$srcle */
- {
- BPF_INSN_MULRLE, "mulrle", "mul", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mul32 $dstle,$imm32 */
- {
- BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mul32 $dstle,$srcle */
- {
- BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* div $dstle,$imm32 */
- {
- BPF_INSN_DIVILE, "divile", "div", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* div $dstle,$srcle */
- {
- BPF_INSN_DIVRLE, "divrle", "div", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* div32 $dstle,$imm32 */
- {
- BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* div32 $dstle,$srcle */
- {
- BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* or $dstle,$imm32 */
- {
- BPF_INSN_ORILE, "orile", "or", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* or $dstle,$srcle */
- {
- BPF_INSN_ORRLE, "orrle", "or", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* or32 $dstle,$imm32 */
- {
- BPF_INSN_OR32ILE, "or32ile", "or32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* or32 $dstle,$srcle */
- {
- BPF_INSN_OR32RLE, "or32rle", "or32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* and $dstle,$imm32 */
- {
- BPF_INSN_ANDILE, "andile", "and", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* and $dstle,$srcle */
- {
- BPF_INSN_ANDRLE, "andrle", "and", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* and32 $dstle,$imm32 */
- {
- BPF_INSN_AND32ILE, "and32ile", "and32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* and32 $dstle,$srcle */
- {
- BPF_INSN_AND32RLE, "and32rle", "and32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* lsh $dstle,$imm32 */
- {
- BPF_INSN_LSHILE, "lshile", "lsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* lsh $dstle,$srcle */
- {
- BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* lsh32 $dstle,$imm32 */
- {
- BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* lsh32 $dstle,$srcle */
- {
- BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* rsh $dstle,$imm32 */
- {
- BPF_INSN_RSHILE, "rshile", "rsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* rsh $dstle,$srcle */
- {
- BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* rsh32 $dstle,$imm32 */
- {
- BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* rsh32 $dstle,$srcle */
- {
- BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mod $dstle,$imm32 */
- {
- BPF_INSN_MODILE, "modile", "mod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mod $dstle,$srcle */
- {
- BPF_INSN_MODRLE, "modrle", "mod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mod32 $dstle,$imm32 */
- {
- BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mod32 $dstle,$srcle */
- {
- BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* xor $dstle,$imm32 */
- {
- BPF_INSN_XORILE, "xorile", "xor", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* xor $dstle,$srcle */
- {
- BPF_INSN_XORRLE, "xorrle", "xor", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* xor32 $dstle,$imm32 */
- {
- BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* xor32 $dstle,$srcle */
- {
- BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* arsh $dstle,$imm32 */
- {
- BPF_INSN_ARSHILE, "arshile", "arsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* arsh $dstle,$srcle */
- {
- BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* arsh32 $dstle,$imm32 */
- {
- BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* arsh32 $dstle,$srcle */
- {
- BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* sdiv $dstle,$imm32 */
- {
- BPF_INSN_SDIVILE, "sdivile", "sdiv", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* sdiv $dstle,$srcle */
- {
- BPF_INSN_SDIVRLE, "sdivrle", "sdiv", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* sdiv32 $dstle,$imm32 */
- {
- BPF_INSN_SDIV32ILE, "sdiv32ile", "sdiv32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* sdiv32 $dstle,$srcle */
- {
- BPF_INSN_SDIV32RLE, "sdiv32rle", "sdiv32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* smod $dstle,$imm32 */
- {
- BPF_INSN_SMODILE, "smodile", "smod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* smod $dstle,$srcle */
- {
- BPF_INSN_SMODRLE, "smodrle", "smod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* smod32 $dstle,$imm32 */
- {
- BPF_INSN_SMOD32ILE, "smod32ile", "smod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* smod32 $dstle,$srcle */
- {
- BPF_INSN_SMOD32RLE, "smod32rle", "smod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* neg $dstle */
- {
- BPF_INSN_NEGLE, "negle", "neg", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* neg32 $dstle */
- {
- BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mov $dstle,$imm32 */
- {
- BPF_INSN_MOVILE, "movile", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mov $dstle,$srcle */
- {
- BPF_INSN_MOVRLE, "movrle", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mov32 $dstle,$imm32 */
- {
- BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* mov32 $dstle,$srcle */
- {
- BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* add $dstbe,$imm32 */
- {
- BPF_INSN_ADDIBE, "addibe", "add", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* add $dstbe,$srcbe */
- {
- BPF_INSN_ADDRBE, "addrbe", "add", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* add32 $dstbe,$imm32 */
- {
- BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* add32 $dstbe,$srcbe */
- {
- BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* sub $dstbe,$imm32 */
- {
- BPF_INSN_SUBIBE, "subibe", "sub", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* sub $dstbe,$srcbe */
- {
- BPF_INSN_SUBRBE, "subrbe", "sub", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* sub32 $dstbe,$imm32 */
- {
- BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* sub32 $dstbe,$srcbe */
- {
- BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mul $dstbe,$imm32 */
- {
- BPF_INSN_MULIBE, "mulibe", "mul", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mul $dstbe,$srcbe */
- {
- BPF_INSN_MULRBE, "mulrbe", "mul", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mul32 $dstbe,$imm32 */
- {
- BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mul32 $dstbe,$srcbe */
- {
- BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* div $dstbe,$imm32 */
- {
- BPF_INSN_DIVIBE, "divibe", "div", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* div $dstbe,$srcbe */
- {
- BPF_INSN_DIVRBE, "divrbe", "div", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* div32 $dstbe,$imm32 */
- {
- BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* div32 $dstbe,$srcbe */
- {
- BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* or $dstbe,$imm32 */
- {
- BPF_INSN_ORIBE, "oribe", "or", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* or $dstbe,$srcbe */
- {
- BPF_INSN_ORRBE, "orrbe", "or", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* or32 $dstbe,$imm32 */
- {
- BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* or32 $dstbe,$srcbe */
- {
- BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* and $dstbe,$imm32 */
- {
- BPF_INSN_ANDIBE, "andibe", "and", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* and $dstbe,$srcbe */
- {
- BPF_INSN_ANDRBE, "andrbe", "and", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* and32 $dstbe,$imm32 */
- {
- BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* and32 $dstbe,$srcbe */
- {
- BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* lsh $dstbe,$imm32 */
- {
- BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* lsh $dstbe,$srcbe */
- {
- BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* lsh32 $dstbe,$imm32 */
- {
- BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* lsh32 $dstbe,$srcbe */
- {
- BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* rsh $dstbe,$imm32 */
- {
- BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* rsh $dstbe,$srcbe */
- {
- BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* rsh32 $dstbe,$imm32 */
- {
- BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* rsh32 $dstbe,$srcbe */
- {
- BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mod $dstbe,$imm32 */
- {
- BPF_INSN_MODIBE, "modibe", "mod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mod $dstbe,$srcbe */
- {
- BPF_INSN_MODRBE, "modrbe", "mod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mod32 $dstbe,$imm32 */
- {
- BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mod32 $dstbe,$srcbe */
- {
- BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* xor $dstbe,$imm32 */
- {
- BPF_INSN_XORIBE, "xoribe", "xor", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* xor $dstbe,$srcbe */
- {
- BPF_INSN_XORRBE, "xorrbe", "xor", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* xor32 $dstbe,$imm32 */
- {
- BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* xor32 $dstbe,$srcbe */
- {
- BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* arsh $dstbe,$imm32 */
- {
- BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* arsh $dstbe,$srcbe */
- {
- BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* arsh32 $dstbe,$imm32 */
- {
- BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* arsh32 $dstbe,$srcbe */
- {
- BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* sdiv $dstbe,$imm32 */
- {
- BPF_INSN_SDIVIBE, "sdivibe", "sdiv", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* sdiv $dstbe,$srcbe */
- {
- BPF_INSN_SDIVRBE, "sdivrbe", "sdiv", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* sdiv32 $dstbe,$imm32 */
- {
- BPF_INSN_SDIV32IBE, "sdiv32ibe", "sdiv32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* sdiv32 $dstbe,$srcbe */
- {
- BPF_INSN_SDIV32RBE, "sdiv32rbe", "sdiv32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* smod $dstbe,$imm32 */
- {
- BPF_INSN_SMODIBE, "smodibe", "smod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* smod $dstbe,$srcbe */
- {
- BPF_INSN_SMODRBE, "smodrbe", "smod", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* smod32 $dstbe,$imm32 */
- {
- BPF_INSN_SMOD32IBE, "smod32ibe", "smod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* smod32 $dstbe,$srcbe */
- {
- BPF_INSN_SMOD32RBE, "smod32rbe", "smod32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* neg $dstbe */
- {
- BPF_INSN_NEGBE, "negbe", "neg", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* neg32 $dstbe */
- {
- BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mov $dstbe,$imm32 */
- {
- BPF_INSN_MOVIBE, "movibe", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mov $dstbe,$srcbe */
- {
- BPF_INSN_MOVRBE, "movrbe", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mov32 $dstbe,$imm32 */
- {
- BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* mov32 $dstbe,$srcbe */
- {
- BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* endle $dstle,$endsize */
- {
- BPF_INSN_ENDLELE, "endlele", "endle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* endbe $dstle,$endsize */
- {
- BPF_INSN_ENDBELE, "endbele", "endbe", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* endle $dstbe,$endsize */
- {
- BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* endbe $dstbe,$endsize */
- {
- BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* lddw $dstle,$imm64 */
- {
- BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* lddw $dstbe,$imm64 */
- {
- BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldabsw $imm32 */
- {
- BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-/* ldabsh $imm32 */
- {
- BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-/* ldabsb $imm32 */
- {
- BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-/* ldabsdw $imm32 */
- {
- BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-/* ldindw $srcle,$imm32 */
- {
- BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldindh $srcle,$imm32 */
- {
- BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldindb $srcle,$imm32 */
- {
- BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldinddw $srcle,$imm32 */
- {
- BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldindw $srcbe,$imm32 */
- {
- BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldindh $srcbe,$imm32 */
- {
- BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldindb $srcbe,$imm32 */
- {
- BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldinddw $srcbe,$imm32 */
- {
- BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldxw $dstle,[$srcle+$offset16] */
- {
- BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldxh $dstle,[$srcle+$offset16] */
- {
- BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldxb $dstle,[$srcle+$offset16] */
- {
- BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldxdw $dstle,[$srcle+$offset16] */
- {
- BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stxw [$dstle+$offset16],$srcle */
- {
- BPF_INSN_STXWLE, "stxwle", "stxw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stxh [$dstle+$offset16],$srcle */
- {
- BPF_INSN_STXHLE, "stxhle", "stxh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stxb [$dstle+$offset16],$srcle */
- {
- BPF_INSN_STXBLE, "stxble", "stxb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stxdw [$dstle+$offset16],$srcle */
- {
- BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* ldxw $dstbe,[$srcbe+$offset16] */
- {
- BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldxh $dstbe,[$srcbe+$offset16] */
- {
- BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldxb $dstbe,[$srcbe+$offset16] */
- {
- BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* ldxdw $dstbe,[$srcbe+$offset16] */
- {
- BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stxw [$dstbe+$offset16],$srcbe */
- {
- BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stxh [$dstbe+$offset16],$srcbe */
- {
- BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stxb [$dstbe+$offset16],$srcbe */
- {
- BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stxdw [$dstbe+$offset16],$srcbe */
- {
- BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stb [$dstle+$offset16],$imm32 */
- {
- BPF_INSN_STBLE, "stble", "stb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* sth [$dstle+$offset16],$imm32 */
- {
- BPF_INSN_STHLE, "sthle", "sth", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stw [$dstle+$offset16],$imm32 */
- {
- BPF_INSN_STWLE, "stwle", "stw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stdw [$dstle+$offset16],$imm32 */
- {
- BPF_INSN_STDWLE, "stdwle", "stdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* stb [$dstbe+$offset16],$imm32 */
- {
- BPF_INSN_STBBE, "stbbe", "stb", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* sth [$dstbe+$offset16],$imm32 */
- {
- BPF_INSN_STHBE, "sthbe", "sth", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stw [$dstbe+$offset16],$imm32 */
- {
- BPF_INSN_STWBE, "stwbe", "stw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* stdw [$dstbe+$offset16],$imm32 */
- {
- BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jeq $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JEQILE, "jeqile", "jeq", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jeq $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jeq32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jeq32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jgt $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JGTILE, "jgtile", "jgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jgt $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jgt32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jgt32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jge $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JGEILE, "jgeile", "jge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jge $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JGERLE, "jgerle", "jge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jge32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jge32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jlt $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JLTILE, "jltile", "jlt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jlt $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jlt32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jlt32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jle $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JLEILE, "jleile", "jle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jle $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JLERLE, "jlerle", "jle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jle32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jle32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jset $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSETILE, "jsetile", "jset", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jset $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jset32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jset32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jne $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JNEILE, "jneile", "jne", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jne $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JNERLE, "jnerle", "jne", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jne32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jne32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsgt $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsgt $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsgt32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsgt32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsge $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsge $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsge32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsge32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jslt $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jslt $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jslt32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jslt32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsle $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsle $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsle32 $dstle,$imm32,$disp16 */
- {
- BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jsle32 $dstle,$srcle,$disp16 */
- {
- BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* jeq $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jeq $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jeq32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jeq32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jgt $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jgt $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jgt32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jgt32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jge $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jge $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JGERBE, "jgerbe", "jge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jge32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jge32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jlt $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jlt $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jlt32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jlt32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jle $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JLEIBE, "jleibe", "jle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jle $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JLERBE, "jlerbe", "jle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jle32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jle32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jset $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jset $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jset32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jset32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jne $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JNEIBE, "jneibe", "jne", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jne $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JNERBE, "jnerbe", "jne", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jne32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jne32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsgt $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsgt $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsgt32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsgt32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsge $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsge $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsge32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsge32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jslt $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jslt $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jslt32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jslt32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsle $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsle $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsle32 $dstbe,$imm32,$disp16 */
- {
- BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* jsle32 $dstbe,$srcbe,$disp16 */
- {
- BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* call $disp32 */
- {
- BPF_INSN_CALLLE, "callle", "call", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* call $disp32 */
- {
- BPF_INSN_CALLBE, "callbe", "call", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* call $dstle */
- {
- BPF_INSN_CALLRLE, "callrle", "call", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
- },
-/* call $dstbe */
- {
- BPF_INSN_CALLRBE, "callrbe", "call", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
- },
-/* ja $disp16 */
- {
- BPF_INSN_JA, "ja", "ja", 64,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-/* exit */
- {
- BPF_INSN_EXIT, "exit", "exit", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-/* xadddw [$dstle+$offset16],$srcle */
- {
- BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* xaddw [$dstle+$offset16],$srcle */
- {
- BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
- },
-/* xadddw [$dstbe+$offset16],$srcbe */
- {
- BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* xaddw [$dstbe+$offset16],$srcbe */
- {
- BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
- },
-/* brkpt */
- {
- BPF_INSN_BRKPT, "brkpt", "brkpt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
- },
-};
-
-#undef OP
-#undef A
-
-/* Initialize anything needed to be done once, before any cpu_open call. */
-
-static void
-init_tables (void)
-{
-}
-
-#ifndef opcodes_error_handler
-#define opcodes_error_handler(...) \
- fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
-#endif
-
-static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
-static void build_hw_table (CGEN_CPU_TABLE *);
-static void build_ifield_table (CGEN_CPU_TABLE *);
-static void build_operand_table (CGEN_CPU_TABLE *);
-static void build_insn_table (CGEN_CPU_TABLE *);
-static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
-
-/* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name. */
-
-static const CGEN_MACH *
-lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
-{
- while (table->name)
- {
- if (strcmp (name, table->bfd_name) == 0)
- return table;
- ++table;
- }
- return NULL;
-}
-
-/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
-
-static void
-build_hw_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- int machs = cd->machs;
- const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
- /* MAX_HW is only an upper bound on the number of selected entries.
- However each entry is indexed by it's enum so there can be holes in
- the table. */
- const CGEN_HW_ENTRY **selected =
- (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
-
- cd->hw_table.init_entries = init;
- cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
- memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
- /* ??? For now we just use machs to determine which ones we want. */
- for (i = 0; init[i].name != NULL; ++i)
- if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
- & machs)
- selected[init[i].type] = &init[i];
- cd->hw_table.entries = selected;
- cd->hw_table.num_entries = MAX_HW;
-}
-
-/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
-
-static void
-build_ifield_table (CGEN_CPU_TABLE *cd)
-{
- cd->ifld_table = & bpf_cgen_ifld_table[0];
-}
-
-/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
-
-static void
-build_operand_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- int machs = cd->machs;
- const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
- /* MAX_OPERANDS is only an upper bound on the number of selected entries.
- However each entry is indexed by it's enum so there can be holes in
- the table. */
- const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
-
- cd->operand_table.init_entries = init;
- cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
- memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
- /* ??? For now we just use mach to determine which ones we want. */
- for (i = 0; init[i].name != NULL; ++i)
- if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
- & machs)
- selected[init[i].type] = &init[i];
- cd->operand_table.entries = selected;
- cd->operand_table.num_entries = MAX_OPERANDS;
-}
-
-/* Subroutine of bpf_cgen_cpu_open to build the hardware table.
- ??? This could leave out insns not supported by the specified mach/isa,
- but that would cause errors like "foo only supported by bar" to become
- "unknown insn", so for now we include all insns and require the app to
- do the checking later.
- ??? On the other hand, parsing of such insns may require their hardware or
- operand elements to be in the table [which they mightn't be]. */
-
-static void
-build_insn_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
- CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
-
- memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
- for (i = 0; i < MAX_INSNS; ++i)
- insns[i].base = &ib[i];
- cd->insn_table.init_entries = insns;
- cd->insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->insn_table.num_init_entries = MAX_INSNS;
-}
-
-/* Subroutine of bpf_cgen_cpu_open to rebuild the tables. */
-
-static void
-bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
-{
- int i;
- CGEN_BITSET *isas = cd->isas;
- unsigned int machs = cd->machs;
-
- cd->int_insn_p = CGEN_INT_INSN_P;
-
- /* Data derived from the isa spec. */
-#define UNSET (CGEN_SIZE_UNKNOWN + 1)
- cd->default_insn_bitsize = UNSET;
- cd->base_insn_bitsize = UNSET;
- cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
- cd->max_insn_bitsize = 0;
- for (i = 0; i < MAX_ISAS; ++i)
- if (cgen_bitset_contains (isas, i))
- {
- const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
-
- /* Default insn sizes of all selected isas must be
- equal or we set the result to 0, meaning "unknown". */
- if (cd->default_insn_bitsize == UNSET)
- cd->default_insn_bitsize = isa->default_insn_bitsize;
- else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
- ; /* This is ok. */
- else
- cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
- /* Base insn sizes of all selected isas must be equal
- or we set the result to 0, meaning "unknown". */
- if (cd->base_insn_bitsize == UNSET)
- cd->base_insn_bitsize = isa->base_insn_bitsize;
- else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
- ; /* This is ok. */
- else
- cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
- /* Set min,max insn sizes. */
- if (isa->min_insn_bitsize < cd->min_insn_bitsize)
- cd->min_insn_bitsize = isa->min_insn_bitsize;
- if (isa->max_insn_bitsize > cd->max_insn_bitsize)
- cd->max_insn_bitsize = isa->max_insn_bitsize;
- }
-
- /* Data derived from the mach spec. */
- for (i = 0; i < MAX_MACHS; ++i)
- if (((1 << i) & machs) != 0)
- {
- const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
-
- if (mach->insn_chunk_bitsize != 0)
- {
- if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
- {
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: bpf_cgen_rebuild_tables: "
- "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
- cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
- abort ();
- }
-
- cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
- }
- }
-
- /* Determine which hw elements are used by MACH. */
- build_hw_table (cd);
-
- /* Build the ifield table. */
- build_ifield_table (cd);
-
- /* Determine which operands are used by MACH/ISA. */
- build_operand_table (cd);
-
- /* Build the instruction table. */
- build_insn_table (cd);
-}
-
-/* Initialize a cpu table and return a descriptor.
- It's much like opening a file, and must be the first function called.
- The arguments are a set of (type/value) pairs, terminated with
- CGEN_CPU_OPEN_END.
-
- Currently supported values:
- CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
- CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
- CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
- CGEN_CPU_OPEN_ENDIAN: specify endian choice
- CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
- CGEN_CPU_OPEN_END: terminates arguments
-
- ??? Simultaneous multiple isas might not make sense, but it's not (yet)
- precluded. */
-
-CGEN_CPU_DESC
-bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
-{
- CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
- static int init_p;
- CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
- unsigned int machs = 0; /* 0 = "unspecified" */
- enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
- enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
- va_list ap;
-
- if (! init_p)
- {
- init_tables ();
- init_p = 1;
- }
-
- memset (cd, 0, sizeof (*cd));
-
- va_start (ap, arg_type);
- while (arg_type != CGEN_CPU_OPEN_END)
- {
- switch (arg_type)
- {
- case CGEN_CPU_OPEN_ISAS :
- isas = va_arg (ap, CGEN_BITSET *);
- break;
- case CGEN_CPU_OPEN_MACHS :
- machs = va_arg (ap, unsigned int);
- break;
- case CGEN_CPU_OPEN_BFDMACH :
- {
- const char *name = va_arg (ap, const char *);
- const CGEN_MACH *mach =
- lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
-
- if (mach != NULL)
- machs |= 1 << mach->num;
- break;
- }
- case CGEN_CPU_OPEN_ENDIAN :
- endian = va_arg (ap, enum cgen_endian);
- break;
- case CGEN_CPU_OPEN_INSN_ENDIAN :
- insn_endian = va_arg (ap, enum cgen_endian);
- break;
- default :
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: bpf_cgen_cpu_open: "
- "unsupported argument `%d'"),
- arg_type);
- abort (); /* ??? return NULL? */
- }
- arg_type = va_arg (ap, enum cgen_cpu_open_arg);
- }
- va_end (ap);
-
- /* Mach unspecified means "all". */
- if (machs == 0)
- machs = (1 << MAX_MACHS) - 1;
- /* Base mach is always selected. */
- machs |= 1;
- if (endian == CGEN_ENDIAN_UNKNOWN)
- {
- /* ??? If target has only one, could have a default. */
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: bpf_cgen_cpu_open: no endianness specified"));
- abort ();
- }
-
- cd->isas = cgen_bitset_copy (isas);
- cd->machs = machs;
- cd->endian = endian;
- cd->insn_endian
- = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
-
- /* Table (re)builder. */
- cd->rebuild_tables = bpf_cgen_rebuild_tables;
- bpf_cgen_rebuild_tables (cd);
-
- /* Default to not allowing signed overflow. */
- cd->signed_overflow_ok_p = 0;
-
- return (CGEN_CPU_DESC) cd;
-}
-
-/* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
- MACH_NAME is the bfd name of the mach. */
-
-CGEN_CPU_DESC
-bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
-{
- return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
- CGEN_CPU_OPEN_ENDIAN, endian,
- CGEN_CPU_OPEN_END);
-}
-
-/* Close a cpu table.
- ??? This can live in a machine independent file, but there's currently
- no place to put this file (there's no libcgen). libopcodes is the wrong
- place as some simulator ports use this but they don't use libopcodes. */
-
-void
-bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
-{
- unsigned int i;
- const CGEN_INSN *insns;
-
- if (cd->macro_insn_table.init_entries)
- {
- insns = cd->macro_insn_table.init_entries;
- for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
- if (CGEN_INSN_RX ((insns)))
- regfree (CGEN_INSN_RX (insns));
- }
-
- if (cd->insn_table.init_entries)
- {
- insns = cd->insn_table.init_entries;
- for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
- if (CGEN_INSN_RX (insns))
- regfree (CGEN_INSN_RX (insns));
- }
-
- free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
- free ((CGEN_INSN *) cd->insn_table.init_entries);
- free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
- free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
- free (cd);
-}
-
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* CPU data header for bpf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2023 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef BPF_CPU_H
-#define BPF_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CGEN_ARCH bpf
-
-/* Given symbol S, return bpf_cgen_<S>. */
-#define CGEN_SYM(s) bpf##_cgen_##s
-
-
-/* Selected cpu families. */
-#define HAVE_CPU_BPFBF
-
-#define CGEN_INSN_LSB0_P 1
-
-/* Minimum size of any insn (in bytes). */
-#define CGEN_MIN_INSN_SIZE 8
-
-/* Maximum size of any insn (in bytes). */
-#define CGEN_MAX_INSN_SIZE 16
-
-#define CGEN_INT_INSN_P 0
-
-/* Maximum number of syntax elements in an instruction. */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16
-
-/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
- e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
- we can't hash on everything up to the space. */
-#define CGEN_MNEMONIC_OPERANDS
-
-/* Maximum number of fields in an instruction. */
-#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
-
-/* Enums. */
-
-/* Enum declaration for eBPF instruction codes. */
-typedef enum insn_op_code_alu {
- OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
- , OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
- , OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
- , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_SDIV = 14, OP_CODE_SMOD = 15
- , OP_CODE_JA = 0, OP_CODE_JEQ = 1, OP_CODE_JGT = 2, OP_CODE_JGE = 3
- , OP_CODE_JSET = 4, OP_CODE_JNE = 5, OP_CODE_JSGT = 6, OP_CODE_JSGE = 7
- , OP_CODE_CALL = 8, OP_CODE_EXIT = 9, OP_CODE_JLT = 10, OP_CODE_JLE = 11
- , OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
-} INSN_OP_CODE_ALU;
-
-/* Enum declaration for eBPF instruction source. */
-typedef enum insn_op_src {
- OP_SRC_K, OP_SRC_X
-} INSN_OP_SRC;
-
-/* Enum declaration for eBPF instruction class. */
-typedef enum insn_op_class {
- OP_CLASS_LD, OP_CLASS_LDX, OP_CLASS_ST, OP_CLASS_STX
- , OP_CLASS_ALU, OP_CLASS_JMP, OP_CLASS_JMP32, OP_CLASS_ALU64
-} INSN_OP_CLASS;
-
-/* Enum declaration for eBPF load/store instruction modes. */
-typedef enum insn_op_mode {
- OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3
- , OP_MODE_XADD = 6
-} INSN_OP_MODE;
-
-/* Enum declaration for eBPF load/store instruction sizes. */
-typedef enum insn_op_size {
- OP_SIZE_W, OP_SIZE_H, OP_SIZE_B, OP_SIZE_DW
-} INSN_OP_SIZE;
-
-/* Attributes. */
-
-/* Enum declaration for machine type selection. */
-typedef enum mach_attr {
- MACH_BASE, MACH_BPF, MACH_XBPF, MACH_MAX
-} MACH_ATTR;
-
-/* Enum declaration for instruction set selection. */
-typedef enum isa_attr {
- ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE
- , ISA_MAX
-} ISA_ATTR;
-
-/* Number of architecture variants. */
-#define MAX_ISAS ((int) ISA_MAX)
-#define MAX_MACHS ((int) MACH_MAX)
-
-/* Ifield support. */
-
-/* Ifield attribute indices. */
-
-/* Enum declaration for cgen_ifld attrs. */
-typedef enum cgen_ifld_attr {
- CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
- , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
- , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
-} CGEN_IFLD_ATTR;
-
-/* Number of non-boolean elements in cgen_ifld_attr. */
-#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
-
-/* cgen_ifld attribute accessor macros. */
-#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
-#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
-
-/* Enum declaration for bpf ifield types. */
-typedef enum ifield_type {
- BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC
- , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE
- , BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS
- , BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B
- , BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX
-} IFIELD_TYPE;
-
-#define MAX_IFLD ((int) BPF_F_MAX)
-
-/* Hardware attribute indices. */
-
-/* Enum declaration for cgen_hw attrs. */
-typedef enum cgen_hw_attr {
- CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
- , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
- , CGEN_HW_END_NBOOLS
-} CGEN_HW_ATTR;
-
-/* Number of non-boolean elements in cgen_hw_attr. */
-#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
-
-/* cgen_hw attribute accessor macros. */
-#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
-#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
-#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
-
-/* Enum declaration for bpf hardware types. */
-typedef enum cgen_hw_type {
- HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
- , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64
- , HW_MAX
-} CGEN_HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
-/* Operand attribute indices. */
-
-/* Enum declaration for cgen_operand attrs. */
-typedef enum cgen_operand_attr {
- CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
- , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
- , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
- , CGEN_OPERAND_END_NBOOLS
-} CGEN_OPERAND_ATTR;
-
-/* Number of non-boolean elements in cgen_operand_attr. */
-#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
-
-/* cgen_operand attribute accessor macros. */
-#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
-#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
-
-/* Enum declaration for bpf operand types. */
-typedef enum cgen_operand_type {
- BPF_OPERAND_PC, BPF_OPERAND_DSTLE, BPF_OPERAND_SRCLE, BPF_OPERAND_DSTBE
- , BPF_OPERAND_SRCBE, BPF_OPERAND_DISP16, BPF_OPERAND_DISP32, BPF_OPERAND_IMM32
- , BPF_OPERAND_OFFSET16, BPF_OPERAND_IMM64, BPF_OPERAND_ENDSIZE, BPF_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Number of operands types. */
-#define MAX_OPERANDS 11
-
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 8
-
-/* Insn attribute indices. */
-
-/* Enum declaration for cgen_insn attrs. */
-typedef enum cgen_insn_attr {
- CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
- , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
- , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS
-} CGEN_INSN_ATTR;
-
-/* Number of non-boolean elements in cgen_insn_attr. */
-#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
-
-/* cgen_insn attribute accessor macros. */
-#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
-#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
-#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
-
-/* cgen.h uses things we just defined. */
-#include "opcode/cgen.h"
-
-extern const struct cgen_ifld bpf_cgen_ifld_table[];
-
-/* Attributes. */
-extern const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[];
-extern const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[];
-extern const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[];
-extern const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[];
-
-/* Hardware decls. */
-
-extern CGEN_KEYWORD bpf_cgen_opval_h_gpr;
-
-extern const CGEN_HW_ENTRY bpf_cgen_hw_table[];
-
-
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* BPF_CPU_H */
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Disassembler interface for targets using CGEN. -*- C -*-
- CGEN: Cpu tools GENerator
+/* bpf-dis.c - BPF disassembler.
+ Copyright (C) 2023 Free Software Foundation, Inc.
- THIS FILE IS MACHINE GENERATED WITH CGEN.
- - the resultant file is machine generated, cgen-dis.in isn't
+ Contributed by Oracle Inc.
- Copyright (C) 1996-2023 Free Software Foundation, Inc.
+ This file is part of the GNU binutils.
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
+ This is free software; you can redistribute them and/or modify them
+ under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
#include "disassemble.h"
-#include "bfd.h"
-#include "symcat.h"
#include "libiberty.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
#include "opintl.h"
+#include "opcode/bpf.h"
-/* Default text to print if an instruction isn't recognized. */
-#define UNKNOWN_INSN_MSG _("*unknown*")
-
-static void print_normal
- (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
-static void print_address
- (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
-static void print_keyword
- (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
-static void print_insn_normal
- (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
-static int print_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
-static int default_print_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
-static int read_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
- unsigned long *);
-\f
-/* -- disassembler routines inserted here. */
-
-/* -- dis.c */
-
-/* We need to customize the disassembler a bit:
- - Use 8 bytes per line by default.
-*/
-
-#define CGEN_PRINT_INSN bpf_print_insn
-
-static int
-bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
- int buflen;
- int status;
-
- info->bytes_per_chunk = 1;
- info->bytes_per_line = 8;
-
- /* Attempt to read the base part of the insn. */
- buflen = cd->base_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- /* Try again with the minimum part, if min < base. */
- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
- {
- buflen = cd->min_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
- }
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- return print_insn (cd, pc, info, buf, buflen);
-}
+#include <string.h>
+#include <inttypes.h>
-/* Signed immediates should be printed in hexadecimal. */
+/* This disassembler supports two different syntaxes for BPF assembly.
+ One is called "normal" and has the typical form for assembly
+ languages, with mnemonics and the like. The othe is called
+ "pseudoc" and looks like C. */
-static void
-print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- int64_t value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+enum bpf_dialect
{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- if (value <= 9)
- (*info->fprintf_func) (info->stream, "%" PRId64, value);
- else
- (*info->fprintf_func) (info->stream, "%#" PRIx64, value);
-
- /* This is to avoid -Wunused-function for print_normal. */
- if (0)
- print_normal (cd, dis_info, value, attrs, pc, length);
-}
-
-/* Endianness bit sizes should be printed in decimal. */
-
-static void
-print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- unsigned long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
- (*info->fprintf_func) (info->stream, "%lu", value);
-}
-
-\f
-/* -- */
-
-void bpf_cgen_print_operand
- (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
+ BPF_DIALECT_NORMAL,
+ BPF_DIALECT_PSEUDOC
+};
-/* Main entry point for printing operands.
- XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
- of dis-asm.h on cgen.h.
+/* Global configuration for the disassembler. */
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
+static enum bpf_dialect asm_dialect = BPF_DIALECT_NORMAL;
+static int asm_bpf_version = BPF_V4;
+static int asm_obase = 10;
- This function could be moved into `print_insn_normal', but keeping it
- separate makes clear the interface between `print_insn_normal' and each of
- the handlers. */
+/* Print BPF specific command-line options. */
void
-bpf_cgen_print_operand (CGEN_CPU_DESC cd,
- int opindex,
- void * xinfo,
- CGEN_FIELDS *fields,
- void const *attrs ATTRIBUTE_UNUSED,
- bfd_vma pc,
- int length)
+print_bpf_disassembler_options (FILE *stream)
{
- disassemble_info *info = (disassemble_info *) xinfo;
-
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
- break;
- case BPF_OPERAND_DISP32 :
- print_normal (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
- break;
- case BPF_OPERAND_DSTBE :
- print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstbe, 0);
- break;
- case BPF_OPERAND_DSTLE :
- print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstle, 0);
- break;
- case BPF_OPERAND_ENDSIZE :
- print_endsize (cd, info, fields->f_imm32, 0, pc, length);
- break;
- case BPF_OPERAND_IMM32 :
- print_immediate (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case BPF_OPERAND_IMM64 :
- print_immediate (cd, info, fields->f_imm64, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
- break;
- case BPF_OPERAND_OFFSET16 :
- print_immediate (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case BPF_OPERAND_SRCBE :
- print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcbe, 0);
- break;
- case BPF_OPERAND_SRCLE :
- print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcle, 0);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while printing insn"),
- opindex);
- abort ();
- }
+ fprintf (stream, _("\n\
+The following BPF specific disassembler options are supported for use\n\
+with the -M switch (multiple options should be separated by commas):\n"));
+ fprintf (stream, "\n");
+ fprintf (stream, _("\
+ pseudoc Use pseudo-c syntax.\n\
+ v1,v2,v3,v4,xbpf Version of the BPF ISA to use.\n\
+ hex,oct,dec Output numerical base for immediates.\n"));
}
-cgen_print_fn * const bpf_cgen_print_handlers[] =
-{
- print_insn_normal,
-};
-
-
-void
-bpf_cgen_init_dis (CGEN_CPU_DESC cd)
-{
- bpf_cgen_init_opcode_table (cd);
- bpf_cgen_init_ibld_table (cd);
- cd->print_handlers = & bpf_cgen_print_handlers[0];
- cd->print_operand = bpf_cgen_print_operand;
-}
-
-\f
-/* Default print handler. */
+/* Parse BPF specific command-line options. */
static void
-print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- long value,
- unsigned int attrs,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+parse_bpf_dis_option (const char *option)
{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* nothing to do */
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
- (*info->fprintf_func) (info->stream, "%ld", value);
+ if (strcmp (option, "pseudoc") == 0)
+ asm_dialect = BPF_DIALECT_PSEUDOC;
+ else if (strcmp (option, "v1") == 0)
+ asm_bpf_version = BPF_V1;
+ else if (strcmp (option, "v2") == 0)
+ asm_bpf_version = BPF_V2;
+ else if (strcmp (option, "v3") == 0)
+ asm_bpf_version = BPF_V3;
+ else if (strcmp (option, "v4") == 0)
+ asm_bpf_version = BPF_V4;
+ else if (strcmp (option, "xbpf") == 0)
+ asm_bpf_version = BPF_XBPF;
+ else if (strcmp (option, "hex") == 0)
+ asm_obase = 16;
+ else if (strcmp (option, "oct") == 0)
+ asm_obase = 8;
+ else if (strcmp (option, "dec") == 0)
+ asm_obase = 10;
else
- (*info->fprintf_func) (info->stream, "0x%lx", value);
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
}
-/* Default address handler. */
-
static void
-print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- bfd_vma value,
- unsigned int attrs,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+parse_bpf_dis_options (const char *opts_in)
{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* Nothing to do. */
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
- (*info->print_address_func) (value, info);
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
- (*info->print_address_func) (value, info);
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
- (*info->fprintf_func) (info->stream, "%ld", (long) value);
- else
- (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
-}
+ char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
-/* Keyword print handler. */
-
-static void
-print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- CGEN_KEYWORD *keyword_table,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
- const CGEN_KEYWORD_ENTRY *ke;
+ for ( ; opt_end != NULL; opt = opt_end + 1)
+ {
+ if ((opt_end = strchr (opt, ',')) != NULL)
+ *opt_end = 0;
+ parse_bpf_dis_option (opt);
+ }
- ke = cgen_keyword_lookup_value (keyword_table, value);
- if (ke != NULL)
- (*info->fprintf_func) (info->stream, "%s", ke->name);
- else
- (*info->fprintf_func) (info->stream, "???");
+ free (opts);
}
-\f
-/* Default insn printer.
- DIS_INFO is defined as `void *' so the disassembler needn't know anything
- about disassemble_info. */
+/* Auxiliary function used in print_insn_bpf below. */
static void
-print_insn_normal (CGEN_CPU_DESC cd,
- void *dis_info,
- const CGEN_INSN *insn,
- CGEN_FIELDS *fields,
- bfd_vma pc,
- int length)
+print_register (disassemble_info *info,
+ const char *tag, uint8_t regno)
{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- disassemble_info *info = (disassemble_info *) dis_info;
- const CGEN_SYNTAX_CHAR_TYPE *syn;
-
- CGEN_INIT_PRINT (cd);
-
- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
- {
- if (CGEN_SYNTAX_MNEMONIC_P (*syn))
- {
- (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
- continue;
- }
- if (CGEN_SYNTAX_CHAR_P (*syn))
- {
- (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
- continue;
- }
-
- /* We have an operand. */
- bpf_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
- fields, CGEN_INSN_ATTRS (insn), pc, length);
- }
+ const char *fmt
+ = (asm_dialect == BPF_DIALECT_NORMAL
+ ? "%%r%d"
+ : ((*(tag + 2) == 'w')
+ ? "w%d"
+ : "r%d"));
+
+ (*info->fprintf_styled_func) (info->stream, dis_style_register, fmt, regno);
}
-\f
-/* Subroutine of print_insn. Reads an insn into the given buffers and updates
- the extract info.
- Returns 0 if all is well, non-zero otherwise. */
-
-static int
-read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- bfd_vma pc,
- disassemble_info *info,
- bfd_byte *buf,
- int buflen,
- CGEN_EXTRACT_INFO *ex_info,
- unsigned long *insn_value)
-{
- int status = (*info->read_memory_func) (pc, buf, buflen, info);
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- ex_info->dis_info = info;
- ex_info->valid = (1 << buflen) - 1;
- ex_info->insn_bytes = buf;
-
- *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
- return 0;
-}
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
-/* Utility to print an insn.
- BUF is the base part of the insn, target byte order, BUFLEN bytes long.
- The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occurs fetching data (memory_error_func will have
- been called). */
-
-static int
-print_insn (CGEN_CPU_DESC cd,
- bfd_vma pc,
- disassemble_info *info,
- bfd_byte *buf,
- unsigned int buflen)
+int
+print_insn_bpf (bfd_vma pc, disassemble_info *info)
{
- CGEN_INSN_INT insn_value;
- const CGEN_INSN_LIST *insn_list;
- CGEN_EXTRACT_INFO ex_info;
- int basesize;
-
- /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
- basesize = cd->base_insn_bitsize < buflen * 8 ?
- cd->base_insn_bitsize : buflen * 8;
- insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
-
-
- /* Fill in ex_info fields like read_insn would. Don't actually call
- read_insn, since the incoming buffer is already read (and possibly
- modified a la m32r). */
- ex_info.valid = (1 << buflen) - 1;
- ex_info.dis_info = info;
- ex_info.insn_bytes = buf;
-
- /* The instructions are stored in hash lists.
- Pick the first one and keep trying until we find the right one. */
-
- insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
- while (insn_list != NULL)
+ int insn_size = 8, status;
+ bfd_byte insn_bytes[16];
+ bpf_insn_word word = 0;
+ const struct bpf_opcode *insn = NULL;
+ enum bpf_endian endian = (info->endian == BFD_ENDIAN_LITTLE
+ ? BPF_ENDIAN_LITTLE : BPF_ENDIAN_BIG);
+
+ /* Handle bpf-specific command-line options. */
+ if (info->disassembler_options != NULL)
{
- const CGEN_INSN *insn = insn_list->insn;
- CGEN_FIELDS fields;
- int length;
- unsigned long insn_value_cropped;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* Not needed as insn shouldn't be in hash lists if not supported. */
- /* Supported by this cpu? */
- if (! bpf_cgen_insn_supported (cd, insn))
- {
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
- continue;
- }
-#endif
-
- /* Basic bit mask must be correct. */
- /* ??? May wish to allow target to defer this check until the extract
- handler. */
-
- /* Base size may exceed this instruction's size. Extract the
- relevant part from the buffer. */
- if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
- info->endian == BFD_ENDIAN_BIG);
- else
- insn_value_cropped = insn_value;
-
- if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
- == CGEN_INSN_BASE_VALUE (insn))
- {
- /* Printing is handled in two passes. The first pass parses the
- machine insn and extracts the fields. The second pass prints
- them. */
-
- /* Make sure the entire insn is loaded into insn_value, if it
- can fit. */
- if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- {
- unsigned long full_insn_value;
- int rc = read_insn (cd, pc, info, buf,
- CGEN_INSN_BITSIZE (insn) / 8,
- & ex_info, & full_insn_value);
- if (rc != 0)
- return rc;
- length = CGEN_EXTRACT_FN (cd, insn)
- (cd, insn, &ex_info, full_insn_value, &fields, pc);
- }
- else
- length = CGEN_EXTRACT_FN (cd, insn)
- (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
-
- /* Length < 0 -> error. */
- if (length < 0)
- return length;
- if (length > 0)
- {
- CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
- /* Length is in bits, result is in bytes. */
- return length / 8;
- }
- }
-
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ parse_bpf_dis_options (info->disassembler_options);
+ /* Avoid repeteadly parsing the options. */
+ info->disassembler_options = NULL;
}
- return 0;
-}
-
-/* Default value for CGEN_PRINT_INSN.
- The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
-
-#ifndef CGEN_PRINT_INSN
-#define CGEN_PRINT_INSN default_print_insn
-#endif
-
-static int
-default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
- int buflen;
- int status;
-
- /* Attempt to read the base part of the insn. */
- buflen = cd->base_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- /* Try again with the minimum part, if min < base. */
- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
- {
- buflen = cd->min_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
- }
+ /* Print eight bytes per line. */
+ info->bytes_per_chunk = 1;
+ info->bytes_per_line = 8;
+ /* Read an instruction word. */
+ status = (*info->read_memory_func) (pc, insn_bytes, 8, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
+ word = (bpf_insn_word) bfd_getb64 (insn_bytes);
- return print_insn (cd, pc, info, buf, buflen);
-}
+ /* Try to match an instruction with it. */
+ insn = bpf_match_insn (word, endian, asm_bpf_version);
-/* Main entry point.
- Print one instruction from PC on INFO->STREAM.
- Return the size of the instruction (in bytes). */
-
-typedef struct cpu_desc_list
-{
- struct cpu_desc_list *next;
- CGEN_BITSET *isa;
- int mach;
- int endian;
- int insn_endian;
- CGEN_CPU_DESC cd;
-} cpu_desc_list;
-
-int
-print_insn_bpf (bfd_vma pc, disassemble_info *info)
-{
- static cpu_desc_list *cd_list = 0;
- cpu_desc_list *cl = 0;
- static CGEN_CPU_DESC cd = 0;
- static CGEN_BITSET *prev_isa;
- static int prev_mach;
- static int prev_endian;
- static int prev_insn_endian;
- int length;
- CGEN_BITSET *isa;
- int mach;
- int endian = (info->endian == BFD_ENDIAN_BIG
- ? CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
- int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
- ? CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
- enum bfd_architecture arch;
-
- /* ??? gdb will set mach but leave the architecture as "unknown" */
-#ifndef CGEN_BFD_ARCH
-#define CGEN_BFD_ARCH bfd_arch_bpf
-#endif
- arch = info->arch;
- if (arch == bfd_arch_unknown)
- arch = CGEN_BFD_ARCH;
-
- /* There's no standard way to compute the machine or isa number
- so we leave it to the target. */
-#ifdef CGEN_COMPUTE_MACH
- mach = CGEN_COMPUTE_MACH (info);
-#else
- mach = info->mach;
-#endif
-
-#ifdef CGEN_COMPUTE_ISA
- {
- static CGEN_BITSET *permanent_isa;
-
- if (!permanent_isa)
- permanent_isa = cgen_bitset_create (MAX_ISAS);
- isa = permanent_isa;
- cgen_bitset_clear (isa);
- cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
- }
-#else
- isa = info->private_data;
-#endif
-
- /* If we've switched cpu's, try to find a handle we've used before */
- if (cd
- && (cgen_bitset_compare (isa, prev_isa) != 0
- || mach != prev_mach
- || endian != prev_endian))
+ /* Print it out. */
+ if (insn)
{
- cd = 0;
- for (cl = cd_list; cl; cl = cl->next)
- {
- if (cgen_bitset_compare (cl->isa, isa) == 0 &&
- cl->mach == mach &&
- cl->endian == endian)
- {
- cd = cl->cd;
- prev_isa = cd->isas;
- break;
- }
- }
- }
+ const char *insn_tmpl
+ = asm_dialect == BPF_DIALECT_NORMAL ? insn->normal : insn->pseudoc;
+ const char *p = insn_tmpl;
- /* If we haven't initialized yet, initialize the opcode table. */
- if (! cd)
- {
- const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
- const char *mach_name;
-
- if (!arch_type)
- abort ();
- mach_name = arch_type->printable_name;
-
- prev_isa = cgen_bitset_copy (isa);
- prev_mach = mach;
- prev_endian = endian;
- prev_insn_endian = insn_endian;
- cd = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
- CGEN_CPU_OPEN_BFDMACH, mach_name,
- CGEN_CPU_OPEN_ENDIAN, prev_endian,
- CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
- CGEN_CPU_OPEN_END);
- if (!cd)
- abort ();
-
- /* Save this away for future reference. */
- cl = xmalloc (sizeof (struct cpu_desc_list));
- cl->cd = cd;
- cl->isa = prev_isa;
- cl->mach = mach;
- cl->endian = endian;
- cl->next = cd_list;
- cd_list = cl;
-
- bpf_cgen_init_dis (cd);
+ /* Print the template contents completed with the instruction
+ operands. */
+ for (p = insn_tmpl; *p != '\0';)
+ {
+ switch (*p)
+ {
+ case ' ':
+ /* Single space prints to nothing. */
+ p += 1;
+ break;
+ case '%':
+ if (*(p + 1) == '%')
+ {
+ (*info->fprintf_styled_func) (info->stream, dis_style_text, "%%");
+ p += 2;
+ }
+ else if (*(p + 1) == 'w' || *(p + 1) == 'W')
+ {
+ /* %W prints to a single space. */
+ (*info->fprintf_styled_func) (info->stream, dis_style_text, " ");
+ p += 2;
+ }
+ else if (strncmp (p, "%dr", 3) == 0)
+ {
+ print_register (info, p, bpf_extract_dst (word, endian));
+ p += 3;
+ }
+ else if (strncmp (p, "%sr", 3) == 0)
+ {
+ print_register (info, p, bpf_extract_src (word, endian));
+ p += 3;
+ }
+ else if (strncmp (p, "%dw", 3) == 0)
+ {
+ print_register (info, p, bpf_extract_dst (word, endian));
+ p += 3;
+ }
+ else if (strncmp (p, "%sw", 3) == 0)
+ {
+ print_register (info, p, bpf_extract_src (word, endian));
+ p += 3;
+ }
+ else if (strncmp (p, "%i32", 4) == 0
+ || strncmp (p, "%d32", 4) == 0
+ || strncmp (p, "%I32", 4) == 0)
+ {
+ int32_t imm32 = bpf_extract_imm32 (word, endian);
+
+ if (p[1] == 'I')
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%s",
+ asm_obase != 10 || imm32 > 0 ? "+" : "");
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ asm_obase == 10 ? "%" PRIi32
+ : asm_obase == 8 ? "%" PRIo32
+ : "0x%" PRIx32,
+ imm32);
+ p += 4;
+ }
+ else if (strncmp (p, "%o16", 4) == 0
+ || strncmp (p, "%d16", 4) == 0)
+ {
+ int16_t offset16 = bpf_extract_offset16 (word, endian);
+
+ if (p[1] == 'o')
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%s",
+ asm_obase != 10 || offset16 > 0 ? "+" : "");
+ if (asm_obase == 16 || asm_obase == 8)
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ asm_obase == 8 ? "0%" PRIo16 : "0x%" PRIx16,
+ (uint16_t) offset16);
+ else
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%" PRIi16, offset16);
+ p += 4;
+ }
+ else if (strncmp (p, "%i64", 4) == 0)
+ {
+ bpf_insn_word word2 = 0;
+
+ status = (*info->read_memory_func) (pc + 8, insn_bytes + 8,
+ 8, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc + 8, info);
+ return -1;
+ }
+ word2 = (bpf_insn_word) bfd_getb64 (insn_bytes + 8);
+
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ asm_obase == 10 ? "%" PRIi64
+ : asm_obase == 8 ? "0%" PRIo64
+ : "0x%" PRIx64,
+ bpf_extract_imm64 (word, word2, endian));
+ insn_size = 16;
+ p += 4;
+ }
+ else
+ {
+ /* xgettext:c-format */
+ opcodes_error_handler (_("# internal error, unknown tag in opcode template (%s)"),
+ insn_tmpl);
+ return -1;
+ }
+ break;
+ default:
+ /* Any other character is printed literally. */
+ (*info->fprintf_styled_func) (info->stream, dis_style_text, "%c", *p);
+ p += 1;
+ }
+ }
}
+ else
+ (*info->fprintf_styled_func) (info->stream, dis_style_text, "<unknown>");
- /* We try to have as much common code as possible.
- But at this point some targets need to take over. */
- /* ??? Some targets may need a hook elsewhere. Try to avoid this,
- but if not possible try to move this hook elsewhere rather than
- have two hooks. */
- length = CGEN_PRINT_INSN (cd, pc, info);
- if (length > 0)
- return length;
- if (length < 0)
- return -1;
-
- (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- return cd->default_insn_bitsize / 8;
+ return insn_size;
}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Instruction building/extraction support for bpf. -*- C -*-
-
- THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- - the resultant file is machine generated, cgen-ibld.in isn't
-
- Copyright (C) 1996-2023 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "dis-asm.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
-#include "cgen/basic-modes.h"
-#include "opintl.h"
-#include "safe-ctype.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
-#define max(a,b) ((a) > (b) ? (a) : (b))
-
-/* Used by the ifield rtx function. */
-#define FLD(f) (fields->f)
-
-static const char * insert_normal
- (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
- unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
-static const char * insert_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *,
- CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
-static int extract_normal
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
- unsigned int, unsigned int, unsigned int, unsigned int,
- unsigned int, unsigned int, bfd_vma, long *);
-static int extract_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
- CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
-#if CGEN_INT_INSN_P
-static void put_insn_int_value
- (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
-#endif
-#if ! CGEN_INT_INSN_P
-static CGEN_INLINE void insert_1
- (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
-static CGEN_INLINE int fill_cache
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
-static CGEN_INLINE long extract_1
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
-#endif
-\f
-/* Operand insertion. */
-
-#if ! CGEN_INT_INSN_P
-
-/* Subroutine of insert_normal. */
-
-static CGEN_INLINE void
-insert_1 (CGEN_CPU_DESC cd,
- unsigned long value,
- int start,
- int length,
- int word_length,
- unsigned char *bufp)
-{
- unsigned long x, mask;
- int shift;
-
- x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
-
- /* Written this way to avoid undefined behaviour. */
- mask = (1UL << (length - 1) << 1) - 1;
- if (CGEN_INSN_LSB0_P)
- shift = (start + 1) - length;
- else
- shift = (word_length - (start + length));
- x = (x & ~(mask << shift)) | ((value & mask) << shift);
-
- cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
-}
-
-#endif /* ! CGEN_INT_INSN_P */
-
-/* Default insertion routine.
-
- ATTRS is a mask of the boolean attributes.
- WORD_OFFSET is the offset in bits from the start of the insn of the value.
- WORD_LENGTH is the length of the word in bits in which the value resides.
- START is the starting bit number in the word, architecture origin.
- LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn in bits.
-
- The result is an error message or NULL if success. */
-
-/* ??? This duplicates functionality with bfd's howto table and
- bfd_install_relocation. */
-/* ??? This doesn't handle bfd_vma's. Create another function when
- necessary. */
-
-static const char *
-insert_normal (CGEN_CPU_DESC cd,
- long value,
- unsigned int attrs,
- unsigned int word_offset,
- unsigned int start,
- unsigned int length,
- unsigned int word_length,
- unsigned int total_length,
- CGEN_INSN_BYTES_PTR buffer)
-{
- static char errbuf[100];
- unsigned long mask;
-
- /* If LENGTH is zero, this operand doesn't contribute to the value. */
- if (length == 0)
- return NULL;
-
- /* Written this way to avoid undefined behaviour. */
- mask = (1UL << (length - 1) << 1) - 1;
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- /* For architectures with insns smaller than the base-insn-bitsize,
- word_length may be too big. */
- if (cd->min_insn_bitsize < cd->base_insn_bitsize)
- {
- if (word_offset == 0
- && word_length > total_length)
- word_length = total_length;
- }
-
- /* Ensure VALUE will fit. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
- {
- long minval = - (1UL << (length - 1));
- unsigned long maxval = mask;
-
- if ((value > 0 && (unsigned long) value > maxval)
- || value < minval)
- {
- /* xgettext:c-format */
- sprintf (errbuf,
- _("operand out of range (%ld not between %ld and %lu)"),
- value, minval, maxval);
- return errbuf;
- }
- }
- else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
- {
- unsigned long maxval = mask;
- unsigned long val = (unsigned long) value;
-
- /* For hosts with a word size > 32 check to see if value has been sign
- extended beyond 32 bits. If so then ignore these higher sign bits
- as the user is attempting to store a 32-bit signed value into an
- unsigned 32-bit field which is allowed. */
- if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
- val &= 0xFFFFFFFF;
-
- if (val > maxval)
- {
- /* xgettext:c-format */
- sprintf (errbuf,
- _("operand out of range (0x%lx not between 0 and 0x%lx)"),
- val, maxval);
- return errbuf;
- }
- }
- else
- {
- if (! cgen_signed_overflow_ok_p (cd))
- {
- long minval = - (1UL << (length - 1));
- long maxval = (1UL << (length - 1)) - 1;
-
- if (value < minval || value > maxval)
- {
- sprintf
- /* xgettext:c-format */
- (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
- value, minval, maxval);
- return errbuf;
- }
- }
- }
-
-#if CGEN_INT_INSN_P
-
- {
- int shift_within_word, shift_to_word, shift;
-
- /* How to shift the value to BIT0 of the word. */
- shift_to_word = total_length - (word_offset + word_length);
-
- /* How to shift the value to the field within the word. */
- if (CGEN_INSN_LSB0_P)
- shift_within_word = start + 1 - length;
- else
- shift_within_word = word_length - start - length;
-
- /* The total SHIFT, then mask in the value. */
- shift = shift_to_word + shift_within_word;
- *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
- }
-
-#else /* ! CGEN_INT_INSN_P */
-
- {
- unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
-
- insert_1 (cd, value, start, length, word_length, bufp);
- }
-
-#endif /* ! CGEN_INT_INSN_P */
-
- return NULL;
-}
-
-/* Default insn builder (insert handler).
- The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
- that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
- recorded in host byte order, otherwise BUFFER is an array of bytes
- and the value is recorded in target byte order).
- The result is an error message or NULL if success. */
-
-static const char *
-insert_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN * insn,
- CGEN_FIELDS * fields,
- CGEN_INSN_BYTES_PTR buffer,
- bfd_vma pc)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- unsigned long value;
- const CGEN_SYNTAX_CHAR_TYPE * syn;
-
- CGEN_INIT_INSERT (cd);
- value = CGEN_INSN_BASE_VALUE (insn);
-
- /* If we're recording insns as numbers (rather than a string of bytes),
- target byte order handling is deferred until later. */
-
-#if CGEN_INT_INSN_P
-
- put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
- CGEN_FIELDS_BITSIZE (fields), value);
-
-#else
-
- cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
- (unsigned) CGEN_FIELDS_BITSIZE (fields)),
- value, cd->insn_endian);
-
-#endif /* ! CGEN_INT_INSN_P */
-
- /* ??? It would be better to scan the format's fields.
- Still need to be able to insert a value based on the operand though;
- e.g. storing a branch displacement that got resolved later.
- Needs more thought first. */
-
- for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
- {
- const char *errmsg;
-
- if (CGEN_SYNTAX_CHAR_P (* syn))
- continue;
-
- errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
- fields, buffer, pc);
- if (errmsg)
- return errmsg;
- }
-
- return NULL;
-}
-
-#if CGEN_INT_INSN_P
-/* Cover function to store an insn value into an integral insn. Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
-
-static void
-put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- CGEN_INSN_BYTES_PTR buf,
- int length,
- int insn_length,
- CGEN_INSN_INT value)
-{
- /* For architectures with insns smaller than the base-insn-bitsize,
- length may be too big. */
- if (length > insn_length)
- *buf = value;
- else
- {
- int shift = insn_length - length;
- /* Written this way to avoid undefined behaviour. */
- CGEN_INSN_INT mask = length == 0 ? 0 : (1UL << (length - 1) << 1) - 1;
-
- *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
- }
-}
-#endif
-\f
-/* Operand extraction. */
-
-#if ! CGEN_INT_INSN_P
-
-/* Subroutine of extract_normal.
- Ensure sufficient bytes are cached in EX_INFO.
- OFFSET is the offset in bytes from the start of the insn of the value.
- BYTES is the length of the needed value.
- Returns 1 for success, 0 for failure. */
-
-static CGEN_INLINE int
-fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- CGEN_EXTRACT_INFO *ex_info,
- int offset,
- int bytes,
- bfd_vma pc)
-{
- /* It's doubtful that the middle part has already been fetched so
- we don't optimize that case. kiss. */
- unsigned int mask;
- disassemble_info *info = (disassemble_info *) ex_info->dis_info;
-
- /* First do a quick check. */
- mask = (1 << bytes) - 1;
- if (((ex_info->valid >> offset) & mask) == mask)
- return 1;
-
- /* Search for the first byte we need to read. */
- for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
- if (! (mask & ex_info->valid))
- break;
-
- if (bytes)
- {
- int status;
-
- pc += offset;
- status = (*info->read_memory_func)
- (pc, ex_info->insn_bytes + offset, bytes, info);
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return 0;
- }
-
- ex_info->valid |= ((1 << bytes) - 1) << offset;
- }
-
- return 1;
-}
-
-/* Subroutine of extract_normal. */
-
-static CGEN_INLINE long
-extract_1 (CGEN_CPU_DESC cd,
- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
- int start,
- int length,
- int word_length,
- unsigned char *bufp,
- bfd_vma pc ATTRIBUTE_UNUSED)
-{
- unsigned long x;
- int shift;
-
- x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
-
- if (CGEN_INSN_LSB0_P)
- shift = (start + 1) - length;
- else
- shift = (word_length - (start + length));
- return x >> shift;
-}
-
-#endif /* ! CGEN_INT_INSN_P */
-
-/* Default extraction routine.
-
- INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
- or sometimes less for cases like the m32r where the base insn size is 32
- but some insns are 16 bits.
- ATTRS is a mask of the boolean attributes. We only need `SIGNED',
- but for generality we take a bitmask of all of them.
- WORD_OFFSET is the offset in bits from the start of the insn of the value.
- WORD_LENGTH is the length of the word in bits in which the value resides.
- START is the starting bit number in the word, architecture origin.
- LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn in bits.
-
- Returns 1 for success, 0 for failure. */
-
-/* ??? The return code isn't properly used. wip. */
-
-/* ??? This doesn't handle bfd_vma's. Create another function when
- necessary. */
-
-static int
-extract_normal (CGEN_CPU_DESC cd,
-#if ! CGEN_INT_INSN_P
- CGEN_EXTRACT_INFO *ex_info,
-#else
- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
-#endif
- CGEN_INSN_INT insn_value,
- unsigned int attrs,
- unsigned int word_offset,
- unsigned int start,
- unsigned int length,
- unsigned int word_length,
- unsigned int total_length,
-#if ! CGEN_INT_INSN_P
- bfd_vma pc,
-#else
- bfd_vma pc ATTRIBUTE_UNUSED,
-#endif
- long *valuep)
-{
- long value, mask;
-
- /* If LENGTH is zero, this operand doesn't contribute to the value
- so give it a standard value of zero. */
- if (length == 0)
- {
- *valuep = 0;
- return 1;
- }
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- /* For architectures with insns smaller than the insn-base-bitsize,
- word_length may be too big. */
- if (cd->min_insn_bitsize < cd->base_insn_bitsize)
- {
- if (word_offset + word_length > total_length)
- word_length = total_length - word_offset;
- }
-
- /* Does the value reside in INSN_VALUE, and at the right alignment? */
-
- if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
- {
- if (CGEN_INSN_LSB0_P)
- value = insn_value >> ((word_offset + start + 1) - length);
- else
- value = insn_value >> (total_length - ( word_offset + start + length));
- }
-
-#if ! CGEN_INT_INSN_P
-
- else
- {
- unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
- {
- *valuep = 0;
- return 0;
- }
-
- value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
- }
-
-#endif /* ! CGEN_INT_INSN_P */
-
- /* Written this way to avoid undefined behaviour. */
- mask = (1UL << (length - 1) << 1) - 1;
-
- value &= mask;
- /* sign extend? */
- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
- && (value & (1UL << (length - 1))))
- value |= ~mask;
-
- *valuep = value;
-
- return 1;
-}
-
-/* Default insn extractor.
-
- INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
- The extracted fields are stored in FIELDS.
- EX_INFO is used to handle reading variable length insns.
- Return the length of the insn in bits, or 0 if no match,
- or -1 if an error occurs fetching data (memory_error_func will have
- been called). */
-
-static int
-extract_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn,
- CGEN_EXTRACT_INFO *ex_info,
- CGEN_INSN_INT insn_value,
- CGEN_FIELDS *fields,
- bfd_vma pc)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- const CGEN_SYNTAX_CHAR_TYPE *syn;
-
- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
-
- CGEN_INIT_EXTRACT (cd);
-
- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
- {
- int length;
-
- if (CGEN_SYNTAX_CHAR_P (*syn))
- continue;
-
- length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
- ex_info, insn_value, fields, pc);
- if (length <= 0)
- return length;
- }
-
- /* We recognized and successfully extracted this insn. */
- return CGEN_INSN_BITSIZE (insn);
-}
-\f
-/* Machine generated code added here. */
-
-const char * bpf_cgen_insert_operand
- (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
-
-/* Main entry point for operand insertion.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `parse_insn_normal', but keeping it
- separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. It's also needed by GAS to insert operands that couldn't be
- resolved during parsing. */
-
-const char *
-bpf_cgen_insert_operand (CGEN_CPU_DESC cd,
- int opindex,
- CGEN_FIELDS * fields,
- CGEN_INSN_BYTES_PTR buffer,
- bfd_vma pc ATTRIBUTE_UNUSED)
-{
- const char * errmsg = NULL;
- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
-
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, buffer);
- break;
- case BPF_OPERAND_DISP32 :
- errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
- break;
- case BPF_OPERAND_DSTBE :
- errmsg = insert_normal (cd, fields->f_dstbe, 0, 8, 7, 4, 8, total_length, buffer);
- break;
- case BPF_OPERAND_DSTLE :
- errmsg = insert_normal (cd, fields->f_dstle, 0, 8, 3, 4, 8, total_length, buffer);
- break;
- case BPF_OPERAND_ENDSIZE :
- errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
- break;
- case BPF_OPERAND_IMM32 :
- errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
- break;
- case BPF_OPERAND_IMM64 :
- {
-{
- FLD (f_imm64_b) = 0;
- FLD (f_imm64_c) = ((UDI) (FLD (f_imm64)) >> (32));
- FLD (f_imm64_a) = ((FLD (f_imm64)) & (MAKEDI (0, 0xffffffff)));
-}
- errmsg = insert_normal (cd, fields->f_imm64_a, 0, 32, 31, 32, 32, total_length, buffer);
- if (errmsg)
- break;
- errmsg = insert_normal (cd, fields->f_imm64_b, 0, 64, 31, 32, 32, total_length, buffer);
- if (errmsg)
- break;
- errmsg = insert_normal (cd, fields->f_imm64_c, 0, 96, 31, 32, 32, total_length, buffer);
- if (errmsg)
- break;
- }
- break;
- case BPF_OPERAND_OFFSET16 :
- errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, buffer);
- break;
- case BPF_OPERAND_SRCBE :
- errmsg = insert_normal (cd, fields->f_srcbe, 0, 8, 3, 4, 8, total_length, buffer);
- break;
- case BPF_OPERAND_SRCLE :
- errmsg = insert_normal (cd, fields->f_srcle, 0, 8, 7, 4, 8, total_length, buffer);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while building insn"),
- opindex);
- abort ();
- }
-
- return errmsg;
-}
-
-int bpf_cgen_extract_operand
- (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
-
-/* Main entry point for operand extraction.
- The result is <= 0 for error, >0 for success.
- ??? Actual values aren't well defined right now.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `print_insn_normal', but keeping it
- separate makes clear the interface between `print_insn_normal' and each of
- the handlers. */
-
-int
-bpf_cgen_extract_operand (CGEN_CPU_DESC cd,
- int opindex,
- CGEN_EXTRACT_INFO *ex_info,
- CGEN_INSN_INT insn_value,
- CGEN_FIELDS * fields,
- bfd_vma pc)
-{
- /* Assume success (for those operands that are nops). */
- int length = 1;
- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
-
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, pc, & fields->f_offset16);
- break;
- case BPF_OPERAND_DISP32 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
- break;
- case BPF_OPERAND_DSTBE :
- length = extract_normal (cd, ex_info, insn_value, 0, 8, 7, 4, 8, total_length, pc, & fields->f_dstbe);
- break;
- case BPF_OPERAND_DSTLE :
- length = extract_normal (cd, ex_info, insn_value, 0, 8, 3, 4, 8, total_length, pc, & fields->f_dstle);
- break;
- case BPF_OPERAND_ENDSIZE :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
- break;
- case BPF_OPERAND_IMM32 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
- break;
- case BPF_OPERAND_IMM64 :
- {
- length = extract_normal (cd, ex_info, insn_value, 0, 32, 31, 32, 32, total_length, pc, & fields->f_imm64_a);
- if (length <= 0) break;
- length = extract_normal (cd, ex_info, insn_value, 0, 64, 31, 32, 32, total_length, pc, & fields->f_imm64_b);
- if (length <= 0) break;
- length = extract_normal (cd, ex_info, insn_value, 0, 96, 31, 32, 32, total_length, pc, & fields->f_imm64_c);
- if (length <= 0) break;
-{
- FLD (f_imm64) = ((((((UDI) (UINT) (FLD (f_imm64_c)))) << (32))) | (((UDI) (UINT) (FLD (f_imm64_a)))));
-}
- }
- break;
- case BPF_OPERAND_OFFSET16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, pc, & fields->f_offset16);
- break;
- case BPF_OPERAND_SRCBE :
- length = extract_normal (cd, ex_info, insn_value, 0, 8, 3, 4, 8, total_length, pc, & fields->f_srcbe);
- break;
- case BPF_OPERAND_SRCLE :
- length = extract_normal (cd, ex_info, insn_value, 0, 8, 7, 4, 8, total_length, pc, & fields->f_srcle);
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while decoding insn"),
- opindex);
- abort ();
- }
-
- return length;
-}
-
-cgen_insert_fn * const bpf_cgen_insert_handlers[] =
-{
- insert_insn_normal,
-};
-
-cgen_extract_fn * const bpf_cgen_extract_handlers[] =
-{
- extract_insn_normal,
-};
-
-int bpf_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-bfd_vma bpf_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-
-/* Getting values from cgen_fields is handled by a collection of functions.
- They are distinguished by the type of the VALUE argument they return.
- TODO: floating point, inlining support, remove cases where result type
- not appropriate. */
-
-int
-bpf_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- const CGEN_FIELDS * fields)
-{
- int value;
-
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- value = fields->f_offset16;
- break;
- case BPF_OPERAND_DISP32 :
- value = fields->f_imm32;
- break;
- case BPF_OPERAND_DSTBE :
- value = fields->f_dstbe;
- break;
- case BPF_OPERAND_DSTLE :
- value = fields->f_dstle;
- break;
- case BPF_OPERAND_ENDSIZE :
- value = fields->f_imm32;
- break;
- case BPF_OPERAND_IMM32 :
- value = fields->f_imm32;
- break;
- case BPF_OPERAND_IMM64 :
- value = fields->f_imm64;
- break;
- case BPF_OPERAND_OFFSET16 :
- value = fields->f_offset16;
- break;
- case BPF_OPERAND_SRCBE :
- value = fields->f_srcbe;
- break;
- case BPF_OPERAND_SRCLE :
- value = fields->f_srcle;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while getting int operand"),
- opindex);
- abort ();
- }
-
- return value;
-}
-
-bfd_vma
-bpf_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- const CGEN_FIELDS * fields)
-{
- bfd_vma value;
-
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- value = fields->f_offset16;
- break;
- case BPF_OPERAND_DISP32 :
- value = fields->f_imm32;
- break;
- case BPF_OPERAND_DSTBE :
- value = fields->f_dstbe;
- break;
- case BPF_OPERAND_DSTLE :
- value = fields->f_dstle;
- break;
- case BPF_OPERAND_ENDSIZE :
- value = fields->f_imm32;
- break;
- case BPF_OPERAND_IMM32 :
- value = fields->f_imm32;
- break;
- case BPF_OPERAND_IMM64 :
- value = fields->f_imm64;
- break;
- case BPF_OPERAND_OFFSET16 :
- value = fields->f_offset16;
- break;
- case BPF_OPERAND_SRCBE :
- value = fields->f_srcbe;
- break;
- case BPF_OPERAND_SRCLE :
- value = fields->f_srcle;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while getting vma operand"),
- opindex);
- abort ();
- }
-
- return value;
-}
-
-void bpf_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
-void bpf_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
-
-/* Stuffing values in cgen_fields is handled by a collection of functions.
- They are distinguished by the type of the VALUE argument they accept.
- TODO: floating point, inlining support, remove cases where argument type
- not appropriate. */
-
-void
-bpf_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- CGEN_FIELDS * fields,
- int value)
-{
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- fields->f_offset16 = value;
- break;
- case BPF_OPERAND_DISP32 :
- fields->f_imm32 = value;
- break;
- case BPF_OPERAND_DSTBE :
- fields->f_dstbe = value;
- break;
- case BPF_OPERAND_DSTLE :
- fields->f_dstle = value;
- break;
- case BPF_OPERAND_ENDSIZE :
- fields->f_imm32 = value;
- break;
- case BPF_OPERAND_IMM32 :
- fields->f_imm32 = value;
- break;
- case BPF_OPERAND_IMM64 :
- fields->f_imm64 = value;
- break;
- case BPF_OPERAND_OFFSET16 :
- fields->f_offset16 = value;
- break;
- case BPF_OPERAND_SRCBE :
- fields->f_srcbe = value;
- break;
- case BPF_OPERAND_SRCLE :
- fields->f_srcle = value;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while setting int operand"),
- opindex);
- abort ();
- }
-}
-
-void
-bpf_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- CGEN_FIELDS * fields,
- bfd_vma value)
-{
- switch (opindex)
- {
- case BPF_OPERAND_DISP16 :
- fields->f_offset16 = value;
- break;
- case BPF_OPERAND_DISP32 :
- fields->f_imm32 = value;
- break;
- case BPF_OPERAND_DSTBE :
- fields->f_dstbe = value;
- break;
- case BPF_OPERAND_DSTLE :
- fields->f_dstle = value;
- break;
- case BPF_OPERAND_ENDSIZE :
- fields->f_imm32 = value;
- break;
- case BPF_OPERAND_IMM32 :
- fields->f_imm32 = value;
- break;
- case BPF_OPERAND_IMM64 :
- fields->f_imm64 = value;
- break;
- case BPF_OPERAND_OFFSET16 :
- fields->f_offset16 = value;
- break;
- case BPF_OPERAND_SRCBE :
- fields->f_srcbe = value;
- break;
- case BPF_OPERAND_SRCLE :
- fields->f_srcle = value;
- break;
-
- default :
- /* xgettext:c-format */
- opcodes_error_handler
- (_("internal error: unrecognized field %d while setting vma operand"),
- opindex);
- abort ();
- }
-}
-
-/* Function to call before using the instruction builder tables. */
-
-void
-bpf_cgen_init_ibld_table (CGEN_CPU_DESC cd)
-{
- cd->insert_handlers = & bpf_cgen_insert_handlers[0];
- cd->extract_handlers = & bpf_cgen_extract_handlers[0];
-
- cd->insert_operand = bpf_cgen_insert_operand;
- cd->extract_operand = bpf_cgen_extract_operand;
-
- cd->get_int_operand = bpf_cgen_get_int_operand;
- cd->set_int_operand = bpf_cgen_set_int_operand;
- cd->get_vma_operand = bpf_cgen_get_vma_operand;
- cd->set_vma_operand = bpf_cgen_set_vma_operand;
-}
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Instruction opcode table for bpf.
+/* bpf-opc.c - BPF opcodes.
+ Copyright (C) 2023 Free Software Foundation, Inc.
-THIS FILE IS MACHINE GENERATED WITH CGEN.
+ Contributed by Oracle Inc.
-Copyright (C) 1996-2023 Free Software Foundation, Inc.
+ This file is part of the GNU binutils.
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
+ This is free software; you can redistribute them and/or modify them
+ under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
-#include "libiberty.h"
-
-/* -- opc.c */
-\f
-/* -- asm.c */
-/* The hash functions are recorded here to help keep assembler code out of
- the disassembler and vice versa. */
-
-static int asm_hash_insn_p (const CGEN_INSN *);
-static unsigned int asm_hash_insn (const char *);
-static int dis_hash_insn_p (const CGEN_INSN *);
-static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
-
-/* Instruction formats. */
-
-#define F(f) & bpf_cgen_ifld_table[BPF_##f]
-static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
- 0, 0, 0x0, { { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
- 64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
- 64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
- 64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
- 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
- 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
- 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = {
- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
-static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
-static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
- 64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
+#include "config.h"
+#include <stdlib.h>
+#include "opcode/bpf.h"
-#undef F
+/* Note that the entries in the opcodes table below are accessed
+ sequentially when matching instructions per opcode, and also when
+ parsing. Please take care to keep the entries sorted
+ accordingly! */
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) BPF_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The instruction table. */
-
-static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
+const struct bpf_opcode bpf_opcodes[] =
{
- /* Special null first entry.
- A `num' value of zero is thus invalid.
- Also, the special `invalid' insn resides here. */
- { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
-/* add $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x7 }
- },
-/* add $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xf }
- },
-/* add32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x4 }
- },
-/* add32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xc }
- },
-/* sub $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x17 }
- },
-/* sub $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x1f }
- },
-/* sub32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x14 }
- },
-/* sub32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x1c }
- },
-/* mul $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x27 }
- },
-/* mul $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x2f }
- },
-/* mul32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x24 }
- },
-/* mul32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x2c }
- },
-/* div $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x37 }
- },
-/* div $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x3f }
- },
-/* div32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x34 }
- },
-/* div32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x3c }
- },
-/* or $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x47 }
- },
-/* or $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x4f }
- },
-/* or32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x44 }
- },
-/* or32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x4c }
- },
-/* and $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x57 }
- },
-/* and $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x5f }
- },
-/* and32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x54 }
- },
-/* and32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x5c }
- },
-/* lsh $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x67 }
- },
-/* lsh $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x6f }
- },
-/* lsh32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x64 }
- },
-/* lsh32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x6c }
- },
-/* rsh $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x77 }
- },
-/* rsh $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x7f }
- },
-/* rsh32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x74 }
- },
-/* rsh32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x7c }
- },
-/* mod $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x97 }
- },
-/* mod $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x9f }
- },
-/* mod32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0x94 }
- },
-/* mod32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0x9c }
- },
-/* xor $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xa7 }
- },
-/* xor $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xaf }
- },
-/* xor32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xa4 }
- },
-/* xor32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xac }
- },
-/* arsh $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xc7 }
- },
-/* arsh $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xcf }
- },
-/* arsh32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xc4 }
- },
-/* arsh32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xcc }
- },
-/* sdiv $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xe7 }
- },
-/* sdiv $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xef }
- },
-/* sdiv32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xe4 }
- },
-/* sdiv32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xec }
- },
-/* smod $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xf7 }
- },
-/* smod $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xff }
- },
-/* smod32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xf4 }
- },
-/* smod32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xfc }
- },
-/* neg $dstle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), 0 } },
- & ifmt_negle, { 0x87 }
- },
-/* neg32 $dstle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), 0 } },
- & ifmt_negle, { 0x84 }
- },
-/* mov $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xb7 }
- },
-/* mov $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xbf }
- },
-/* mov32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xb4 }
- },
-/* mov32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xbc }
- },
-/* add $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x7 }
- },
-/* add $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xf }
- },
-/* add32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x4 }
- },
-/* add32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xc }
- },
-/* sub $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x17 }
- },
-/* sub $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x1f }
- },
-/* sub32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x14 }
- },
-/* sub32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x1c }
- },
-/* mul $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x27 }
- },
-/* mul $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x2f }
- },
-/* mul32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x24 }
- },
-/* mul32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x2c }
- },
-/* div $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x37 }
- },
-/* div $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x3f }
- },
-/* div32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x34 }
- },
-/* div32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x3c }
- },
-/* or $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x47 }
- },
-/* or $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x4f }
- },
-/* or32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x44 }
- },
-/* or32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x4c }
- },
-/* and $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x57 }
- },
-/* and $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x5f }
- },
-/* and32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x54 }
- },
-/* and32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x5c }
- },
-/* lsh $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x67 }
- },
-/* lsh $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x6f }
- },
-/* lsh32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x64 }
- },
-/* lsh32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x6c }
- },
-/* rsh $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x77 }
- },
-/* rsh $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x7f }
- },
-/* rsh32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x74 }
- },
-/* rsh32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x7c }
- },
-/* mod $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x97 }
- },
-/* mod $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x9f }
- },
-/* mod32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0x94 }
- },
-/* mod32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0x9c }
- },
-/* xor $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xa7 }
- },
-/* xor $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xaf }
- },
-/* xor32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xa4 }
- },
-/* xor32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xac }
- },
-/* arsh $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xc7 }
- },
-/* arsh $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xcf }
- },
-/* arsh32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xc4 }
- },
-/* arsh32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xcc }
- },
-/* sdiv $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xe7 }
- },
-/* sdiv $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xef }
- },
-/* sdiv32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xe4 }
- },
-/* sdiv32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xec }
- },
-/* smod $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xf7 }
- },
-/* smod $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xff }
- },
-/* smod32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xf4 }
- },
-/* smod32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xfc }
- },
-/* neg $dstbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), 0 } },
- & ifmt_negbe, { 0x87 }
- },
-/* neg32 $dstbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), 0 } },
- & ifmt_negbe, { 0x84 }
- },
-/* mov $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xb7 }
- },
-/* mov $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xbf }
- },
-/* mov32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xb4 }
- },
-/* mov32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xbc }
- },
-/* endle $dstle,$endsize */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },
- & ifmt_endlele, { 0xd4 }
- },
-/* endbe $dstle,$endsize */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },
- & ifmt_endlele, { 0xdc }
- },
-/* endle $dstbe,$endsize */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },
- & ifmt_endlebe, { 0xd4 }
- },
-/* endbe $dstbe,$endsize */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },
- & ifmt_endlebe, { 0xdc }
- },
-/* lddw $dstle,$imm64 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM64), 0 } },
- & ifmt_lddwle, { 0x18 }
- },
-/* lddw $dstbe,$imm64 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM64), 0 } },
- & ifmt_lddwbe, { 0x18 }
- },
-/* ldabsw $imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (IMM32), 0 } },
- & ifmt_ldabsw, { 0x20 }
- },
-/* ldabsh $imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (IMM32), 0 } },
- & ifmt_ldabsw, { 0x28 }
- },
-/* ldabsb $imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (IMM32), 0 } },
- & ifmt_ldabsw, { 0x30 }
- },
-/* ldabsdw $imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (IMM32), 0 } },
- & ifmt_ldabsw, { 0x38 }
- },
-/* ldindw $srcle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwle, { 0x40 }
- },
-/* ldindh $srcle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwle, { 0x48 }
- },
-/* ldindb $srcle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwle, { 0x50 }
- },
-/* ldinddw $srcle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwle, { 0x58 }
- },
-/* ldindw $srcbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwbe, { 0x40 }
- },
-/* ldindh $srcbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwbe, { 0x48 }
- },
-/* ldindb $srcbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwbe, { 0x50 }
- },
-/* ldinddw $srcbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
- & ifmt_ldindwbe, { 0x58 }
- },
-/* ldxw $dstle,[$srcle+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwle, { 0x61 }
- },
-/* ldxh $dstle,[$srcle+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwle, { 0x69 }
- },
-/* ldxb $dstle,[$srcle+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwle, { 0x71 }
- },
-/* ldxdw $dstle,[$srcle+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwle, { 0x79 }
- },
-/* stxw [$dstle+$offset16],$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
- & ifmt_ldxwle, { 0x63 }
- },
-/* stxh [$dstle+$offset16],$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
- & ifmt_ldxwle, { 0x6b }
- },
-/* stxb [$dstle+$offset16],$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
- & ifmt_ldxwle, { 0x73 }
- },
-/* stxdw [$dstle+$offset16],$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
- & ifmt_ldxwle, { 0x7b }
- },
-/* ldxw $dstbe,[$srcbe+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwbe, { 0x61 }
- },
-/* ldxh $dstbe,[$srcbe+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwbe, { 0x69 }
- },
-/* ldxb $dstbe,[$srcbe+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwbe, { 0x71 }
- },
-/* ldxdw $dstbe,[$srcbe+$offset16] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
- & ifmt_ldxwbe, { 0x79 }
- },
-/* stxw [$dstbe+$offset16],$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
- & ifmt_ldxwbe, { 0x63 }
- },
-/* stxh [$dstbe+$offset16],$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
- & ifmt_ldxwbe, { 0x6b }
- },
-/* stxb [$dstbe+$offset16],$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
- & ifmt_ldxwbe, { 0x73 }
- },
-/* stxdw [$dstbe+$offset16],$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
- & ifmt_ldxwbe, { 0x7b }
- },
-/* stb [$dstle+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stble, { 0x72 }
- },
-/* sth [$dstle+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stble, { 0x6a }
- },
-/* stw [$dstle+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stble, { 0x62 }
- },
-/* stdw [$dstle+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stble, { 0x7a }
- },
-/* stb [$dstbe+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stbbe, { 0x72 }
- },
-/* sth [$dstbe+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stbbe, { 0x6a }
- },
-/* stw [$dstbe+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stbbe, { 0x62 }
- },
-/* stdw [$dstbe+$offset16],$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
- & ifmt_stbbe, { 0x7a }
- },
-/* jeq $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x15 }
- },
-/* jeq $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x1d }
- },
-/* jeq32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x16 }
- },
-/* jeq32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x1e }
- },
-/* jgt $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x25 }
- },
-/* jgt $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x2d }
- },
-/* jgt32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x26 }
- },
-/* jgt32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x2e }
- },
-/* jge $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x35 }
- },
-/* jge $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x3d }
- },
-/* jge32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x36 }
- },
-/* jge32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x3e }
- },
-/* jlt $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xa5 }
- },
-/* jlt $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xad }
- },
-/* jlt32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xa6 }
- },
-/* jlt32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xae }
- },
-/* jle $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xb5 }
- },
-/* jle $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xbd }
- },
-/* jle32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xb6 }
- },
-/* jle32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xbe }
- },
-/* jset $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x45 }
- },
-/* jset $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x4d }
- },
-/* jset32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x46 }
- },
-/* jset32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x4e }
- },
-/* jne $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x55 }
- },
-/* jne $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x5d }
- },
-/* jne32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x56 }
- },
-/* jne32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x5e }
- },
-/* jsgt $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x65 }
- },
-/* jsgt $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x6d }
- },
-/* jsgt32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x66 }
- },
-/* jsgt32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x6e }
- },
-/* jsge $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x75 }
- },
-/* jsge $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x7d }
- },
-/* jsge32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0x76 }
- },
-/* jsge32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0x7e }
- },
-/* jslt $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xc5 }
- },
-/* jslt $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xcd }
- },
-/* jslt32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xc6 }
- },
-/* jslt32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xce }
- },
-/* jsle $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xd5 }
- },
-/* jsle $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xdd }
- },
-/* jsle32 $dstle,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqile, { 0xd6 }
- },
-/* jsle32 $dstle,$srcle,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrle, { 0xde }
- },
-/* jeq $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x15 }
- },
-/* jeq $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x1d }
- },
-/* jeq32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x16 }
- },
-/* jeq32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x1e }
- },
-/* jgt $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x25 }
- },
-/* jgt $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x2d }
- },
-/* jgt32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x26 }
- },
-/* jgt32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x2e }
- },
-/* jge $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x35 }
- },
-/* jge $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x3d }
- },
-/* jge32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x36 }
- },
-/* jge32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x3e }
- },
-/* jlt $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xa5 }
- },
-/* jlt $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xad }
- },
-/* jlt32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xa6 }
- },
-/* jlt32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xae }
- },
-/* jle $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xb5 }
- },
-/* jle $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xbd }
- },
-/* jle32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xb6 }
- },
-/* jle32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xbe }
- },
-/* jset $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x45 }
- },
-/* jset $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x4d }
- },
-/* jset32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x46 }
- },
-/* jset32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x4e }
- },
-/* jne $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x55 }
- },
-/* jne $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x5d }
- },
-/* jne32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x56 }
- },
-/* jne32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x5e }
- },
-/* jsgt $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x65 }
- },
-/* jsgt $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x6d }
- },
-/* jsgt32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x66 }
- },
-/* jsgt32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x6e }
- },
-/* jsge $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x75 }
- },
-/* jsge $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x7d }
- },
-/* jsge32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0x76 }
- },
-/* jsge32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0x7e }
- },
-/* jslt $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xc5 }
- },
-/* jslt $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xcd }
- },
-/* jslt32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xc6 }
- },
-/* jslt32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xce }
- },
-/* jsle $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xd5 }
- },
-/* jsle $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xdd }
- },
-/* jsle32 $dstbe,$imm32,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
- & ifmt_jeqibe, { 0xd6 }
- },
-/* jsle32 $dstbe,$srcbe,$disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
- & ifmt_jeqrbe, { 0xde }
- },
-/* call $disp32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP32), 0 } },
- & ifmt_callle, { 0x85 }
- },
-/* call $disp32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP32), 0 } },
- & ifmt_callbe, { 0x85 }
- },
-/* call $dstle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), 0 } },
- & ifmt_negle, { 0x8d }
- },
-/* call $dstbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), 0 } },
- & ifmt_negbe, { 0x8d }
- },
-/* ja $disp16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP16), 0 } },
- & ifmt_ja, { 0x5 }
- },
-/* exit */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_exit, { 0x95 }
- },
-/* xadddw [$dstle+$offset16],$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
- & ifmt_ldxwle, { 0xdb }
- },
-/* xaddw [$dstle+$offset16],$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
- & ifmt_ldxwle, { 0xc3 }
- },
-/* xadddw [$dstbe+$offset16],$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
- & ifmt_ldxwbe, { 0xdb }
- },
-/* xaddw [$dstbe+$offset16],$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
- & ifmt_ldxwbe, { 0xc3 }
- },
-/* brkpt */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_exit, { 0x8c }
- },
+ /* id, normal, pseudoc, version, mask, opcodes */
+
+ /* ALU instructions. */
+ {BPF_INSN_ADDR, "add%W%dr , %sr", "%dr += %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_X},
+ {BPF_INSN_ADDI, "add%W%dr , %i32", "%dr += %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_K},
+ {BPF_INSN_SUBR, "sub%W%dr , %sr", "%dr -= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_X},
+ {BPF_INSN_SUBI, "sub%W%dr , %i32", "%dr -= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_K},
+ {BPF_INSN_MULR, "mul%W%dr , %sr", "%dr *= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_X},
+ {BPF_INSN_MULI, "mul%W%dr , %i32", "%dr *= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_K},
+ {BPF_INSN_SDIVR, "sdiv%W%dr, %sr", "%dr s/= %sr",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_SDIVI, "sdiv%W%dr , %i32","%dr s/= %i32",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_SMODR, "smod%W%dr , %sr", "%dr s%%= %sr",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_SMODI, "smod%W%dr , %i32", "%dr s%%= %i32",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_DIVR, "div%W%dr , %sr", "%dr /= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X},
+ {BPF_INSN_DIVI, "div%W%dr , %i32", "%dr /= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K},
+ {BPF_INSN_MODR, "mod%W%dr , %sr", "%dr %%= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X},
+ {BPF_INSN_MODI, "mod%W%dr , %i32", "%dr %%= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K},
+ {BPF_INSN_ORR, "or%W%dr , %sr", "%dr |= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_X},
+ {BPF_INSN_ORI, "or%W%dr , %i32", "%dr |= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_K},
+ {BPF_INSN_ANDR, "and%W%dr , %sr", "%dr &= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_X},
+ {BPF_INSN_ANDI, "and%W%dr , %i32", "%dr &= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_K},
+ {BPF_INSN_XORR, "xor%W%dr , %sr", "%dr ^= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_X},
+ {BPF_INSN_XORI, "xor%W%dr , %i32", "%dr ^= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_K},
+ {BPF_INSN_NEGR, "neg%W%dr, %sr", "%dr = - %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_X},
+ {BPF_INSN_NEGI, "neg%W%dr , %i32", "%dr = -%W%i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_K},
+ {BPF_INSN_LSHR, "lsh%W%dr , %sr", "%dr <<= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_X},
+ {BPF_INSN_LSHI, "lsh%W%dr , %i32", "%dr <<= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_K},
+ {BPF_INSN_RSHR, "rsh%W%dr , %sr", "%dr >>= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_X},
+ {BPF_INSN_RSHI, "rsh%W%dr , %i32", "%dr >>= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_K},
+ {BPF_INSN_ARSHR, "arsh%W%dr , %sr", "%dr%ws>>= %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},
+ {BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},
+ {BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},
+ {BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr = %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_K},
+
+ /* ALU32 instructions. */
+ {BPF_INSN_ADD32R, "add32%W%dr , %sr", "%dw += %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_X},
+ {BPF_INSN_ADD32I, "add32%W%dr , %i32", "%dw += %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_K},
+ {BPF_INSN_SUB32R, "sub32%W%dr , %sr", "%dw -= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_X},
+ {BPF_INSN_SUB32I, "sub32%W%dr , %i32", "%dw -= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_K},
+ {BPF_INSN_MUL32R, "mul32%W%dr , %sr", "%dw *= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_X},
+ {BPF_INSN_MUL32I, "mul32%W%dr , %i32", "%dw *= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_K},
+ {BPF_INSN_SDIV32R, "sdiv32%W%dr , %sr", "%dw s/= %sw",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_SDIV32I, "sdiv32%W%dr , %i32", "%dw s/= %i32",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_SMOD32R, "smod32%W%dr , %sr", "%dw s%%= %sw",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_SMOD32I, "smod32%W%dr , %i32", "%dw s%%= %i32",
+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+ {BPF_INSN_DIV32R, "div32%W%dr , %sr", "%dw /= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X},
+ {BPF_INSN_DIV32I, "div32%W%dr , %i32", "%dw /= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K},
+ {BPF_INSN_MOD32R, "mod32%W%dr , %sr", "%dw %%= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X},
+ {BPF_INSN_MOD32I, "mod32%W%dr , %i32", "%dw %%= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K},
+ {BPF_INSN_OR32R, "or32%W%dr , %sr", "%dw |= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_X},
+ {BPF_INSN_OR32I, "or32%W%dr , %i32", "%dw |= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_K},
+ {BPF_INSN_AND32R, "and32%W%dr , %sr", "%dw &= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_X},
+ {BPF_INSN_AND32I, "and32%W%dr , %i32", "%dw &= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_K},
+ {BPF_INSN_XOR32R, "xor32%W%dr , %sr", "%dw ^= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_X},
+ {BPF_INSN_XOR32I, "xor32%W%dr , %i32", "%dw ^= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_K},
+ {BPF_INSN_NEG32R, "neg32%W%dr , %sr", "%dw = - %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_X},
+ {BPF_INSN_NEG32I, "neg32%W%dr , %i32", "%dw = -%W%i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_K},
+ {BPF_INSN_LSH32R, "lsh32%W%dr , %sr", "%dw <<= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_X},
+ {BPF_INSN_LSH32I, "lsh32%W%dr , %i32", "%dw <<= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_K},
+ {BPF_INSN_RSH32R, "rsh32%W%dr , %sr", "%dw >>= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_X},
+ {BPF_INSN_RSH32I, "rsh32%W%dr , %i32", "%dw >>= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_K},
+ {BPF_INSN_ARSH32R, "arsh32%W%dr , %sr", "%dw%ws>>= %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},
+ {BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},
+ {BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},
+ {BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw = %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_K},
+
+ /* Endianness conversion instructions. */
+ {BPF_INSN_ENDLE16, "endle%W%dr , 16", "%dr = le16%w%dr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END16},
+ {BPF_INSN_ENDLE32, "endle%W%dr , 32", "%dr = le32%w%dr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END32},
+ {BPF_INSN_ENDLE64, "endle%W%dr , 64", "%dr = le64%w%dr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END64},
+ {BPF_INSN_ENDBE16, "endbe%W%dr , 16", "%dr = be16%w%dr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END16},
+ {BPF_INSN_ENDBE32, "endbe%W%dr , 32", "%dr = be32%w%dr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END32},
+ {BPF_INSN_ENDBE64, "endbe%W%dr , 64", "%dr = be64%w%dr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END64},
+
+ /* 64-bit load instruction. */
+ {BPF_INSN_LDDW, "lddw%W%dr , %i64", "%dr = %i64%wll",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IMM},
+
+ /* Indirect load instructions, designed to be used in socket
+ filters. */
+ {BPF_INSN_LDINDB, "ldindb%W%sr , %i32", "r0 = * ( u8 * ) skb [ %sr %I32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_IND},
+ {BPF_INSN_LDINDH, "ldindh%W%sr , %i32", "r0 = * ( u16 * ) skb [ %sr %I32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_IND},
+ {BPF_INSN_LDINDW, "ldindw%W%sr , %i32", "r0 = * ( u32 * ) skb [ %sr %I32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_IND},
+ {BPF_INSN_LDINDDW, "ldinddw%W%sr , %i32", "r0 = * ( u64 * ) skb [ %sr %I32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IND},
+
+ /* Absolute load instructions, designed to be used in socket filters. */
+ {BPF_INSN_LDABSB, "ldabsb%W%i32", "r0 = * ( u8 * ) skb [ %i32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_ABS},
+ {BPF_INSN_LDABSH, "ldabsh%W%i32", "r0 = * ( u16 * ) skb [ %i32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_ABS},
+ {BPF_INSN_LDABSW, "ldabsw%W%i32", "r0 = * ( u32 * ) skb [ %i32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_ABS},
+ {BPF_INSN_LDABSDW, "ldabsdw%W%i32", "r0 = * ( u64 * ) skb [ %i32 ]",
+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_ABS},
+
+ /* Generic load instructions (to register.) */
+ {BPF_INSN_LDXB, "ldxb%W%dr , [ %sr %o16 ]", "%dr = * ( u8 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM},
+ {BPF_INSN_LDXH, "ldxh%W%dr , [ %sr %o16 ]", "%dr = * ( u16 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM},
+ {BPF_INSN_LDXW, "ldxw%W%dr , [ %sr %o16 ]", "%dr = * ( u32 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
+ {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
+
+ /* Generic store instructions (from register.) */
+ {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM},
+ {BPF_INSN_STXHR, "stxh%W[ %dr %o16 ] , %sr", "* ( u16 * ) ( %dr %o16 ) = %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_MEM},
+ {BPF_INSN_STXWR, "stxw%W[ %dr %o16 ], %sr", "* ( u32 * ) ( %dr %o16 ) = %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_MEM},
+ {BPF_INSN_STXDWR, "stxdw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) = %sr",
+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_MEM},
+
+ /* Generic store instructions (from 32-bit immediate.) */
+ {BPF_INSN_STXBI, "stb%W[ %dr %o16 ] , %i32", "* ( u8 * ) ( %dr %o16 ) = %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_B|BPF_MODE_MEM},
+ {BPF_INSN_STXHI, "sth%W[ %dr %o16 ] , %i32", "* ( u16 * ) ( %dr %o16 ) = %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_H|BPF_MODE_MEM},
+ {BPF_INSN_STXWI, "stw%W[ %dr %o16 ] , %i32", "* ( u32 * ) ( %dr %o16 ) = %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_W|BPF_MODE_MEM},
+ {BPF_INSN_STXDWI, "stdw%W[ %dr %o16 ] , %i32", "* ( u64 * ) ( %dr %o16 ) = %i32",
+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_DW|BPF_MODE_MEM},
+
+ /* Compare-and-jump instructions (reg OP reg). */
+ {BPF_INSN_JAR, "ja%W%d16", "goto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JA|BPF_SRC_K},
+ {BPF_INSN_JEQR, "jeq%W%dr , %sr , %d16", "if%w%dr == %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_X},
+ {BPF_INSN_JGTR, "jgt%W%dr , %sr , %d16", "if%w%dr > %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_X},
+ {BPF_INSN_JSGTR, "jsgt%W%dr, %sr , %d16", "if%w%dr s> %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_X},
+ {BPF_INSN_JGER, "jge%W%dr , %sr , %d16", "if%w%dr >= %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_X},
+ {BPF_INSN_JSGER, "jsge%W%dr , %sr , %d16", "if%w%dr s>= %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_X},
+ {BPF_INSN_JLTR, "jlt%W%dr , %sr , %d16", "if%w%dr < %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_X},
+ {BPF_INSN_JSLTR, "jslt%W%dr , %sr , %d16", "if%w%dr s< %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_X},
+ {BPF_INSN_JLER, "jle%W%dr , %sr , %d16", "if%w%dr <= %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_X},
+ {BPF_INSN_JSLER, "jsle%W%dr , %sr , %d16", "if%w%dr s<= %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_X},
+ {BPF_INSN_JSETR, "jset%W%dr , %sr , %d16", "if%w%dr & %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_X},
+ {BPF_INSN_JNER, "jne%W%dr , %sr , %d16", "if%w%dr != %sr%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_X},
+ {BPF_INSN_CALLR, "call%W%dr", "callx%w%dr",
+ BPF_XBPF, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X},
+ {BPF_INSN_CALL, "call%W%d32", "call%w%d32",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_K},
+ {BPF_INSN_EXIT, "exit", "exit",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_EXIT|BPF_SRC_K},
+
+ /* Compare-and-jump instructions (reg OP imm). */
+ {BPF_INSN_JEQI, "jeq%W%dr , %i32 , %d16", "if%w%dr == %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_K},
+ {BPF_INSN_JGTI, "jgt%W%dr , %i32 , %d16", "if%w%dr > %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_K},
+ {BPF_INSN_JSGTI, "jsgt%W%dr, %i32 , %d16", "if%w%dr s> %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_K},
+ {BPF_INSN_JGEI, "jge%W%dr , %i32 , %d16", "if%w%dr >= %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_K},
+ {BPF_INSN_JSGEI, "jsge%W%dr , %i32 , %d16", "if%w%dr s>= %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_K},
+ {BPF_INSN_JLTI, "jlt%W%dr , %i32 , %d16", "if%w%dr < %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_K},
+ {BPF_INSN_JSLTI, "jslt%W%dr , %i32, %d16", "if%w%dr s< %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_K},
+ {BPF_INSN_JLEI, "jle%W%dr , %i32 , %d16", "if%w%dr <= %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_K},
+ {BPF_INSN_JSLEI, "jsle%W%dr , %i32 , %d16", "if%w%dr s<= %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_K},
+ {BPF_INSN_JSETI, "jset%W%dr , %i32 , %d16", "if%w%dr & %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_K},
+ {BPF_INSN_JNEI, "jne%W%dr , %i32 , %d16", "if%w%dr != %i32%wgoto%w%d16",
+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_K},
+
+ /* 32-bit compare-and-jump instructions (reg OP reg). */
+ {BPF_INSN_JEQ32R, "jeq32%W%dr , %sr , %d16", "if%w%dw == %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_X},
+ {BPF_INSN_JGT32R, "jgt32%W%dr , %sr , %d16", "if%w%dw > %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_X},
+ {BPF_INSN_JSGT32R, "jsgt32%W%dr, %sr , %d16", "if%w%dw s> %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_X},
+ {BPF_INSN_JGE32R, "jge32%W%dr , %sr , %d16", "if%w%dw >= %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_X},
+ {BPF_INSN_JSGE32R, "jsge32%W%dr , %sr , %d16", "if%w%dw s>= %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_X},
+ {BPF_INSN_JLT32R, "jlt32%W%dr , %sr , %d16", "if%w%dw < %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_X},
+ {BPF_INSN_JSLT32R, "jslt32%W%dr , %sr , %d16", "if%w%dw s< %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_X},
+ {BPF_INSN_JLE32R, "jle32%W%dr , %sr , %d16", "if%w%dw <= %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_X},
+ {BPF_INSN_JSLE32R, "jsle32%W%dr , %sr , %d16", "if%w%dw s<= %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_X},
+ {BPF_INSN_JSET32R, "jset32%W%dr , %sr , %d16", "if%w%dw & %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_X},
+ {BPF_INSN_JNE32R, "jne32%W%dr , %sr , %d16", "if%w%dw != %sw%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_X},
+
+ /* 32-bit compare-and-jump instructions (reg OP imm). */
+ {BPF_INSN_JEQ32I, "jeq32%W%dr , %i32 , %d16", "if%w%dw == %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_K},
+ {BPF_INSN_JGT32I, "jgt32%W%dr , %i32 , %d16", "if%w%dw > %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_K},
+ {BPF_INSN_JSGT32I, "jsgt32%W%dr, %i32 , %d16", "if%w%dw s> %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_K},
+ {BPF_INSN_JGE32I, "jge32%W%dr , %i32 , %d16", "if%w%dw >= %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_K},
+ {BPF_INSN_JSGE32I, "jsge32%W%dr , %i32 , %d16", "if%w%dw s>= %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_K},
+ {BPF_INSN_JLT32I, "jlt32%W%dr , %i32 , %d16", "if%w%dw < %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_K},
+ {BPF_INSN_JSLT32I, "jslt32%W%dr , %i32, %d16", "if%w%dw s< %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_K},
+ {BPF_INSN_JLE32I, "jle32%W%dr , %i32 , %d16", "if%w%dw <= %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_K},
+ {BPF_INSN_JSLE32I, "jsle32%W%dr , %i32 , %d16", "if%w%dw s<= %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_K},
+ {BPF_INSN_JSET32I, "jset32%W%dr , %i32 , %d16", "if%w%dw & %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_K},
+ {BPF_INSN_JNE32I, "jne32%W%dr , %i32 , %d16", "if%w%dw != %i32%wgoto%w%d16",
+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_K},
+
+ /* Atomic instructions. */
+ {BPF_INSN_AADD, "aadd%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+ {BPF_INSN_AOR, "aor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) |= %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
+ {BPF_INSN_AAND, "aand%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) &= %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
+ {BPF_INSN_AXOR, "axor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) ^= %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
+
+ /* Atomic instructions with fetching. */
+ {BPF_INSN_AFADD, "afadd%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
+ {BPF_INSN_AFOR, "afor%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
+ {BPF_INSN_AFAND, "afand%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
+ {BPF_INSN_AFXOR, "afxor%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
+
+ /* Atomic instructions (32-bit.) */
+ {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+ {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) |= %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
+ {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) &= %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
+ {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) ^= %sr",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
+
+ /* Atomic instructions with fetching (32-bit.) */
+ {BPF_INSN_AFADD32, "afadd32 %W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
+ {BPF_INSN_AFOR32, "afor32%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
+ {BPF_INSN_AFAND32, "afand32%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
+ {BPF_INSN_AFXOR32, "afxor32%W[ %dr %o16 ] , %sr", "???",
+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
+
+ /* Old versions of aadd and aadd32. */
+ {BPF_INSN_AADD, "xadddw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+ {BPF_INSN_AADD32, "xaddw%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+
+ /* the brkpt instruction is used by the BPF simulator and it doesn't
+ really belong to the BPF instruction set. */
+ {BPF_INSN_BRKPT, "brkpt", "brkpt",
+ BPF_XBPF, BPF_CODE, BPF_CLASS_ALU|BPF_SRC_X|BPF_CODE_NEG},
+
+ /* Sentinel. */
+ {BPF_NOINSN, NULL, NULL, 0, 0UL, 0UL},
};
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
-
-/* Formats for ALIAS macro-insns. */
-
-#define F(f) & bpf_cgen_ifld_table[BPF_##f]
-#undef F
-
-/* Each non-simple macro entry points to an array of expansion possibilities. */
-
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) BPF_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The macro instruction table. */
-
-static const CGEN_IBASE bpf_cgen_macro_insn_table[] =
+static bpf_insn_word
+bpf_handle_endianness (bpf_insn_word word, enum bpf_endian endian)
{
-};
+ if (endian == BPF_ENDIAN_LITTLE)
+ {
+ /* Endianness groups: 8 | 4 | 4 | 16 | 32 */
+
+ bpf_insn_word code = (word >> 56) & 0xff;
+ bpf_insn_word dst = (word >> 48) & 0xf;
+ bpf_insn_word src = (word >> 52) & 0xf;
+ bpf_insn_word offset16 = (word >> 32) & 0xffff;
+ bpf_insn_word imm32 = word & 0xffffffff;
+
+ return ((code << 56)
+ | dst << 52
+ | src << 48
+ | (offset16 & 0xff) << 40
+ | ((offset16 >> 8) & 0xff) << 32
+ | (imm32 & 0xff) << 24
+ | ((imm32 >> 8) & 0xff) << 16
+ | ((imm32 >> 16) & 0xff) << 8
+ | ((imm32 >> 24) & 0xff));
+ }
-/* The macro instruction opcode table. */
+ return word;
+}
-static const CGEN_OPCODE bpf_cgen_macro_insn_opcode_table[] =
+const struct bpf_opcode *
+bpf_match_insn (bpf_insn_word word,
+ enum bpf_endian endian,
+ int version)
{
-};
-
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
+ unsigned int i = 0;
-#ifndef CGEN_ASM_HASH_P
-#define CGEN_ASM_HASH_P(insn) 1
-#endif
-
-#ifndef CGEN_DIS_HASH_P
-#define CGEN_DIS_HASH_P(insn) 1
-#endif
+ while (bpf_opcodes[i].normal != NULL)
+ {
+ bpf_insn_word cword
+ = bpf_handle_endianness (word, endian);
+
+ /* Attempt match using mask and opcodes. */
+ if (bpf_opcodes[i].version <= version
+ && (cword & bpf_opcodes[i].mask) == bpf_opcodes[i].opcode)
+ return &bpf_opcodes[i];
+ i++;
+ }
-/* Return non-zero if INSN is to be added to the hash table.
- Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+ /* No maching instruction found. */
+ return NULL;
+}
-static int
-asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED)
+uint8_t
+bpf_extract_src (bpf_insn_word word, enum bpf_endian endian)
{
- return CGEN_ASM_HASH_P (insn);
+ word = bpf_handle_endianness (word, endian);
+ return (uint8_t) ((word >> 48) & 0xf);
}
-static int
-dis_hash_insn_p (const CGEN_INSN *insn)
+uint8_t
+bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian)
{
- /* If building the hash table and the NO-DIS attribute is present,
- ignore. */
- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
- return 0;
- return CGEN_DIS_HASH_P (insn);
+ word = bpf_handle_endianness (word, endian);
+ return (uint8_t) ((word >> 52) & 0xf);
}
-#ifndef CGEN_ASM_HASH
-#define CGEN_ASM_HASH_SIZE 127
-#ifdef CGEN_MNEMONIC_OPERANDS
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
-#else
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
-#endif
-#endif
-
-/* It doesn't make much sense to provide a default here,
- but while this is under development we do.
- BUFFER is a pointer to the bytes of the insn, target order.
- VALUE is the first base_insn_bitsize bits as an int in host order. */
-
-#ifndef CGEN_DIS_HASH
-#define CGEN_DIS_HASH_SIZE 256
-#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
-#endif
-
-/* The result is the hash value of the insn.
- Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
-
-static unsigned int
-asm_hash_insn (const char *mnem)
+int16_t
+bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian)
{
- return CGEN_ASM_HASH (mnem);
+ word = bpf_handle_endianness (word, endian);
+ return (int16_t) ((word >> 32) & 0xffff);
}
-/* BUF is a pointer to the bytes of the insn, target order.
- VALUE is the first base_insn_bitsize bits as an int in host order. */
-
-static unsigned int
-dis_hash_insn (const char *buf ATTRIBUTE_UNUSED,
- CGEN_INSN_INT value ATTRIBUTE_UNUSED)
+int32_t
+bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian)
{
- return CGEN_DIS_HASH (buf, value);
+ word = bpf_handle_endianness (word, endian);
+ return (int32_t) (word & 0xffffffff);
}
-/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
-
-static void
-set_fields_bitsize (CGEN_FIELDS *fields, int size)
+int64_t
+bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,
+ enum bpf_endian endian)
{
- CGEN_FIELDS_BITSIZE (fields) = size;
+ word1 = bpf_handle_endianness (word1, endian);
+ word2 = bpf_handle_endianness (word2, endian);
+ return (int64_t) (((word2 & 0xffffffff) << 32) | (word1 & 0xffffffff));
}
-/* Function to call before using the operand instance table.
- This plugs the opcode entries and macro instructions into the cpu table. */
-
-void
-bpf_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+const struct bpf_opcode *
+bpf_get_opcode (unsigned int index)
{
- int i;
- int num_macros = (sizeof (bpf_cgen_macro_insn_table) /
- sizeof (bpf_cgen_macro_insn_table[0]));
- const CGEN_IBASE *ib = & bpf_cgen_macro_insn_table[0];
- const CGEN_OPCODE *oc = & bpf_cgen_macro_insn_opcode_table[0];
- CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
-
- /* This test has been added to avoid a warning generated
- if memset is called with a third argument of value zero. */
- if (num_macros >= 1)
- memset (insns, 0, num_macros * sizeof (CGEN_INSN));
- for (i = 0; i < num_macros; ++i)
- {
- insns[i].base = &ib[i];
- insns[i].opcode = &oc[i];
- bpf_cgen_build_insn_regex (& insns[i]);
- }
- cd->macro_insn_table.init_entries = insns;
- cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->macro_insn_table.num_init_entries = num_macros;
-
- oc = & bpf_cgen_insn_opcode_table[0];
- insns = (CGEN_INSN *) cd->insn_table.init_entries;
- for (i = 0; i < MAX_INSNS; ++i)
- {
- insns[i].opcode = &oc[i];
- bpf_cgen_build_insn_regex (& insns[i]);
- }
-
- cd->sizeof_fields = sizeof (CGEN_FIELDS);
- cd->set_fields_bitsize = set_fields_bitsize;
-
- cd->asm_hash_p = asm_hash_insn_p;
- cd->asm_hash = asm_hash_insn;
- cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+ unsigned int i = 0;
- cd->dis_hash_p = dis_hash_insn_p;
- cd->dis_hash = dis_hash_insn;
- cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+ while (bpf_opcodes[i].normal != NULL && i < index)
+ ++i;
+ return (bpf_opcodes[i].normal == NULL
+ ? NULL
+ : &bpf_opcodes[i]);
}
+++ /dev/null
-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
-/* Instruction opcode header for bpf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2023 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef BPF_OPC_H
-#define BPF_OPC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* -- opc.h */
-
-#undef CGEN_DIS_HASH_SIZE
-#define CGEN_DIS_HASH_SIZE 1
-
-#undef CGEN_DIS_HASH
-#define CGEN_DIS_HASH(buffer, value) 0
-
-/* Allows reason codes to be output when assembler errors occur. */
-#define CGEN_VERBOSE_ASSEMBLER_ERRORS
-
-#define CGEN_VALIDATE_INSN_SUPPORTED
-extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
-
-\f
-/* -- opc.c */
-/* Enum declaration for bpf instruction types. */
-typedef enum cgen_insn_type {
- BPF_INSN_INVALID, BPF_INSN_ADDILE, BPF_INSN_ADDRLE, BPF_INSN_ADD32ILE
- , BPF_INSN_ADD32RLE, BPF_INSN_SUBILE, BPF_INSN_SUBRLE, BPF_INSN_SUB32ILE
- , BPF_INSN_SUB32RLE, BPF_INSN_MULILE, BPF_INSN_MULRLE, BPF_INSN_MUL32ILE
- , BPF_INSN_MUL32RLE, BPF_INSN_DIVILE, BPF_INSN_DIVRLE, BPF_INSN_DIV32ILE
- , BPF_INSN_DIV32RLE, BPF_INSN_ORILE, BPF_INSN_ORRLE, BPF_INSN_OR32ILE
- , BPF_INSN_OR32RLE, BPF_INSN_ANDILE, BPF_INSN_ANDRLE, BPF_INSN_AND32ILE
- , BPF_INSN_AND32RLE, BPF_INSN_LSHILE, BPF_INSN_LSHRLE, BPF_INSN_LSH32ILE
- , BPF_INSN_LSH32RLE, BPF_INSN_RSHILE, BPF_INSN_RSHRLE, BPF_INSN_RSH32ILE
- , BPF_INSN_RSH32RLE, BPF_INSN_MODILE, BPF_INSN_MODRLE, BPF_INSN_MOD32ILE
- , BPF_INSN_MOD32RLE, BPF_INSN_XORILE, BPF_INSN_XORRLE, BPF_INSN_XOR32ILE
- , BPF_INSN_XOR32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
- , BPF_INSN_ARSH32RLE, BPF_INSN_SDIVILE, BPF_INSN_SDIVRLE, BPF_INSN_SDIV32ILE
- , BPF_INSN_SDIV32RLE, BPF_INSN_SMODILE, BPF_INSN_SMODRLE, BPF_INSN_SMOD32ILE
- , BPF_INSN_SMOD32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
- , BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE, BPF_INSN_MOV32RLE, BPF_INSN_ADDIBE
- , BPF_INSN_ADDRBE, BPF_INSN_ADD32IBE, BPF_INSN_ADD32RBE, BPF_INSN_SUBIBE
- , BPF_INSN_SUBRBE, BPF_INSN_SUB32IBE, BPF_INSN_SUB32RBE, BPF_INSN_MULIBE
- , BPF_INSN_MULRBE, BPF_INSN_MUL32IBE, BPF_INSN_MUL32RBE, BPF_INSN_DIVIBE
- , BPF_INSN_DIVRBE, BPF_INSN_DIV32IBE, BPF_INSN_DIV32RBE, BPF_INSN_ORIBE
- , BPF_INSN_ORRBE, BPF_INSN_OR32IBE, BPF_INSN_OR32RBE, BPF_INSN_ANDIBE
- , BPF_INSN_ANDRBE, BPF_INSN_AND32IBE, BPF_INSN_AND32RBE, BPF_INSN_LSHIBE
- , BPF_INSN_LSHRBE, BPF_INSN_LSH32IBE, BPF_INSN_LSH32RBE, BPF_INSN_RSHIBE
- , BPF_INSN_RSHRBE, BPF_INSN_RSH32IBE, BPF_INSN_RSH32RBE, BPF_INSN_MODIBE
- , BPF_INSN_MODRBE, BPF_INSN_MOD32IBE, BPF_INSN_MOD32RBE, BPF_INSN_XORIBE
- , BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_ARSHIBE
- , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_SDIVIBE
- , BPF_INSN_SDIVRBE, BPF_INSN_SDIV32IBE, BPF_INSN_SDIV32RBE, BPF_INSN_SMODIBE
- , BPF_INSN_SMODRBE, BPF_INSN_SMOD32IBE, BPF_INSN_SMOD32RBE, BPF_INSN_NEGBE
- , BPF_INSN_NEG32BE, BPF_INSN_MOVIBE, BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE
- , BPF_INSN_MOV32RBE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
- , BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSW
- , BPF_INSN_LDABSH, BPF_INSN_LDABSB, BPF_INSN_LDABSDW, BPF_INSN_LDINDWLE
- , BPF_INSN_LDINDHLE, BPF_INSN_LDINDBLE, BPF_INSN_LDINDDWLE, BPF_INSN_LDINDWBE
- , BPF_INSN_LDINDHBE, BPF_INSN_LDINDBBE, BPF_INSN_LDINDDWBE, BPF_INSN_LDXWLE
- , BPF_INSN_LDXHLE, BPF_INSN_LDXBLE, BPF_INSN_LDXDWLE, BPF_INSN_STXWLE
- , BPF_INSN_STXHLE, BPF_INSN_STXBLE, BPF_INSN_STXDWLE, BPF_INSN_LDXWBE
- , BPF_INSN_LDXHBE, BPF_INSN_LDXBBE, BPF_INSN_LDXDWBE, BPF_INSN_STXWBE
- , BPF_INSN_STXHBE, BPF_INSN_STXBBE, BPF_INSN_STXDWBE, BPF_INSN_STBLE
- , BPF_INSN_STHLE, BPF_INSN_STWLE, BPF_INSN_STDWLE, BPF_INSN_STBBE
- , BPF_INSN_STHBE, BPF_INSN_STWBE, BPF_INSN_STDWBE, BPF_INSN_JEQILE
- , BPF_INSN_JEQRLE, BPF_INSN_JEQ32ILE, BPF_INSN_JEQ32RLE, BPF_INSN_JGTILE
- , BPF_INSN_JGTRLE, BPF_INSN_JGT32ILE, BPF_INSN_JGT32RLE, BPF_INSN_JGEILE
- , BPF_INSN_JGERLE, BPF_INSN_JGE32ILE, BPF_INSN_JGE32RLE, BPF_INSN_JLTILE
- , BPF_INSN_JLTRLE, BPF_INSN_JLT32ILE, BPF_INSN_JLT32RLE, BPF_INSN_JLEILE
- , BPF_INSN_JLERLE, BPF_INSN_JLE32ILE, BPF_INSN_JLE32RLE, BPF_INSN_JSETILE
- , BPF_INSN_JSETRLE, BPF_INSN_JSET32ILE, BPF_INSN_JSET32RLE, BPF_INSN_JNEILE
- , BPF_INSN_JNERLE, BPF_INSN_JNE32ILE, BPF_INSN_JNE32RLE, BPF_INSN_JSGTILE
- , BPF_INSN_JSGTRLE, BPF_INSN_JSGT32ILE, BPF_INSN_JSGT32RLE, BPF_INSN_JSGEILE
- , BPF_INSN_JSGERLE, BPF_INSN_JSGE32ILE, BPF_INSN_JSGE32RLE, BPF_INSN_JSLTILE
- , BPF_INSN_JSLTRLE, BPF_INSN_JSLT32ILE, BPF_INSN_JSLT32RLE, BPF_INSN_JSLEILE
- , BPF_INSN_JSLERLE, BPF_INSN_JSLE32ILE, BPF_INSN_JSLE32RLE, BPF_INSN_JEQIBE
- , BPF_INSN_JEQRBE, BPF_INSN_JEQ32IBE, BPF_INSN_JEQ32RBE, BPF_INSN_JGTIBE
- , BPF_INSN_JGTRBE, BPF_INSN_JGT32IBE, BPF_INSN_JGT32RBE, BPF_INSN_JGEIBE
- , BPF_INSN_JGERBE, BPF_INSN_JGE32IBE, BPF_INSN_JGE32RBE, BPF_INSN_JLTIBE
- , BPF_INSN_JLTRBE, BPF_INSN_JLT32IBE, BPF_INSN_JLT32RBE, BPF_INSN_JLEIBE
- , BPF_INSN_JLERBE, BPF_INSN_JLE32IBE, BPF_INSN_JLE32RBE, BPF_INSN_JSETIBE
- , BPF_INSN_JSETRBE, BPF_INSN_JSET32IBE, BPF_INSN_JSET32RBE, BPF_INSN_JNEIBE
- , BPF_INSN_JNERBE, BPF_INSN_JNE32IBE, BPF_INSN_JNE32RBE, BPF_INSN_JSGTIBE
- , BPF_INSN_JSGTRBE, BPF_INSN_JSGT32IBE, BPF_INSN_JSGT32RBE, BPF_INSN_JSGEIBE
- , BPF_INSN_JSGERBE, BPF_INSN_JSGE32IBE, BPF_INSN_JSGE32RBE, BPF_INSN_JSLTIBE
- , BPF_INSN_JSLTRBE, BPF_INSN_JSLT32IBE, BPF_INSN_JSLT32RBE, BPF_INSN_JSLEIBE
- , BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_CALLLE
- , BPF_INSN_CALLBE, BPF_INSN_CALLRLE, BPF_INSN_CALLRBE, BPF_INSN_JA
- , BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE, BPF_INSN_XADDDWBE
- , BPF_INSN_XADDWBE, BPF_INSN_BRKPT
-} CGEN_INSN_TYPE;
-
-/* Index of `invalid' insn place holder. */
-#define CGEN_INSN_INVALID BPF_INSN_INVALID
-
-/* Total number of insns in table. */
-#define MAX_INSNS ((int) BPF_INSN_BRKPT + 1)
-
-/* This struct records data prior to insertion or after extraction. */
-struct cgen_fields
-{
- int length;
- long f_nil;
- long f_anyof;
- long f_op_code;
- long f_op_src;
- long f_op_class;
- long f_op_mode;
- long f_op_size;
- long f_dstle;
- long f_srcle;
- long f_dstbe;
- long f_srcbe;
- long f_regs;
- long f_offset16;
- long f_imm32;
- long f_imm64_a;
- long f_imm64_b;
- long f_imm64_c;
- int64_t f_imm64;
-};
-
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
-
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* BPF_OPC_H */
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
- bfd_bpf_arch) ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
+ bfd_bpf_arch) ta="$ta bpf-dis.lo bpf-opc.lo" ;;
bfd_loongarch_arch) ta="$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo" ;;
"") ;;
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
- bfd_bpf_arch) ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
+ bfd_bpf_arch) ta="$ta bpf-dis.lo bpf-opc.lo" ;;
bfd_loongarch_arch) ta="$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo" ;;
"") ;;
#include "m32c-desc.h"
#endif
-#ifdef ARCH_bpf
-/* XXX this should be including bpf-desc.h instead of this hackery,
- but at the moment it is not possible to include several CGEN
- generated *-desc.h files simultaneously. To be fixed in
- CGEN... */
-
-# ifdef ARCH_m32c
-enum epbf_isa_attr
-{
- ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE, ISA_EBPFMAX
-};
-# else
-# include "bpf-desc.h"
-# define ISA_EBPFMAX ISA_MAX
-# endif
-#endif /* ARCH_bpf */
-
disassembler_ftype
disassembler (enum bfd_architecture a,
bool big ATTRIBUTE_UNUSED,
#ifdef ARCH_loongarch
print_loongarch_disassembler_options (stream);
#endif
-
+#ifdef ARCH_bpf
+ print_bpf_disassembler_options (stream);
+#endif
return;
}
#endif
#ifdef ARCH_bpf
case bfd_arch_bpf:
+ /* XXX option for dialect */
+ info->created_styled_output = true;
+#if 0
info->endian_code = BFD_ENDIAN_LITTLE;
if (!info->private_data)
{
cgen_bitset_set (info->private_data, ISA_XBPFLE);
}
}
+#endif
break;
#endif
#ifdef ARCH_pru
default:
return;
-#ifdef ARCH_bpf
- case bfd_arch_bpf:
-#endif
#ifdef ARCH_m32c
case bfd_arch_m32c:
#endif
-#if defined ARCH_bpf || defined ARCH_m32c
+#if defined ARCH_m32c
if (info->private_data)
{
CGEN_BITSET *mask = info->private_data;
projects / binutils-gdb.git / commitdiff