config: Use shared cache config for regressions

This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 0b5f9e1823ab5885438b761da244ca9ffe020bd1..867d0cb2e2e6076f78b7d097e7ee21f60de6d17a 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -40,22 +40,40 @@
 
 from m5.objects import *
 
-class L1Cache(BaseCache):
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+class L1(BaseCache):
     assoc = 2
-    block_size = 64
     hit_latency = 2
     response_latency = 2
-    mshrs = 10
+    block_size = 64
+    mshrs = 4
     tgts_per_mshr = 20
     is_top_level = True
 
-class L2Cache(BaseCache):
+class L2(BaseCache):
     assoc = 8
     block_size = 64
     hit_latency = 20
     response_latency = 20
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
+    size = '1kB'
     tgts_per_mshr = 12
+    forward_snoops = False
+    is_top_level = True
 
 class PageTableWalkerCache(BaseCache):
     assoc = 2
@@ -67,13 +85,3 @@ class PageTableWalkerCache(BaseCache):
     tgts_per_mshr = 12
     is_top_level = True
 
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    forward_snoops = False
-    is_top_level = True

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 0b10f576609ae34b89c936ee353302dfb16f2d89..b02b43d03bdaaa93eb525ce5406d18b2ca5ddd2c 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -29,30 +29,7 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
+from Caches import *
 
 nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]

diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 729f3bd8f0438b909cb4a5b5de93673c11153535..c4317ec23efd3e95dc322278191809097b54884b 100644 (file)
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -31,59 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
 #the system
@@ -94,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 7dfec362ec7794d6954dc5f7c66f9712758539d9..44ba51b3c1b11c1ecc2b9a8a19fd976ea8651565 100644 (file)
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -31,61 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-    is_top_level = True
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-    is_top_level = True
-
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
 #the system
@@ -96,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index bfbf926dc44a10d9ffdad5cf55c76e8e8ccc8471..99017900839f5cd6f8e657fa17744b6e91549eec 100644 (file)
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -31,60 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
-
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
 #the system
@@ -95,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index a791b3983c5d32a1f2b8aec09fe2c678e7f1842c..248a1d41b2ca80918d45033f5278af6fe75f6dfd 100644 (file)
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -39,45 +39,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
@@ -89,7 +51,7 @@ system.cpu = cpu
 cpu.addCheckerCpu()
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 599ef6f8cec2521b3f00baf98f253659468e7c30..cc4fa236fb48adf031be5f93fdcaa3ac7c9411ea 100644 (file)
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -31,50 +31,13 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 from Benchmarks import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 698c6dd14925e911e1f99de43cc78b475e11f965..6f98309fe812f0f0a21c133d727e5210365b20d2 100644 (file)
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -30,45 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index 9bf2fd70dc00e732abbcb0db9f97a4f000f85fc0..b26272a9104f05fed34107ccda4720eb29ac5b1e 100644 (file)
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -31,50 +31,13 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 from Benchmarks import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 05ef0dd63b6cf7145875448e85946fefa95d3767..2d1efe3fe871dfb18c141939e985ada56da0224d 100644 (file)
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -30,44 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
@@ -77,7 +40,7 @@ system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index ee5ffaf0668adb80293a915add9b8dbab3e84974..1c86f42bfc7b01511fb70f83f945eb556e2ca37f 100644 (file)
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -31,50 +31,13 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 from Benchmarks import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 28cd3163fe19a118eed73ab5dbd6a37e54fce514..4bb641e808481478c56698e6b5d7972d8afe41a4 100644 (file)
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -30,45 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
+from Caches import *
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 163ac3ba690e0ada9b568158521ffe87322bb41a..0d7e817e0f810b427ed2c319aec44b77d3b7651c 100644 (file)
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpu = InOrderCPU(cpu_id=0)
@@ -82,7 +43,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index 5ba14753d8c93dd392eb05fe3260a2e52eb607bc..a1564f8f8d3353b065788bf715684f3329313473 100644 (file)
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpus
 #create the l1/l2 bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 2920c878aeac99d5da625d2ff8fd327d7821997f..18cbf1db1dd59c2b32dedbcef0627db04d552183 100644 (file)
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 851ec847b00d3ee436b06133163c0e11d9d89864..1f63ff7a84b43b35a0410abf08b14b4c030ae5fa 100644 (file)
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -30,51 +30,13 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index c583f9d2bd6616c37ddfddefd40e3ead434285be..9c7e5c265d4a909e1aa418c4ee0c1b7eee5872be 100644 (file)
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -30,45 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index e69db34387011e2b89242f9f9a9a3c72a68486f4..8bac5bd903abf154090d6ba4524ce21819da0c7f 100644 (file)
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -30,51 +30,13 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('timing')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index e71d758468863b24f32404ae4778322bab365b5b..60b4e47f475686d4fc4325b36be0663284106b33 100644 (file)
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
+from Caches import *
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave