RA[n+20:n+31] <- DPD_TO_BCD( (RS)[n+22:n+31] )
Special Registers Altered:
+
None
# Add and Generate Sixes
RT <- (¬c) & 0x6666_6666_6666_6666
Special Registers Altered:
+
None
# Convert Binary Coded Decimal To Declets
RA[n+22:n+31] <- BCD_TO_DPD( (RS)[n+20:n+31] )
Special Registers Altered:
+
None
RT <- [0]*56 || MEM(EA, 1)
Special Registers Altered:
+
None
# Load Byte and Zero Indexed
RT <- [0] * 56 || MEM(EA, 1)
Special Registers Altered:
+
None
# Load Byte and Zero with Update
RA <- EA
Special Registers Altered:
+
None
# Load Byte and Zero with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Halfword and Zero
RT <- [0] * 48 || MEM(EA, 2)
Special Registers Altered:
+
None
# Load Halfword and Zero Indexed
RT <- [0] * 48 || MEM(EA, 2)
Special Registers Altered:
+
None
# Load Halfword and Zero with Update
RA <- EA
Special Registers Altered:
+
None
# Load Halfword and Zero with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Halfword Algebraic
RT <- EXTS(MEM(EA, 2))
Special Registers Altered:
+
None
# Load Halfword Algebraic Indexed
RT <- EXTS(MEM(EA, 2))
Special Registers Altered:
+
None
# Load Halfword Algebraic with Update
RA <- EA
Special Registers Altered:
+
None
# Load Halfword Algebraic with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Word and Zero
RT <- [0] * 32 || MEM(EA, 4)
Special Registers Altered:
+
None
# Load Word and Zero Indexed
RT <- [0] * 32 || MEM(EA, 4)
Special Registers Altered:
+
None
# Load Word and Zero with Update
RA <- EA
Special Registers Altered:
+
None
# Load Word and Zero with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Word Algebraic
RT <- EXTS(MEM(EA, 4))
Special Registers Altered:
+
None
# Load Word Algebraic Indexed
RT <- EXTS(MEM(EA, 4))
Special Registers Altered:
+
None
# Load Word Algebraic with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Doubleword
RT <- MEM(EA, 8)
Special Registers Altered:
+
None
# Load Doubleword Indexed
RT <- MEM(EA, 8)
Special Registers Altered:
+
None
# Load Doubleword with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Doubleword with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Load Quadword
RTp <- MEM(EA, 16)
Special Registers Altered:
+
None
# Load Halfword Byte-Reverse Indexed
RT <- [0]*48 || load_data[8:15] || load_data[0:7]
Special Registers Altered:
+
None
# Load Word Byte-Reverse Indexed
|| load_data[8:15] || load_data[0:7]
Special Registers Altered:
+
None
# Load Doubleword Byte-Reverse Indexed
|| load_data[8:15 || load_data[0:7]
Special Registers Altered:
+
None
# Load Multiple Word
MEM(EA, 1) <- (RS)[56:63]
Special Registers Altered:
+
None
# Store Byte Indexed
MEM(EA, 1) <- (RS)[56:63]
Special Registers Altered:
+
None
# Store Byte with Update
RA <- EA
Special Registers Altered:
+
None
# Store Byte with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Store Halfword
MEM(EA, 2) <- (RS)[48:63]
Special Registers Altered:
+
None
# Store Halfword Indexed
MEM(EA, 2) <- (RS)[48:63]
Special Registers Altered:
+
None
# Store Halfword with Update
RA <- EA
Special Registers Altered:
+
None
# Store Halfword with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Store Word
MEM(EA, 4) <- (RS)[32:63]
Special Registers Altered:
+
None
# Store Word Indexed
MEM(EA, 4) <- (RS)[32:63]
Special Registers Altered:
+
None
# Store Word with Update
RA <- EA
Special Registers Altered:
+
None
# Store Word with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Store Doubleword
MEM(EA, 8) <- (RS)
Special Registers Altered:
+
None
# Store Doubleword Indexed
MEM(EA, 8) <- (RS)
Special Registers Altered:
+
None
# Store Doubleword with Update
RA <- EA
Special Registers Altered:
+
None
# Store Doubleword with Update Indexed
RA <- EA
Special Registers Altered:
+
None
# Store Quadword
MEM(EA, 16) <- RSp
Special Registers Altered:
+
None
# Store Halfword Byte-Reverse Indexed
MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
Special Registers Altered:
+
None
# Store Word Byte-Reverse Indexed
||(RS)[32:39]
Special Registers Altered:
+
None
# Store Doubleword Byte-Reverse Indexed
|| (RS)[8:15] || (RS)[0:7]
Special Registers Altered:
+
None
# Store Multiple Word
EA <- EA + 4
Special Registers Altered:
+
None
if (a >u EXTS(SI)) & TO[4] then TRAP
Special Registers Altered:
+
None
# Trap Word
if (a >u b) & TO[4] then TRAP
Special Registers Altered:
+
None
D-Form
if (a >u b) & TO[4] then TRAP
Special Registers Altered:
+
None
# Trap Doubleword
if (a >u b) & TO[4] then TRAP
Special Registers Altered:
+
None
# Integer Select
else RT <- (RB)
Special Registers Altered:
+
None
SPR(n) <- (RS) [32:63]
Special Registers Altered:
+
See spec 3.3.17
# Move From Special Purpose Register
RT <- [0]*32 || SPR(n)
Special Registers Altered:
+
None
# Move to CR from XER Extended
CR[4×BF+32:4×BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
Special Registers Altered:
+
CR field BF
# Move To One Condition Register Field
else CR <- undefined
Special Registers Altered:
+
CR field selected by FXM
# Move To Condition Register Fields
CR <- ((RS)[32:63] & mask) | (CR & ¬mask)
Special Registers Altered:
+
CR fields selected by mask
# Move From One Condition Register Field
RT[4 *n+32:4*n+35] <- CR[4*n+32:4* n+35]
Special Registers Altered:
+
None
# Move From Condition Register
RT <- [0]*32 || CR
Special Registers Altered:
+
None
# Set Boolean
RT <- 0x0000_0000_0000_0000
Special Registers Altered:
+
None
n <- n - 1
Special Registers Altered:
+
None
# Load String Word Indexed
n <- n - 1
Special Registers Altered:
+
None
# Store String Word Immediate
n <- n - 1
Special Registers Altered:
+
None
# Store String Word Indexed
n <- n - 1
Special Registers Altered:
+
None
projects / libreriscv.git / commitdiff