csr/SRAM: prefix page register with memory name

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 264c63c001fd033227dd0e3594afecb03614aaf4..9deb334b77ed7221e5daa727d255a1ee0229b4e0 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -62,7 +62,7 @@ class SRAM:
                self.address = address
                page_bits = _compute_page_bits(self.mem.depth)
                if page_bits:
-                       self._page = RegisterField("page", page_bits)
+                       self._page = RegisterField(self.mem.name_override + "_page", page_bits)
                else:
                        self._page = None
                if bus is None: