synth_xilinx: before abc read +/xilinx/cells_box.v

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0058f626fb49a92a0a1d92cea3332d4b4fe3ced9..c10e42532a93e87ce0c3a365dd267305e2ec3f1a 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass
                {
                        Pass::call(design, "opt -full");
                        Pass::call(design, "techmap -map +/techmap.v");
+                       Pass::call(design, "read_verilog +/xilinx/cells_box.v");
                        if (abc == "abc9")
                                Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
                        else