misc: pass ThreadContext on ISA clear

This patch changes the clear API for the ISAs to pass the ThreadContext
issuing the call. This allows the ISA to carry out maintainance
operations on the TC state.

Change-Id: I40d6cf39c321521a221146aa0fd8f2cf665d39c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25465
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 14ccb5cb87618bfccf9f729515d8376e1caff2d5..89be0158acfe99413d9174995951bff67c6efd66 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -463,9 +463,10 @@ namespace ArmISA
         }
 
       public:
-        void clear();
+        void clear(ThreadContext *tc) { clear(); }
 
       protected:
+        void clear();
         void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
         void clear64(const ArmISAParams *p);
         void initID32(const ArmISAParams *p);

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 0f5f6af7d6103fe257e18abf35da052dbc5e6611..73cb0462ac366445e0d77025e0847bde67f076ad 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -72,8 +72,12 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
+        void clear(ThreadContext *tc) { clear(); }
+
+      protected:
         void clear();
 
+      public:
         void configCP();
 
         unsigned getVPENum(ThreadID tid) const;

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index fb6c2da43b8373773091d192452852adc82c2d71..c82b7bb4122f01ea3ad14581c731704f880d3a51 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -54,11 +54,19 @@ class ISA : public BaseISA
   public:
     typedef PowerISAParams Params;
 
+    void
+    clear(ThreadContext *tc)
+    {
+        clear();
+    }
+
+  protected:
     void
     clear()
     {
     }
 
+  public:
     RegVal
     readMiscRegNoEffect(int misc_reg) const
     {

diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 227b8123331acbe06e848f0dfa64c13900e79622..4bf0fdb058b2c647d927f7cb5a738a9c28e7ab42 100644 (file)
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -68,8 +68,12 @@ class ISA : public BaseISA
   public:
     typedef RiscvISAParams Params;
 
+    void clear(ThreadContext *tc) { clear(); }
+
+  protected:
     void clear();
 
+  public:
     RegVal readMiscRegNoEffect(int misc_reg) const;
     RegVal readMiscReg(int misc_reg, ThreadContext *tc);
     void setMiscRegNoEffect(int misc_reg, RegVal val);

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 0e67fbb9386633eb9a35e1f00e2ae874c6e055dd..63eab2e2c0d3915bec828cad1ebcd6d43481d44d 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -165,7 +165,7 @@ class ISA : public BaseISA
 
   public:
 
-    void clear();
+    void clear(ThreadContext *tc) { clear(); }
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
@@ -176,6 +176,7 @@ class ISA : public BaseISA
     using BaseISA::startup;
 
   protected:
+    void clear();
     bool isHyperPriv() { return hpstate.hpriv; }
     bool isPriv() { return hpstate.hpriv || pstate.priv; }
     bool isNonPriv() { return !isPriv(); }

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index e801dea0e55187ed21bae2309fdc1dacc70ab9b4..774321ac3517de61251ebb44e286b524f0ef1630 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -54,11 +54,12 @@ namespace X86ISA
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
                 ThreadContext *tc);
+        void clear();
 
       public:
         typedef X86ISAParams Params;
 
-        void clear();
+        void clear(ThreadContext *tc) { clear(); }
 
         ISA(Params *p);
         const Params *params() const;

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 5e0b1767b801d550b103661d6aa74289094d0ac1..104e63cab93db5c0bfcebbd12a563d618381bf17 100644 (file)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -197,7 +197,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::clearArchRegs()
 {
-    cpu->isa[thread->threadId()]->clear();
+    cpu->isa[thread->threadId()]->clear(this);
 }
 
 template <class Impl>

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 89bb3d96eb2a177a0b9477787eeab91c4be9485e..d63bf0bf980db7e870f0fed82ac54e0507676ed6 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -296,7 +296,7 @@ class SimpleThread : public ThreadState, public ThreadContext
         for (auto &pred_reg: vecPredRegs)
             pred_reg.reset();
         ccRegs.fill(0);
-        isa->clear();
+        isa->clear(this);
     }
 
     //