fix(ls003.mdwn): Using desc from PowerISA as template for maddedu. Added Luke's chain...

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 1f49463ff167180354770ceb5ddc100de7e41edd..7fb86463b28a397ae79b6c0fcdc3615e60b12ec9 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -114,9 +114,17 @@ Special registers altered:
 
     None
 
-RC is zero-extended (not shifted, not sign-extended), the 128-bit product added
-to it; the lower half of that result stored in RT and the upper half
-in RS.
+The 64-bit operands are (RA), (RB), and (RC).
+RC is zero-extended (not shifted, not sign-extended).
+The 128-bit product of the operands (RA) and (RB) is added to (RC).
+The low-order 64 bits of the 128-bit sum are
+placed into register RT.
+The high-order 64 bits of the 128-bit sum are
+placed into register RS.
+RS is implictly defined as the same register as RC.
+
+All three operands and the result are interpreted as
+unsigned integers.
 
 The differences here to `maddhdu` are that `maddhdu` stores the upper
 half in RT, where `maddedu` stores the upper half in RS.
@@ -126,8 +134,6 @@ performing sign-extension on RC, because RT is the full mathematical result
 modulo 2^64 and sign/zero extension from 64 to 128 bits produces identical
 results modulo 2^64. This is why there is no maddldu instruction.
 
-RS is implictly defined as the same register as RC.
-
 *Programmer's Note:
 As a Scalar Power ISA operation, like `lq` and `stq`, RS=RT+1.
 To achieve a big-integer rolling-accumulation effect:
@@ -145,6 +151,10 @@ Examples:
 ```
 # (r0 * r1) + r2, store lower in r4, upper in r2
 maddedu r4, r0, r1, r2
+
+# Chaining together for larger bigint (see Programmer's Note above)
+maddedu r20,r4,r0,r20
+maddedu r21,r5,r0,r21
 ```
 
 ----------