examples/fir: print Verilog source

diff --git a/examples/fir.py b/examples/fir.py
index e10ff94e046279b6d2e682674645cfb65b749ff6..2119679f6c8c95bffa3787c93607718ac8a41100 100644 (file)
--- a/examples/fir.py
+++ b/examples/fir.py
@@ -76,5 +76,9 @@ def main():
        plt.plot(in_signals)
        plt.plot(out_signals)
        plt.show()
+       
+       # Print the Verilog source for the filter.
+       print(verilog.convert(fir.get_fragment(),
+               ios={fir.i, fir.o}))
 
 main()