AVX-512. 64/n. Add rest of VI1-AVX2: vpack[us]wb.

gcc/
	* config/i386/sse.md
	(define_insn "<sse2_avx2>_packsswb<mask_name>"): Add masking.
	(define_insn "<sse2_avx2>_packuswb<mask_name>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r216181

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ff14980dd31e43a4584a19598313cbae18bae56a..a3f8471e1f90817a281a80abf119ca4a9291bb36 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/sse.md
+       (define_insn "<sse2_avx2>_packsswb<mask_name>"): Add masking.
+       (define_insn "<sse2_avx2>_packuswb<mask_name>"): Ditto.
+
 2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
            Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
            Anna Tikhonova  <anna.tikhonova@intel.com>

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a71f969535c58d077a48efae3ec5523dc494d37c..2673ddf30739b6d82b1d1bd8d7c274e71a99cd96 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10840,21 +10840,21 @@
   DONE;
 })
 
-(define_insn "<sse2_avx2>_packsswb"
-  [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
+(define_insn "<sse2_avx2>_packsswb<mask_name>"
+  [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,v")
        (vec_concat:VI1_AVX2
          (ss_truncate:<ssehalfvecmode>
-           (match_operand:<sseunpackmode> 1 "register_operand" "0,x"))
+           (match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
          (ss_truncate:<ssehalfvecmode>
-           (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,xm"))))]
-  "TARGET_SSE2"
+           (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))]
+  "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packsswb\t{%2, %0|%0, %2}
-   vpacksswb\t{%2, %1, %0|%0, %1, %2}"
+   vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sselog")
    (set_attr "prefix_data16" "1,*")
-   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix" "orig,maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "<sse2_avx2>_packssdw"
@@ -10874,17 +10874,17 @@
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<sse2_avx2>_packuswb"
-  [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
+(define_insn "<sse2_avx2>_packuswb<mask_name>"
+  [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,v")
        (vec_concat:VI1_AVX2
          (us_truncate:<ssehalfvecmode>
-           (match_operand:<sseunpackmode> 1 "register_operand" "0,x"))
+           (match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
          (us_truncate:<ssehalfvecmode>
-           (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,xm"))))]
-  "TARGET_SSE2"
+           (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))]
+  "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packuswb\t{%2, %0|%0, %2}
-   vpackuswb\t{%2, %1, %0|%0, %1, %2}"
+   vpackuswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sselog")
    (set_attr "prefix_data16" "1,*")