Bundle the uart16550 core file
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 24 Oct 2022 04:25:39 +0000 (15:25 +1100)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 24 Oct 2022 10:39:00 +0000 (21:39 +1100)
We already carry the UART verilog source, so we may as well use it
instead of requiring fusesoc to import it from its library

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
microwatt.core
uart16550/uart16550.core [new file with mode: 0644]

index bb6770d03f5e4e58e93d4e908a24d007a3c4bdac..febd3978f8f3807d6bd4832f935cb9a1a0003993 100644 (file)
@@ -138,7 +138,7 @@ filesets:
       depend : [":microwatt:litesdcard"]
 
   uart16550:
-      depend : ["::uart16550"]
+      depend : [":microwatt:uart16550"]
 
 targets:
   nexys_a7:
diff --git a/uart16550/uart16550.core b/uart16550/uart16550.core
new file mode 100644 (file)
index 0000000..cdb98da
--- /dev/null
@@ -0,0 +1,28 @@
+CAPI=2:
+name : :microwatt:uart16550:1.5.5-r1
+description : UART 16550 transceiver
+
+filesets:
+  rtl:
+    files:
+      - uart_defines.v: {is_include_file: true}
+      - raminfr.v
+      - uart_receiver.v
+      - uart_regs.v
+      - uart_rfifo.v
+      - uart_sync_flops.v
+      - uart_tfifo.v
+      - uart_top.v
+      - uart_transmitter.v
+      - uart_wb.v
+    file_type: verilogSource
+
+targets:
+  default:
+    filesets: [rtl]
+
+provider:
+  name    : github
+  user    : olofk
+  repo    : uart16550
+  version : v1.5.5