2003-01-14 Chris Demetriou <cgd@broadcom.com>

        * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index b9653ef7c78cb4cea55165ceeddc14e184b7c80d..0482ab2b0a286de54d7ebb338a5b7c3b3c481198 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,7 @@
+2003-01-14  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
+
 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 
        * mips.igen (EI, DI): Remove.

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index a4308761acf910b160d768be20fd98b339ce890c..81fb2001b27498a9141428e7021c65c2db0e7ba2 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -4271,6 +4271,22 @@
 }
 
 
+010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
+"luxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mipsV:
+*mips64:
+{
+  address_word base = GPR[BASE];
+  address_word index = GPR[INDEX];
+  address_word vaddr = base + index;
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
+  if ((vaddr & 0x7) != 0)
+    index -= (vaddr & 0x7);
+  COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
+}
+
 
 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
@@ -4743,6 +4759,24 @@
 }
 
 
+010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
+"suxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mipsV:
+*mips64:
+{
+  unsigned64 v;
+  address_word base = GPR[BASE];
+  address_word index = GPR[INDEX];
+  address_word vaddr = base + index;
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
+  if ((vaddr & 0x7) != 0)
+    index -= (vaddr & 0x7);
+  do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
+}
+
+
 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
 "sqrt.%s<FMT> f<FD>, f<FS>"
 *mipsII: