DRIVER_SOURCES = r200_context.c \
r200_ioctl.c \
- r200_lock.c \
r200_state.c \
r200_state_init.c \
r200_cmdbuf.c \
r200_fragshader.c \
r200_vertprog.c \
radeon_screen.c \
+ common_lock.c \
+ common_misc.c \
$(EGL_SOURCES)
C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
radeon_screen.h \
radeon_bo_legacy.h \
radeon_buffer.h \
- common_context.h
+ common_context.h \
+ common_lock.c \
+ common_lock.h \
+ common_misc.h \
+ common_misc.c
##### TARGETS #####
{ NULL, 0 }
};
+static void r200_get_lock(radeonContextPtr radeon)
+{
+ r200ContextPtr rmesa = (r200ContextPtr)radeon;
+ drm_radeon_sarea_t *sarea = radeon->sarea;
+ int i;
+
+ R200_STATECHANGE( rmesa, ctx );
+ if (rmesa->radeon.sarea->tiling_enabled) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
+ }
+ else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE;
+
+ if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) {
+ sarea->ctx_owner = rmesa->radeon.dri.hwContext;
+ }
+
+ for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
+ DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] );
+ }
+}
+
+static void r200_init_vtbl(radeonContextPtr radeon)
+{
+ radeon->vtbl.get_lock = r200_get_lock;
+ radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
+}
/* Create the device specific rendering context.
*/
rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
if ( !rmesa )
return GL_FALSE;
-
+
+ r200_init_vtbl(&rmesa->radeon);
/* init exp fog table data */
r200InitStaticFogData();
r200FlushCmdBuf( rmesa, __FUNCTION__ );
}
- if (rmesa->state.scissor.pClipRects) {
- FREE(rmesa->state.scissor.pClipRects);
- rmesa->state.scissor.pClipRects = NULL;
+ if (rmesa->radeon.state.scissor.pClipRects) {
+ FREE(rmesa->radeon.state.scissor.pClipRects);
+ rmesa->radeon.state.scissor.pClipRects = NULL;
}
if ( release_texture_heaps ) {
#include "radeon_screen.h"
#include "common_context.h"
+#include "common_misc.h"
struct r200_context;
typedef struct r200_context r200ContextRec;
struct r200_state {
/* Derived state for internal purposes:
*/
- struct radeon_colorbuffer_state color;
- struct radeon_depthbuffer_state depth;
- struct radeon_scissor_state scissor;
- struct radeon_stencilbuffer_state stencil;
struct radeon_stipple_state stipple;
struct r200_texture_state texture;
GLuint envneeded;
if (R200_DEBUG & DEBUG_SANITY) {
- if (rmesa->state.scissor.enabled)
+ if (rmesa->radeon.state.scissor.enabled)
ret = r200SanityCmdBuffer( rmesa,
- rmesa->state.scissor.numClipRects,
- rmesa->state.scissor.pClipRects);
+ rmesa->radeon.state.scissor.numClipRects,
+ rmesa->radeon.state.scissor.pClipRects);
else
ret = r200SanityCmdBuffer( rmesa,
rmesa->radeon.numClipRects,
cmd.bufsz = rmesa->store.cmd_used;
cmd.buf = rmesa->store.cmd_buf;
- if (rmesa->state.scissor.enabled) {
- cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = (drm_clip_rect_t *)rmesa->state.scissor.pClipRects;
+ if (rmesa->radeon.state.scissor.enabled) {
+ cmd.nbox = rmesa->radeon.state.scissor.numClipRects;
+ cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.state.scissor.pClipRects;
} else {
cmd.nbox = rmesa->radeon.numClipRects;
cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects;
{
int ret;
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
ret = r200FlushCmdBufLocked( rmesa, caller );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (ret) {
fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret);
dma.request_sizes = &size;
dma.granted_count = 0;
- LOCK_HARDWARE(rmesa); /* no need to validate */
+ LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */
while (1) {
ret = drmDMA( fd, &dma );
}
if (rmesa->radeon.do_usleeps) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
}
- UNLOCK_HARDWARE(rmesa);
+ UNLOCK_HARDWARE(&rmesa->radeon);
if (R200_DEBUG & DEBUG_DMA)
fprintf(stderr, "Allocated buffer %d\n", index);
;
}
else {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
r200WaitIrq( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
rmesa->radeon.irqsEmitted = 10;
}
}
else {
while (r200GetLastFrame (rmesa) < sarea->last_frame) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (rmesa->radeon.do_usleeps)
DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
}
}
R200_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* Throttle the frame rate -- only allow one pending swap buffers
r200WaitForFrameCompletion( rmesa );
if (!rect)
{
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
driWaitForVBlank( dPriv, & missed_target );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
nbox = dPriv->numClipRects; /* must be in locked region */
if ( ret ) {
fprintf( stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
exit( 1 );
}
}
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (!rect)
{
rmesa->hw.all_dirty = GL_TRUE;
}
R200_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
if (!dPriv->numClipRects) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
usleep( 10000 ); /* throttle invisible client 10ms */
return;
}
* request at a time.
*/
r200WaitForFrameCompletion( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
driWaitForVBlank( dPriv, & missed_target );
if ( missed_target ) {
rmesa->radeon.swap_missed_count++;
(void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust );
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if ( ret ) {
fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret );
}
{
- LOCK_HARDWARE( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if ( dPriv->numClipRects == 0 )
return;
}
mask &= ~BUFFER_BIT_DEPTH;
}
- if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) {
+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) {
flags |= RADEON_STENCIL;
mask &= ~BUFFER_BIT_STENCIL;
}
flags |= RADEON_USE_COMP_ZBUF;
/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
flags |= RADEON_USE_HIERZ; */
- if (!(rmesa->state.stencil.hwBuffer) ||
+ if (!(rmesa->radeon.state.stencil.hwBuffer) ||
((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
- ((rmesa->state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) {
+ ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) {
flags |= RADEON_CLEAR_FASTZ;
}
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* compute region after locking: */
cx = ctx->DrawBuffer->_Xmin;
}
if (rmesa->radeon.do_usleeps) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
}
rmesa->radeon.sarea->nbox = n;
clear.flags = flags;
- clear.clear_color = rmesa->state.color.clear;
- clear.clear_depth = rmesa->state.depth.clear; /* needed for hyperz */
+ clear.clear_color = rmesa->radeon.state.color.clear;
+ clear.clear_depth = rmesa->radeon.state.depth.clear; /* needed for hyperz */
clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- clear.depth_mask = rmesa->state.stencil.clear;
+ clear.depth_mask = rmesa->radeon.state.stencil.clear;
clear.depth_boxes = depth_boxes;
n--;
if ( ret ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret );
exit( 1 );
}
}
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
rmesa->hw.all_dirty = GL_TRUE;
}
} while (ret && ++i < 100);
if ( ret < 0 ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
fprintf( stderr, "Error: R200 timed out... exiting\n" );
exit( -1 );
}
static void r200WaitForIdle( r200ContextPtr rmesa )
{
- LOCK_HARDWARE(rmesa);
+ LOCK_HARDWARE(&rmesa->radeon);
r200WaitForIdleLocked( rmesa );
- UNLOCK_HARDWARE(rmesa);
+ UNLOCK_HARDWARE(&rmesa->radeon);
}
r200Flush( ctx );
if (rmesa->radeon.do_irqs) {
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
r200EmitIrqLocked( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
r200WaitIrq( rmesa );
}
else
#ifndef __R200_LOCK_H__
#define __R200_LOCK_H__
-extern void r200GetLock( r200ContextPtr rmesa, GLuint flags );
-
-/* Turn DEBUG_LOCKING on to find locking conflicts.
- */
-#define DEBUG_LOCKING 0
-
-#if DEBUG_LOCKING
-extern char *prevLockFile;
-extern int prevLockLine;
-
-#define DEBUG_LOCK() \
- do { \
- prevLockFile = (__FILE__); \
- prevLockLine = (__LINE__); \
- } while (0)
-
-#define DEBUG_RESET() \
- do { \
- prevLockFile = 0; \
- prevLockLine = 0; \
- } while (0)
-
-#define DEBUG_CHECK_LOCK() \
- do { \
- if ( prevLockFile ) { \
- fprintf( stderr, \
- "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \
- prevLockFile, prevLockLine, __FILE__, __LINE__ ); \
- exit( 1 ); \
- } \
- } while (0)
-
-#else
-
-#define DEBUG_LOCK()
-#define DEBUG_RESET()
-#define DEBUG_CHECK_LOCK()
-
-#endif
-
-/*
- * !!! We may want to separate locks from locks with validation. This
- * could be used to improve performance for those things commands that
- * do not do any drawing !!!
- */
-
-
-/* Lock the hardware and validate our state.
- */
-#define LOCK_HARDWARE( rmesa ) \
- do { \
- char __ret = 0; \
- DEBUG_CHECK_LOCK(); \
- DRM_CAS( rmesa->radeon.dri.hwLock, rmesa->radeon.dri.hwContext, \
- (DRM_LOCK_HELD | rmesa->radeon.dri.hwContext), __ret ); \
- if ( __ret ) \
- r200GetLock( rmesa, 0 ); \
- DEBUG_LOCK(); \
- } while (0)
-
-#define UNLOCK_HARDWARE( rmesa ) \
- do { \
- DRM_UNLOCK( rmesa->radeon.dri.fd, \
- rmesa->radeon.dri.hwLock, \
- rmesa->radeon.dri.hwContext ); \
- DEBUG_RESET(); \
- } while (0)
+#include "common_lock.h"
#endif /* __R200_LOCK_H__ */
* a full command buffer expects to be called unlocked. As a
* workaround, immediately flush the buffer on aquiring the lock.
*/
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
if (rmesa->store.cmd_used)
r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height,
&size)) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (R200_DEBUG & DEBUG_PIXEL)
fprintf(stderr, "%s totally clipped -- nothing to do\n",
__FUNCTION__);
r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
}
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
r200Finish( ctx ); /* required by GL */
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
if (rmesa->store.cmd_used)
r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
if (!clip_pixelrect(ctx, ctx->DrawBuffer,
&x, &y, &width, &height,
&size)) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
return;
}
r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
r200WaitForIdleLocked( rmesa ); /* required by GL */
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
}
r200ContextPtr rmesa = R200_CONTEXT( ctx );
R200_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
r200WaitForIdleLocked( rmesa );
/* Read & rewrite the first pixel in the frame buffer. This should
{
r200ContextPtr rmesa = R200_CONTEXT( ctx );
_swrast_flush( ctx );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
}
void r200InitSpanFuncs( GLcontext *ctx )
switch ( format ) {
case R200_DEPTH_FORMAT_16BIT_INT_Z:
- rmesa->state.depth.clear = d * 0x0000ffff;
+ rmesa->radeon.state.depth.clear = d * 0x0000ffff;
break;
case R200_DEPTH_FORMAT_24BIT_INT_Z:
- rmesa->state.depth.clear = d * 0x00ffffff;
+ rmesa->radeon.state.depth.clear = d * 0x00ffffff;
break;
}
}
*/
-static GLboolean intersect_rect( drm_clip_rect_t *out,
- drm_clip_rect_t *a,
- drm_clip_rect_t *b )
-{
- *out = *a;
- if ( b->x1 > out->x1 ) out->x1 = b->x1;
- if ( b->y1 > out->y1 ) out->y1 = b->y1;
- if ( b->x2 < out->x2 ) out->x2 = b->x2;
- if ( b->y2 < out->y2 ) out->y2 = b->y2;
- if ( out->x1 >= out->x2 ) return GL_FALSE;
- if ( out->y1 >= out->y2 ) return GL_FALSE;
- return GL_TRUE;
-}
-
-
-void r200RecalcScissorRects( r200ContextPtr rmesa )
-{
- drm_clip_rect_t *out;
- int i;
-
- /* Grow cliprect store?
- */
- if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
- while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
- rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */
- rmesa->state.scissor.numAllocedClipRects *= 2;
- }
-
- if (rmesa->state.scissor.pClipRects)
- FREE(rmesa->state.scissor.pClipRects);
-
- rmesa->state.scissor.pClipRects =
- MALLOC( rmesa->state.scissor.numAllocedClipRects *
- sizeof(drm_clip_rect_t) );
-
- if ( rmesa->state.scissor.pClipRects == NULL ) {
- rmesa->state.scissor.numAllocedClipRects = 0;
- return;
- }
- }
-
- out = rmesa->state.scissor.pClipRects;
- rmesa->state.scissor.numClipRects = 0;
-
- for ( i = 0 ; i < rmesa->radeon.numClipRects ; i++ ) {
- if ( intersect_rect( out,
- &rmesa->radeon.pClipRects[i],
- &rmesa->state.scissor.rect ) ) {
- rmesa->state.scissor.numClipRects++;
- out++;
- }
- }
-}
-
-
-static void r200UpdateScissor( GLcontext *ctx )
-{
- r200ContextPtr rmesa = R200_CONTEXT(ctx);
-
- if ( rmesa->radeon.dri.drawable ) {
- __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
-
- int x = ctx->Scissor.X;
- int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
- int w = ctx->Scissor.X + ctx->Scissor.Width - 1;
- int h = dPriv->h - ctx->Scissor.Y - 1;
-
- rmesa->state.scissor.rect.x1 = x + dPriv->x;
- rmesa->state.scissor.rect.y1 = y + dPriv->y;
- rmesa->state.scissor.rect.x2 = w + dPriv->x + 1;
- rmesa->state.scissor.rect.y2 = h + dPriv->y + 1;
-
- r200RecalcScissorRects( rmesa );
- }
-}
-
-
static void r200Scissor( GLcontext *ctx,
GLint x, GLint y, GLsizei w, GLsizei h )
{
if ( ctx->Scissor.Enabled ) {
R200_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */
- r200UpdateScissor( ctx );
+ radeonUpdateScissor( ctx );
}
}
GLfloat factor, GLfloat units )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- float_ui32_type constant = { units * rmesa->state.depth.scale };
+ float_ui32_type constant = { units * rmesa->radeon.state.depth.scale };
float_ui32_type factoru = { factor };
/* factor *= 2; */
/* TODO: push this into cmd mechanism
*/
R200_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* FIXME: Use window x,y offsets into stipple RAM.
*/
stipple.mask = rmesa->state.stipple.mask;
drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE,
&stipple, sizeof(stipple) );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
}
static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- rmesa->state.stencil.clear =
+ rmesa->radeon.state.stencil.clear =
((GLuint) (ctx->Stencil.Clear & 0xff) |
(0xff << R200_STENCIL_MASK_SHIFT) |
((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT));
float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X };
float_ui32_type sy = { - v[MAT_SY] };
float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y };
- float_ui32_type sz = { v[MAT_SZ] * rmesa->state.depth.scale };
- float_ui32_type tz = { v[MAT_TZ] * rmesa->state.depth.scale };
+ float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
+ float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
R200_FIREVERTICES( rmesa );
R200_STATECHANGE( rmesa, vpt );
CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]);
CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]);
- rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
+ rmesa->radeon.state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
color[0], color[1],
color[2], color[3] );
}
}
-/*
- * Set up the cliprects for either front or back-buffer drawing.
- */
-void r200SetCliprects( r200ContextPtr rmesa )
-{
- __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable;
- __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable;
- GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate;
- GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate;
-
- if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BIT_BACK_LEFT) {
- /* Can't ignore 2d windows if we are page flipping.
- */
- if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) {
- rmesa->radeon.numClipRects = drawable->numClipRects;
- rmesa->radeon.pClipRects = drawable->pClipRects;
- }
- else {
- rmesa->radeon.numClipRects = drawable->numBackClipRects;
- rmesa->radeon.pClipRects = drawable->pBackClipRects;
- }
- }
- else {
- /* front buffer (or none, or multiple buffers) */
- rmesa->radeon.numClipRects = drawable->numClipRects;
- rmesa->radeon.pClipRects = drawable->pClipRects;
- }
-
- if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) {
- _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb,
- drawable->w, drawable->h);
- draw_fb->Initialized = GL_TRUE;
- }
-
- if (drawable != readable) {
- if ((read_fb->Width != readable->w) ||
- (read_fb->Height != readable->h)) {
- _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb,
- readable->w, readable->h);
- read_fb->Initialized = GL_TRUE;
- }
- }
-
- if (rmesa->state.scissor.enabled)
- r200RecalcScissorRects( rmesa );
-
- rmesa->radeon.lastStamp = drawable->lastStamp;
-}
-
-
static void r200DrawBuffer( GLcontext *ctx, GLenum mode )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
return;
}
- r200SetCliprects( rmesa );
+ radeonSetCliprects( &rmesa->radeon );
/* We'll set the drawing engine's offset/pitch parameters later
* when we update other state.
R200_STATECHANGE(rmesa, ctx );
if ( state ) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable;
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable;
} else {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_DITHER_ENABLE;
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
}
break;
case GL_SCISSOR_TEST:
R200_FIREVERTICES( rmesa );
- rmesa->state.scissor.enabled = state;
+ rmesa->radeon.state.scissor.enabled = state;
r200UpdateScissor( ctx );
break;
case GL_STENCIL_TEST:
- if ( rmesa->state.stencil.hwBuffer ) {
+ if ( rmesa->radeon.state.stencil.hwBuffer ) {
R200_STATECHANGE( rmesa, ctx );
if ( state ) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE;
exit( -1 );
}
- rmesa->state.color.clear = 0x00000000;
+ rmesa->radeon.state.color.clear = 0x00000000;
switch ( ctx->Visual.depthBits ) {
case 16:
- rmesa->state.depth.clear = 0x0000ffff;
- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
+ rmesa->radeon.state.depth.clear = 0x0000ffff;
+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
- rmesa->state.stencil.clear = 0x00000000;
+ rmesa->radeon.state.stencil.clear = 0x00000000;
break;
case 24:
- rmesa->state.depth.clear = 0x00ffffff;
- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
+ rmesa->radeon.state.depth.clear = 0x00ffffff;
+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
- rmesa->state.stencil.clear = 0xffff0000;
+ rmesa->radeon.state.stencil.clear = 0xffff0000;
break;
default:
fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
}
/* Only have hw stencil when depth buffer is 24 bits deep */
- rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
+ rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
ctx->Visual.depthBits == 24 );
rmesa->radeon.Fallback = 0;
}
#if 000
if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
- rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch;
+ rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
+ rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch;
} else {
- rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch;
+ rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
+ rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch;
}
- rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
- rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch;
+ rmesa->state.pixel.readOffset = rmesa->radeon.state.color.drawOffset;
+ rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch;
#endif
rmesa->hw.max_state_size = 0;
}
if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
DRI_CONF_ROUND_ROUND )
- rmesa->state.color.roundEnable = R200_ROUND_ENABLE;
+ rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
else
- rmesa->state.color.roundEnable = 0;
+ rmesa->radeon.state.color.roundEnable = 0;
if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
DRI_CONF_COLOR_REDUCTION_DITHER )
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
else
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
#if 000
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->radeon.state.color.drawOffset +
rmesa->radeon.radeonScreen->fbLocation)
& R200_COLOROFFSET_MASK);
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->radeon.state.color.drawPitch &
R200_COLORPITCH_MASK) |
R200_COLOR_ENDIAN_NO_SWAP);
#else
/* Update window height
*/
- LOCK_HARDWARE( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
+ UNLOCK_HARDWARE( &rmesa->radeon );
h = rmesa->radeon.dri.drawable->h + rmesa->radeon.dri.drawable->y;
px += rmesa->radeon.dri.drawable->x;
}
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
do {
ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
&tex, sizeof(drm_radeon_texture_t) );
}
} while ( ret == -EAGAIN );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if ( ret ) {
fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
r200Finish( rmesa->radeon.glCtx );
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
if ( t->base.memBlock == NULL ) {
int heap;
heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
(driTextureObject *) t );
if ( heap == -1 ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
return -1;
}
/* Let the world know we've used this memory recently.
*/
driUpdateTextureLRU( (driTextureObject *) t );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
/* Upload any images that are new */
if (t->base.dirty_images[face]) {
radeon_bo_legacy.c \
radeon_cs_legacy.c \
radeon_screen.c \
+ common_lock.c \
+ common_misc.c \
radeon_context.c \
radeon_ioctl.c \
- radeon_lock.c \
radeon_span.c \
radeon_state.c \
r300_context.c \
radeon_cs_legacy.c \
radeon_bo_legacy.h \
radeon_cs_legacy.h \
- common_context.h
+ common_context.h \
+ common_lock.c \
+ common_lock.h \
+ common_misc.c \
+ common_misc.h
DRI_LIB_DEPS += -ldrm_radeon
struct radeon_renderbuffer *rrb;
uint32_t zbpitch;
- rrb = r300->radeon.state.depth_buffer;
+ rrb = r300->radeon.state.depth.rrb;
if (!rrb)
return;
_mesa_unlock_context_textures(ctx);
}
+static void r300_get_lock(radeonContextPtr rmesa)
+{
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
+
+ if (sarea->ctx_owner != rmesa->dri.hwContext) {
+ sarea->ctx_owner = rmesa->dri.hwContext;
+ if (!rmesa->radeonScreen->kernel_mm)
+ radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
+ }
+}
+
+static void r300_init_vtbl(radeonContextPtr radeon)
+{
+ radeon->vtbl.get_lock = r300_get_lock;
+ radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
+}
+
/* Create the device specific rendering context.
*/
GLboolean r300CreateContext(const __GLcontextModes * glVisual,
if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
hw_tcl_on = future_hw_tcl_on = 0;
+ r300_init_vtbl(&r300->radeon);
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
* State cache
*/
-struct r300_depthbuffer_state {
- GLfloat scale;
-};
-
-struct r300_stencilbuffer_state {
- GLboolean hw_stencil;
-};
-
/* Vertex shader state */
/* Perhaps more if we store programs in vmem? */
};
struct r300_state {
- struct r300_depthbuffer_state depth;
struct r300_texture_state texture;
int sw_tcl_inputs[VERT_ATTRIB_MAX];
struct r300_vertex_shader_state vertex_shader;
DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
They are the same as tnl->render_inputs for fixed pipeline */
- struct r300_stencilbuffer_state stencil;
-
};
#define R300_FALLBACK_NONE 0
mask &= ~BUFFER_BIT_DEPTH;
}
- if ((mask & BUFFER_BIT_STENCIL) && r300->state.stencil.hw_stencil) {
+ if ((mask & BUFFER_BIT_STENCIL) && r300->radeon.state.stencil.hwBuffer) {
bits |= CLEARBUFFER_STENCIL;
mask &= ~BUFFER_BIT_STENCIL;
}
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
- if (r300->state.stencil.hw_stencil) {
+ if (r300->radeon.state.stencil.hwBuffer) {
R300_STATECHANGE(r300, zs);
if (state) {
r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
GLfloat sy = -v[MAT_SY];
GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
- GLfloat sz = v[MAT_SZ] * rmesa->state.depth.scale;
- GLfloat tz = v[MAT_TZ] * rmesa->state.depth.scale;
+ GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale;
+ GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale;
R300_FIREVERTICES(rmesa);
R300_STATECHANGE(rmesa, vpt);
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
- rrb = r300->radeon.state.depth_buffer;
+ rrb = r300->radeon.state.depth.rrb;
if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) {
/* XXX: Turn off when clearing buffers ? */
r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE;
switch (ctx->Visual.depthBits) {
case 16:
- r300->state.depth.scale = 1.0 / (GLfloat) 0xffff;
+ r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffff;
depth_fmt = R300_DEPTHFORMAT_16BIT_INT_Z;
break;
case 24:
- r300->state.depth.scale = 1.0 / (GLfloat) 0xffffff;
+ r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffffff;
depth_fmt = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
break;
default:
}
/* Only have hw stencil when depth buffer is 24 bits deep */
- r300->state.stencil.hw_stencil = (ctx->Visual.stencilBits > 0 &&
- ctx->Visual.depthBits == 24);
+ r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 &&
+ ctx->Visual.depthBits == 24);
memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
radeon_update_renderbuffers(driContextPriv, driReadPriv);
radeon->state.color.rrb =
(void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- radeon->state.depth_buffer =
+ radeon->state.depth.rrb =
(void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer;
}
#include "radeon_screen.h"
#include "common_context.h"
+#include "common_misc.h"
#if R200_MERGED
extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
* Scissoring
*/
-static GLboolean intersect_rect(drm_clip_rect_t * out,
- drm_clip_rect_t * a, drm_clip_rect_t * b)
-{
- *out = *a;
- if (b->x1 > out->x1)
- out->x1 = b->x1;
- if (b->y1 > out->y1)
- out->y1 = b->y1;
- if (b->x2 < out->x2)
- out->x2 = b->x2;
- if (b->y2 < out->y2)
- out->y2 = b->y2;
- if (out->x1 >= out->x2)
- return GL_FALSE;
- if (out->y1 >= out->y2)
- return GL_FALSE;
- return GL_TRUE;
-}
-
-void radeonRecalcScissorRects(radeonContextPtr radeon)
-{
- drm_clip_rect_t *out;
- int i;
-
- /* Grow cliprect store?
- */
- if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) {
- while (radeon->state.scissor.numAllocedClipRects <
- radeon->numClipRects) {
- radeon->state.scissor.numAllocedClipRects += 1; /* zero case */
- radeon->state.scissor.numAllocedClipRects *= 2;
- }
-
- if (radeon->state.scissor.pClipRects)
- FREE(radeon->state.scissor.pClipRects);
-
- radeon->state.scissor.pClipRects =
- MALLOC(radeon->state.scissor.numAllocedClipRects *
- sizeof(drm_clip_rect_t));
-
- if (radeon->state.scissor.pClipRects == NULL) {
- radeon->state.scissor.numAllocedClipRects = 0;
- return;
- }
- }
-
- out = radeon->state.scissor.pClipRects;
- radeon->state.scissor.numClipRects = 0;
-
- for (i = 0; i < radeon->numClipRects; i++) {
- if (intersect_rect(out,
- &radeon->pClipRects[i],
- &radeon->state.scissor.rect)) {
- radeon->state.scissor.numClipRects++;
- out++;
- }
- }
-}
-
-void radeonUpdateScissor(GLcontext* ctx)
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-
- if (radeon->dri.drawable) {
- __DRIdrawablePrivate *dPriv = radeon->dri.drawable;
- int x1 = dPriv->x + ctx->Scissor.X;
- int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height);
-
- radeon->state.scissor.rect.x1 = x1;
- radeon->state.scissor.rect.y1 = y1;
- radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width;
- radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height;
-
- radeonRecalcScissorRects(radeon);
- }
-}
-
static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h)
{
if (ctx->Scissor.Enabled) {
}
}
-
-/**
- * Update cliprects and scissors.
- */
-void radeonSetCliprects(radeonContextPtr radeon)
-{
- __DRIdrawablePrivate *const drawable = radeon->dri.drawable;
- __DRIdrawablePrivate *const readable = radeon->dri.readable;
- GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate;
- GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate;
-
- if (!radeon->radeonScreen->driScreen->dri2.enabled) {
- if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
- /* Can't ignore 2d windows if we are page flipping. */
- if (drawable->numBackClipRects == 0 || radeon->doPageFlip ||
- radeon->sarea->pfCurrentPage == 1) {
- radeon->numClipRects = drawable->numClipRects;
- radeon->pClipRects = drawable->pClipRects;
- } else {
- radeon->numClipRects = drawable->numBackClipRects;
- radeon->pClipRects = drawable->pBackClipRects;
- }
- } else {
- /* front buffer (or none, or multiple buffers */
- radeon->numClipRects = drawable->numClipRects;
- radeon->pClipRects = drawable->pClipRects;
- }
- }
-
- if ((draw_fb->Width != drawable->w) ||
- (draw_fb->Height != drawable->h)) {
- _mesa_resize_framebuffer(radeon->glCtx, draw_fb,
- drawable->w, drawable->h);
- draw_fb->Initialized = GL_TRUE;
- }
-
- if (drawable != readable) {
- if ((read_fb->Width != readable->w) ||
- (read_fb->Height != readable->h)) {
- _mesa_resize_framebuffer(radeon->glCtx, read_fb,
- readable->w, readable->h);
- read_fb->Initialized = GL_TRUE;
- }
- }
-
- if (radeon->state.scissor.enabled)
- radeonRecalcScissorRects(radeon);
-
- radeon->lastStamp = drawable->lastStamp;
-}
-
-
/**
* Handle common enable bits.
* Called as a fallback by r200Enable/r300Enable.
#ifndef __RADEON_STATE_H__
#define __RADEON_STATE_H__
-extern void radeonRecalcScissorRects(radeonContextPtr radeon);
-extern void radeonSetCliprects(radeonContextPtr radeon);
-extern void radeonUpdateScissor(GLcontext* ctx);
-
extern void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state);
extern void radeonInitState(radeonContextPtr radeon);
DRIVER_SOURCES = \
radeon_context.c \
radeon_ioctl.c \
- radeon_lock.c \
radeon_screen.c \
radeon_state.c \
radeon_state_init.c \
radeon_swtcl.c \
radeon_span.c \
radeon_maos.c \
- radeon_sanity.c
+ radeon_sanity.c \
+ common_lock.c \
+ common_misc.c
C_SOURCES = \
$(COMMON_SOURCES) \
typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
-struct r300_radeon_state {
+struct radeon_state {
struct radeon_colorbuffer_state color;
+ struct radeon_depthbuffer_state depth;
struct radeon_scissor_state scissor;
- struct radeon_renderbuffer *depth_buffer;
+ struct radeon_stencilbuffer_state stencil;
};
struct radeon_context {
GLuint swap_missed_count;
/* Derived state - for r300 only */
- struct r300_radeon_state state;
+ struct radeon_state state;
/* Configuration cache
*/
driOptionCache optionCache;
+ struct {
+ void (*get_lock)(radeonContextPtr radeon);
+ void (*update_viewport_offset)(GLcontext *ctx);
+ } vtbl;
};
#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
--- /dev/null
+/**************************************************************************
+
+Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
+ VA Linux Systems Inc., Fremont, California.
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
+
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ * Gareth Hughes <gareth@valinux.com>
+ * Keith Whitwell <keith@tungstengraphics.com>
+ * Kevin E. Martin <martin@valinux.com>
+ */
+
+#include "main/glheader.h"
+#include "main/mtypes.h"
+#include "main/colormac.h"
+#include "dri_util.h"
+#include "radeon_screen.h"
+#include "common_context.h"
+#include "common_lock.h"
+
+#include "drirenderbuffer.h"
+
+#if DEBUG_LOCKING
+char *prevLockFile = NULL;
+int prevLockLine = 0;
+#endif
+
+#ifdef RADEON_COMMON_FOR_R300
+/* Turn on/off page flipping according to the flags in the sarea:
+ */
+void radeonUpdatePageFlipping(radeonContextPtr rmesa)
+{
+ int use_back;
+ __DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
+ GLframebuffer *fb = drawable->driverPrivate;
+
+ rmesa->doPageFlip = rmesa->sarea->pfState;
+ if (rmesa->glCtx->WinSysDrawBuffer) {
+ r300UpdateDrawBuffer(rmesa->glCtx);
+ }
+
+ use_back = rmesa->glCtx->DrawBuffer ?
+ (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] ==
+ BUFFER_BACK_LEFT) : 1;
+ use_back ^= (rmesa->sarea->pfCurrentPage == 1);
+
+ if (use_back)
+ rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ else
+ rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+
+ rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+}
+#else
+/* Turn on/off page flipping according to the flags in the sarea:
+ */
+static void radeonUpdatePageFlipping(radeonContextPtr rmesa)
+{
+ rmesa->doPageFlip = rmesa->sarea->pfState;
+ if (rmesa->glCtx->WinSysDrawBuffer) {
+ driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
+ rmesa->sarea->pfCurrentPage);
+ }
+}
+#endif
+
+/* Update the hardware state. This is called if another context has
+ * grabbed the hardware lock, which includes the X server. This
+ * function also updates the driver's window state after the X server
+ * moves, resizes or restacks a window -- the change will be reflected
+ * in the drawable position and clip rects. Since the X server grabs
+ * the hardware lock when it changes the window state, this routine will
+ * automatically be called after such a change.
+ */
+void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
+{
+ __DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
+ __DRIdrawablePrivate *const readable = rmesa->dri.readable;
+ __DRIscreenPrivate *sPriv = rmesa->dri.screen;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
+
+ assert(drawable != NULL);
+
+ drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags);
+
+ /* The window might have moved, so we might need to get new clip
+ * rects.
+ *
+ * NOTE: This releases and regrabs the hw lock to allow the X server
+ * to respond to the DRI protocol request for new drawable info.
+ * Since the hardware state depends on having the latest drawable
+ * clip rects, all state checking must be done _after_ this call.
+ */
+ DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable);
+ if (drawable != readable) {
+ DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable);
+ }
+
+ if (rmesa->lastStamp != drawable->lastStamp) {
+ radeonUpdatePageFlipping(rmesa);
+ radeonSetCliprects(rmesa);
+ rmesa->vtbl.update_viewport_offset(rmesa->glCtx);
+ driUpdateFramebufferSize(rmesa->glCtx, drawable);
+ }
+
+ rmesa->vtbl.get_lock(rmesa);
+
+ rmesa->lost_context = GL_TRUE;
+}
--- /dev/null
+/**************************************************************************
+
+Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
+ VA Linux Systems Inc., Fremont, California.
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
+
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ * Gareth Hughes <gareth@valinux.com>
+ * Keith Whitwell <keith@tungstengraphics.com>
+ * Kevin E. Martin <martin@valinux.com>
+ */
+
+#ifndef COMMON_LOCK_H
+#define COMMON_LOCK_H
+extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags);
+
+/* Turn DEBUG_LOCKING on to find locking conflicts.
+ */
+#define DEBUG_LOCKING 0
+
+#if DEBUG_LOCKING
+extern char *prevLockFile;
+extern int prevLockLine;
+
+#define DEBUG_LOCK() \
+ do { \
+ prevLockFile = (__FILE__); \
+ prevLockLine = (__LINE__); \
+ } while (0)
+
+#define DEBUG_RESET() \
+ do { \
+ prevLockFile = 0; \
+ prevLockLine = 0; \
+ } while (0)
+
+#define DEBUG_CHECK_LOCK() \
+ do { \
+ if ( prevLockFile ) { \
+ fprintf( stderr, \
+ "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \
+ prevLockFile, prevLockLine, __FILE__, __LINE__ ); \
+ exit( 1 ); \
+ } \
+ } while (0)
+
+#else
+
+#define DEBUG_LOCK()
+#define DEBUG_RESET()
+#define DEBUG_CHECK_LOCK()
+
+#endif
+
+/*
+ * !!! We may want to separate locks from locks with validation. This
+ * could be used to improve performance for those things commands that
+ * do not do any drawing !!!
+ */
+
+/* Lock the hardware and validate our state.
+ */
+#define LOCK_HARDWARE( rmesa ) \
+ do { \
+ char __ret = 0; \
+ DEBUG_CHECK_LOCK(); \
+ DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \
+ (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \
+ if ( __ret ) \
+ radeonGetLock( (rmesa), 0 ); \
+ DEBUG_LOCK(); \
+ } while (0)
+
+#define UNLOCK_HARDWARE( rmesa ) \
+ do { \
+ DRM_UNLOCK( (rmesa)->dri.fd, \
+ (rmesa)->dri.hwLock, \
+ (rmesa)->dri.hwContext ); \
+ DEBUG_RESET(); \
+ } while (0)
+
+#endif
--- /dev/null
+/**************************************************************************
+
+Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+
+The Weather Channel (TM) funded Tungsten Graphics to develop the
+initial release of the Radeon 8500 driver under the XFree86 license.
+This notice must be preserved.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ * Keith Whitwell <keith@tungstengraphics.com>
+ */
+
+#include "main/glheader.h"
+#include "main/imports.h"
+#include "main/api_arrayelt.h"
+#include "main/enums.h"
+#include "main/colormac.h"
+#include "main/light.h"
+#include "main/framebuffer.h"
+
+#include "swrast/swrast.h"
+#include "vbo/vbo.h"
+#include "tnl/tnl.h"
+#include "tnl/t_pipeline.h"
+#include "swrast_setup/swrast_setup.h"
+
+#include "dri_util.h"
+#include "radeon_drm.h"
+#include "radeon_screen.h"
+#include "common_context.h"
+#include "common_misc.h"
+/* =============================================================
+ * Scissoring
+ */
+
+static GLboolean intersect_rect(drm_clip_rect_t * out,
+ drm_clip_rect_t * a, drm_clip_rect_t * b)
+{
+ *out = *a;
+ if (b->x1 > out->x1)
+ out->x1 = b->x1;
+ if (b->y1 > out->y1)
+ out->y1 = b->y1;
+ if (b->x2 < out->x2)
+ out->x2 = b->x2;
+ if (b->y2 < out->y2)
+ out->y2 = b->y2;
+ if (out->x1 >= out->x2)
+ return GL_FALSE;
+ if (out->y1 >= out->y2)
+ return GL_FALSE;
+ return GL_TRUE;
+}
+
+void radeonRecalcScissorRects(radeonContextPtr radeon)
+{
+ drm_clip_rect_t *out;
+ int i;
+
+ /* Grow cliprect store?
+ */
+ if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) {
+ while (radeon->state.scissor.numAllocedClipRects <
+ radeon->numClipRects) {
+ radeon->state.scissor.numAllocedClipRects += 1; /* zero case */
+ radeon->state.scissor.numAllocedClipRects *= 2;
+ }
+
+ if (radeon->state.scissor.pClipRects)
+ FREE(radeon->state.scissor.pClipRects);
+
+ radeon->state.scissor.pClipRects =
+ MALLOC(radeon->state.scissor.numAllocedClipRects *
+ sizeof(drm_clip_rect_t));
+
+ if (radeon->state.scissor.pClipRects == NULL) {
+ radeon->state.scissor.numAllocedClipRects = 0;
+ return;
+ }
+ }
+
+ out = radeon->state.scissor.pClipRects;
+ radeon->state.scissor.numClipRects = 0;
+
+ for (i = 0; i < radeon->numClipRects; i++) {
+ if (intersect_rect(out,
+ &radeon->pClipRects[i],
+ &radeon->state.scissor.rect)) {
+ radeon->state.scissor.numClipRects++;
+ out++;
+ }
+ }
+}
+
+/**
+ * Update cliprects and scissors.
+ */
+void radeonSetCliprects(radeonContextPtr radeon)
+{
+ __DRIdrawablePrivate *const drawable = radeon->dri.drawable;
+ __DRIdrawablePrivate *const readable = radeon->dri.readable;
+ GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate;
+ GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate;
+
+ if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+ if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
+ /* Can't ignore 2d windows if we are page flipping. */
+ if (drawable->numBackClipRects == 0 || radeon->doPageFlip ||
+ radeon->sarea->pfCurrentPage == 1) {
+ radeon->numClipRects = drawable->numClipRects;
+ radeon->pClipRects = drawable->pClipRects;
+ } else {
+ radeon->numClipRects = drawable->numBackClipRects;
+ radeon->pClipRects = drawable->pBackClipRects;
+ }
+ } else {
+ /* front buffer (or none, or multiple buffers */
+ radeon->numClipRects = drawable->numClipRects;
+ radeon->pClipRects = drawable->pClipRects;
+ }
+ }
+
+ if ((draw_fb->Width != drawable->w) ||
+ (draw_fb->Height != drawable->h)) {
+ _mesa_resize_framebuffer(radeon->glCtx, draw_fb,
+ drawable->w, drawable->h);
+ draw_fb->Initialized = GL_TRUE;
+ }
+
+ if (drawable != readable) {
+ if ((read_fb->Width != readable->w) ||
+ (read_fb->Height != readable->h)) {
+ _mesa_resize_framebuffer(radeon->glCtx, read_fb,
+ readable->w, readable->h);
+ read_fb->Initialized = GL_TRUE;
+ }
+ }
+
+ if (radeon->state.scissor.enabled)
+ radeonRecalcScissorRects(radeon);
+
+ radeon->lastStamp = drawable->lastStamp;
+}
+
+void radeonUpdateScissor( GLcontext *ctx )
+{
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+
+ if ( rmesa->dri.drawable ) {
+ __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+
+ int x = ctx->Scissor.X;
+ int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
+ int w = ctx->Scissor.X + ctx->Scissor.Width - 1;
+ int h = dPriv->h - ctx->Scissor.Y - 1;
+
+ rmesa->state.scissor.rect.x1 = x + dPriv->x;
+ rmesa->state.scissor.rect.y1 = y + dPriv->y;
+ rmesa->state.scissor.rect.x2 = w + dPriv->x + 1;
+ rmesa->state.scissor.rect.y2 = h + dPriv->y + 1;
+
+ radeonRecalcScissorRects( rmesa );
+ }
+}
--- /dev/null
+#ifndef COMMON_MISC_H
+#define COMMON_MISC_H
+
+void radeonRecalcScissorRects(radeonContextPtr radeon);
+void radeonSetCliprects(radeonContextPtr radeon);
+void radeonUpdateScissor( GLcontext *ctx );
+
+#endif
{ NULL, 0 }
};
+static void r100_get_lock(radeonContextPtr radeon)
+{
+ r100ContextPtr rmesa = (r100ContextPtr)radeon;
+ drm_radeon_sarea_t *sarea = radeon->sarea;
+
+ RADEON_STATECHANGE(rmesa, ctx);
+ if (rmesa->radeon.sarea->tiling_enabled) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
+ RADEON_COLOR_TILE_ENABLE;
+ } else {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
+ ~RADEON_COLOR_TILE_ENABLE;
+ }
+
+ if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
+ int i;
+ sarea->ctx_owner = rmesa->radeon.dri.hwContext;
+
+ for (i = 0; i < rmesa->radeon.nr_heaps; i++) {
+ DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]);
+ }
+ }
+}
+
+static void r100_init_vtbl(radeonContextPtr radeon)
+{
+ radeon->vtbl.get_lock = r100_get_lock;
+ radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
+}
/* Create the device specific context.
*/
if ( !rmesa )
return GL_FALSE;
+ r100_init_vtbl(&rmesa->radeon);
+
/* init exp fog table data */
radeonInitStaticFogData();
_mesa_vector4f_free( &rmesa->tcl.ObjClean );
- if (rmesa->state.scissor.pClipRects) {
- FREE(rmesa->state.scissor.pClipRects);
- rmesa->state.scissor.pClipRects = NULL;
+ if (rmesa->radeon.state.scissor.pClipRects) {
+ FREE(rmesa->radeon.state.scissor.pClipRects);
+ rmesa->radeon.state.scissor.pClipRects = NULL;
}
if ( release_texture_heaps ) {
#include "radeon_screen.h"
#include "common_context.h"
+#include "common_misc.h"
struct r100_context;
};
-struct radeon_state {
- struct radeon_colorbuffer_state color;
- struct radeon_depthbuffer_state depth;
- struct radeon_scissor_state scissor;
- struct radeon_stencilbuffer_state stencil;
+struct r100_state {
struct radeon_stipple_state stipple;
struct radeon_texture_state texture;
};
/* Driver and hardware state management
*/
struct radeon_hw_state hw;
- struct radeon_state state;
+ struct r100_state state;
/* Vertex buffers
*/
if (RADEON_DEBUG & DEBUG_SANITY) {
- if (rmesa->state.scissor.enabled)
+ if (rmesa->radeon.state.scissor.enabled)
ret = radeonSanityCmdBuffer( rmesa,
- rmesa->state.scissor.numClipRects,
- rmesa->state.scissor.pClipRects);
+ rmesa->radeon.state.scissor.numClipRects,
+ rmesa->radeon.state.scissor.pClipRects);
else
ret = radeonSanityCmdBuffer( rmesa,
rmesa->radeon.numClipRects,
cmd.bufsz = rmesa->store.cmd_used;
cmd.buf = rmesa->store.cmd_buf;
- if (rmesa->state.scissor.enabled) {
- cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = rmesa->state.scissor.pClipRects;
+ if (rmesa->radeon.state.scissor.enabled) {
+ cmd.nbox = rmesa->radeon.state.scissor.numClipRects;
+ cmd.boxes = rmesa->radeon.state.scissor.pClipRects;
} else {
cmd.nbox = rmesa->radeon.numClipRects;
cmd.boxes = rmesa->radeon.pClipRects;
int ret;
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
ret = radeonFlushCmdBufLocked( rmesa, caller );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (ret) {
fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret);
dma.request_sizes = &size;
dma.granted_count = 0;
- LOCK_HARDWARE(rmesa); /* no need to validate */
+ LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */
ret = drmDMA( fd, &dma );
ret = drmDMA( fd, &dma );
if ( ret != 0 ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
fprintf( stderr, "Error: Could not get dma buffer... exiting\n" );
exit( -1 );
}
}
- UNLOCK_HARDWARE(rmesa);
+ UNLOCK_HARDWARE(&rmesa->radeon);
if (RADEON_DEBUG & DEBUG_DMA)
fprintf(stderr, "Allocated buffer %d\n", index);
;
}
else {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
radeonWaitIrq( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
rmesa->radeon.irqsEmitted = 10;
}
}
else {
while (radeonGetLastFrame (rmesa) < sarea->last_frame) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (rmesa->radeon.do_usleeps)
DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
}
}
}
RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* Throttle the frame rate -- only allow one pending swap buffers
* request at a time.
radeonWaitForFrameCompletion( rmesa );
if (!rect)
{
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
driWaitForVBlank( dPriv, & missed_target );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
nbox = dPriv->numClipRects; /* must be in locked region */
if ( ret ) {
fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
exit( 1 );
}
}
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if (!rect)
{
psp = dPriv->driScreenPriv;
}
RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* Need to do this for the perf box placement:
*/
* request at a time.
*/
radeonWaitForFrameCompletion( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
driWaitForVBlank( dPriv, & missed_target );
if ( missed_target ) {
rmesa->radeon.swap_missed_count++;
(void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust );
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if ( ret ) {
fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret );
}
{
- LOCK_HARDWARE( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if ( dPriv->numClipRects == 0 )
return;
}
mask &= ~BUFFER_BIT_DEPTH;
}
- if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) {
+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) {
flags |= RADEON_STENCIL;
mask &= ~BUFFER_BIT_STENCIL;
}
flags |= RADEON_USE_COMP_ZBUF;
/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
flags |= RADEON_USE_HIERZ; */
- if (!(rmesa->state.stencil.hwBuffer) ||
+ if (!(rmesa->radeon.state.stencil.hwBuffer) ||
((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
- ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
+ ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
flags |= RADEON_CLEAR_FASTZ;
}
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* compute region after locking: */
cx = ctx->DrawBuffer->_Xmin;
}
if ( rmesa->radeon.do_usleeps ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
}
}
rmesa->radeon.sarea->nbox = n;
clear.flags = flags;
- clear.clear_color = rmesa->state.color.clear;
- clear.clear_depth = rmesa->state.depth.clear;
+ clear.clear_color = rmesa->radeon.state.color.clear;
+ clear.clear_depth = rmesa->radeon.state.depth.clear;
clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- clear.depth_mask = rmesa->state.stencil.clear;
+ clear.depth_mask = rmesa->radeon.state.stencil.clear;
clear.depth_boxes = depth_boxes;
n--;
depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
depth_boxes[n].f[CLEAR_DEPTH] =
- (float)rmesa->state.depth.clear;
+ (float)rmesa->radeon.state.depth.clear;
}
ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR,
&clear, sizeof(drm_radeon_clear_t));
if ( ret ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret );
exit( 1 );
}
}
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
rmesa->hw.all_dirty = GL_TRUE;
}
} while ( ( ret == -EBUSY ) && ( to++ < RADEON_TIMEOUT ) );
if ( ret < 0 ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
fprintf( stderr, "Error: Radeon timed out... exiting\n" );
exit( -1 );
}
static void radeonWaitForIdle( r100ContextPtr rmesa )
{
- LOCK_HARDWARE(rmesa);
+ LOCK_HARDWARE(&rmesa->radeon);
radeonWaitForIdleLocked( rmesa );
- UNLOCK_HARDWARE(rmesa);
+ UNLOCK_HARDWARE(&rmesa->radeon);
}
radeonFlush( ctx );
if (rmesa->radeon.do_irqs) {
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
radeonEmitIrqLocked( rmesa );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
radeonWaitIrq( rmesa );
}
else
#ifndef __RADEON_LOCK_H__
#define __RADEON_LOCK_H__
-extern void radeonGetLock(r100ContextPtr rmesa, GLuint flags);
-
-/* Turn DEBUG_LOCKING on to find locking conflicts.
- */
-#define DEBUG_LOCKING 0
-
-#if DEBUG_LOCKING
-extern char *prevLockFile;
-extern int prevLockLine;
-
-#define DEBUG_LOCK() \
- do { \
- prevLockFile = (__FILE__); \
- prevLockLine = (__LINE__); \
- } while (0)
-
-#define DEBUG_RESET() \
- do { \
- prevLockFile = 0; \
- prevLockLine = 0; \
- } while (0)
-
-#define DEBUG_CHECK_LOCK() \
- do { \
- if ( prevLockFile ) { \
- fprintf( stderr, \
- "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \
- prevLockFile, prevLockLine, __FILE__, __LINE__ ); \
- exit( 1 ); \
- } \
- } while (0)
-
-#else
-
-#define DEBUG_LOCK()
-#define DEBUG_RESET()
-#define DEBUG_CHECK_LOCK()
-
-#endif
-
-/*
- * !!! We may want to separate locks from locks with validation. This
- * could be used to improve performance for those things commands that
- * do not do any drawing !!!
- */
-
-/* Lock the hardware and validate our state.
- */
-#define LOCK_HARDWARE( rmesa ) \
- do { \
- char __ret = 0; \
- DEBUG_CHECK_LOCK(); \
- DRM_CAS( (rmesa)->radeon.dri.hwLock, (rmesa)->radeon.dri.hwContext, \
- (DRM_LOCK_HELD | (rmesa)->radeon.dri.hwContext), __ret ); \
- if ( __ret ) \
- radeonGetLock( (rmesa), 0 ); \
- DEBUG_LOCK(); \
- } while (0)
-
-#define UNLOCK_HARDWARE( rmesa ) \
- do { \
- DRM_UNLOCK( (rmesa)->radeon.dri.fd, \
- (rmesa)->radeon.dri.hwLock, \
- (rmesa)->radeon.dri.hwContext ); \
- DEBUG_RESET(); \
- } while (0)
+#include "common_lock.h"
#endif /* __RADEON_LOCK_H__ */
#ifdef COMPILE_R300
r300ContextPtr r300 = (r300ContextPtr) rmesa;
R300_FIREVERTICES(r300);
- LOCK_HARDWARE(rmesa);
#else
r100ContextPtr r100 = (r100ContextPtr) rmesa;
RADEON_FIREVERTICES(r100);
- LOCK_HARDWARE(r100);
#endif
-
+ LOCK_HARDWARE(rmesa);
radeonWaitForIdleLocked(rmesa);
}
static void radeonSpanRenderFinish(GLcontext * ctx)
{
- r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
_swrast_flush(ctx);
UNLOCK_HARDWARE(rmesa);
}
switch ( format ) {
case RADEON_DEPTH_FORMAT_16BIT_INT_Z:
- rmesa->state.depth.clear = d * 0x0000ffff;
+ rmesa->radeon.state.depth.clear = d * 0x0000ffff;
break;
case RADEON_DEPTH_FORMAT_24BIT_INT_Z:
- rmesa->state.depth.clear = d * 0x00ffffff;
+ rmesa->radeon.state.depth.clear = d * 0x00ffffff;
break;
}
}
/* =============================================================
* Scissoring
*/
-
-
-static GLboolean intersect_rect( drm_clip_rect_t *out,
- drm_clip_rect_t *a,
- drm_clip_rect_t *b )
-{
- *out = *a;
- if ( b->x1 > out->x1 ) out->x1 = b->x1;
- if ( b->y1 > out->y1 ) out->y1 = b->y1;
- if ( b->x2 < out->x2 ) out->x2 = b->x2;
- if ( b->y2 < out->y2 ) out->y2 = b->y2;
- if ( out->x1 >= out->x2 ) return GL_FALSE;
- if ( out->y1 >= out->y2 ) return GL_FALSE;
- return GL_TRUE;
-}
-
-
-void radeonRecalcScissorRects( r100ContextPtr rmesa )
-{
- drm_clip_rect_t *out;
- int i;
-
- /* Grow cliprect store?
- */
- if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
- while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
- rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */
- rmesa->state.scissor.numAllocedClipRects *= 2;
- }
-
- if (rmesa->state.scissor.pClipRects)
- FREE(rmesa->state.scissor.pClipRects);
-
- rmesa->state.scissor.pClipRects =
- MALLOC( rmesa->state.scissor.numAllocedClipRects *
- sizeof(drm_clip_rect_t) );
-
- if ( rmesa->state.scissor.pClipRects == NULL ) {
- rmesa->state.scissor.numAllocedClipRects = 0;
- return;
- }
- }
-
- out = rmesa->state.scissor.pClipRects;
- rmesa->state.scissor.numClipRects = 0;
-
- for ( i = 0 ; i < rmesa->radeon.numClipRects ; i++ ) {
- if ( intersect_rect( out,
- &rmesa->radeon.pClipRects[i],
- &rmesa->state.scissor.rect ) ) {
- rmesa->state.scissor.numClipRects++;
- out++;
- }
- }
-}
-
-
-static void radeonUpdateScissor( GLcontext *ctx )
-{
- r100ContextPtr rmesa = R100_CONTEXT(ctx);
-
- if ( rmesa->radeon.dri.drawable ) {
- __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
-
- int x = ctx->Scissor.X;
- int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
- int w = ctx->Scissor.X + ctx->Scissor.Width - 1;
- int h = dPriv->h - ctx->Scissor.Y - 1;
-
- rmesa->state.scissor.rect.x1 = x + dPriv->x;
- rmesa->state.scissor.rect.y1 = y + dPriv->y;
- rmesa->state.scissor.rect.x2 = w + dPriv->x + 1;
- rmesa->state.scissor.rect.y2 = h + dPriv->y + 1;
-
- radeonRecalcScissorRects( rmesa );
- }
-}
-
-
static void radeonScissor( GLcontext *ctx,
GLint x, GLint y, GLsizei w, GLsizei h )
{
GLfloat factor, GLfloat units )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
- float_ui32_type constant = { units * rmesa->state.depth.scale };
+ float_ui32_type constant = { units * rmesa->radeon.state.depth.scale };
float_ui32_type factoru = { factor };
RADEON_STATECHANGE( rmesa, zbs );
/* TODO: push this into cmd mechanism
*/
RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
/* FIXME: Use window x,y offsets into stipple RAM.
*/
stipple.mask = rmesa->state.stipple.mask;
drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE,
&stipple, sizeof(drm_radeon_stipple_t) );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
}
static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
- rmesa->state.stencil.clear =
+ rmesa->radeon.state.stencil.clear =
((GLuint) (ctx->Stencil.Clear & 0xff) |
(0xff << RADEON_STENCIL_MASK_SHIFT) |
((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT));
float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X };
float_ui32_type sy = { - v[MAT_SY] };
float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y };
- float_ui32_type sz = { v[MAT_SZ] * rmesa->state.depth.scale };
- float_ui32_type tz = { v[MAT_TZ] * rmesa->state.depth.scale };
+ float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
+ float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
RADEON_FIREVERTICES( rmesa );
RADEON_STATECHANGE( rmesa, vpt );
CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
- rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
+ rmesa->radeon.state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
c[0], c[1], c[2], c[3] );
}
}
-/**
- * Set up the cliprects for either front or back-buffer drawing.
- */
-void radeonSetCliprects( r100ContextPtr rmesa )
-{
- __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable;
- __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable;
- GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate;
- GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate;
-
- if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
- /* Can't ignore 2d windows if we are page flipping.
- */
- if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) {
- rmesa->radeon.numClipRects = drawable->numClipRects;
- rmesa->radeon.pClipRects = drawable->pClipRects;
- }
- else {
- rmesa->radeon.numClipRects = drawable->numBackClipRects;
- rmesa->radeon.pClipRects = drawable->pBackClipRects;
- }
- }
- else {
- /* front buffer (or none, or multiple buffers */
- rmesa->radeon.numClipRects = drawable->numClipRects;
- rmesa->radeon.pClipRects = drawable->pClipRects;
- }
-
- if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) {
- _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb,
- drawable->w, drawable->h);
- draw_fb->Initialized = GL_TRUE;
- }
-
- if (drawable != readable) {
- if ((read_fb->Width != readable->w) || (read_fb->Height != readable->h)) {
- _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb,
- readable->w, readable->h);
- read_fb->Initialized = GL_TRUE;
- }
- }
-
- if (rmesa->state.scissor.enabled)
- radeonRecalcScissorRects( rmesa );
-
- rmesa->radeon.lastStamp = drawable->lastStamp;
-}
-
-
/**
* Called via glDrawBuffer.
*/
return;
}
- radeonSetCliprects( rmesa );
+ radeonSetCliprects( &rmesa->radeon );
/* We'll set the drawing engine's offset/pitch parameters later
* when we update other state.
RADEON_STATECHANGE(rmesa, ctx );
if ( state ) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable;
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable;
} else {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_DITHER_ENABLE;
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
}
break;
case GL_SCISSOR_TEST:
RADEON_FIREVERTICES( rmesa );
- rmesa->state.scissor.enabled = state;
+ rmesa->radeon.state.scissor.enabled = state;
radeonUpdateScissor( ctx );
break;
case GL_STENCIL_TEST:
- if ( rmesa->state.stencil.hwBuffer ) {
+ if ( rmesa->radeon.state.stencil.hwBuffer ) {
RADEON_STATECHANGE( rmesa, ctx );
if ( state ) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE;
extern void radeonUpdateMaterial( GLcontext *ctx );
-extern void radeonSetCliprects( r100ContextPtr rmesa );
-extern void radeonRecalcScissorRects( r100ContextPtr rmesa );
extern void radeonUpdateViewportOffset( GLcontext *ctx );
extern void radeonUpdateWindow( GLcontext *ctx );
extern void radeonUpdateDrawBuffer( GLcontext *ctx );
exit( -1 );
}
- rmesa->state.color.clear = 0x00000000;
+ rmesa->radeon.state.color.clear = 0x00000000;
switch ( ctx->Visual.depthBits ) {
case 16:
- rmesa->state.depth.clear = 0x0000ffff;
- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
+ rmesa->radeon.state.depth.clear = 0x0000ffff;
+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
- rmesa->state.stencil.clear = 0x00000000;
+ rmesa->radeon.state.stencil.clear = 0x00000000;
break;
case 24:
- rmesa->state.depth.clear = 0x00ffffff;
- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
+ rmesa->radeon.state.depth.clear = 0x00ffffff;
+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
- rmesa->state.stencil.clear = 0xffff0000;
+ rmesa->radeon.state.stencil.clear = 0xffff0000;
break;
default:
fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
}
/* Only have hw stencil when depth buffer is 24 bits deep */
- rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
+ rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
ctx->Visual.depthBits == 24 );
rmesa->radeon.Fallback = 0;
}
if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
DRI_CONF_ROUND_ROUND )
- rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
+ rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
else
- rmesa->state.color.roundEnable = 0;
+ rmesa->radeon.state.color.roundEnable = 0;
if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
DRI_CONF_COLOR_REDUCTION_DITHER )
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
else
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
rmesa->radeon.radeonScreen->fbLocation)
}
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
do {
ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
&tex, sizeof(drm_radeon_texture_t) );
} while ( ret == -EAGAIN );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
if ( ret ) {
fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
radeonFinish( rmesa->radeon.glCtx );
}
- LOCK_HARDWARE( rmesa );
+ LOCK_HARDWARE( &rmesa->radeon );
if ( t->base.memBlock == NULL ) {
int heap;
heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
(driTextureObject *) t );
if ( heap == -1 ) {
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
return -1;
}
/* Let the world know we've used this memory recently.
*/
driUpdateTextureLRU( (driTextureObject *) t );
- UNLOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( &rmesa->radeon );
/* Upload any images that are new */
projects / mesa.git / commitdiff