stats: updates due to previous mmap and exit_group patches.

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 863245d9da9418109045287d0865b857a3d29713..3f4662e45147e032a7e1016d98f982819ba3ef0a 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -402,7 +402,7 @@ system.cpu.fetch.Insts                      135034231                       # Nu
 system.cpu.fetch.Branches                    28272297                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           11865865                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     113822766                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679444                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                 1679445                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   53                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.IcacheWaitRetryStallCycles          259                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                  32316581                       # Number of cache lines fetched
@@ -669,7 +669,7 @@ system.cpu.commit.op_class_0::total          91053638                       # Cl
 system.cpu.commit.bw_lim_events               4115210                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    217038076                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219583064                       # The number of ROB writes
+system.cpu.rob.rob_writes                   219583065                       # The number of ROB writes
 system.cpu.timesIdled                             319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           16958                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589798                       # Number of Instructions Simulated
@@ -678,7 +678,7 @@ system.cpu.cpi                               1.274156                       # CP
 system.cpu.cpi_total                         1.274156                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.784833                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.784833                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108123919                       # number of integer regfile reads
+system.cpu.int_regfile_reads                108123923                       # number of integer regfile reads
 system.cpu.int_regfile_writes                58738896                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      100                       # number of floating regfile writes

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 4cbab1671d868c43f83d9fdca6d6cfa796571e60..0aa02b40d9e65269dec36cf03639950981d907ec 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes            53956115                       # nu
 system.cpu.num_mem_refs                      27220755                       # number of memory refs
 system.cpu.num_load_insts                    22475911                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  108282001                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               108282000.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          18732304                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                  63822828     70.09%     70.09% # Class of executed instruction

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index cf47ed55202b381485b26c881c20bcab2fb62575..b163f38c3cc3822bf02c0402a845cae3f212cfbd 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes            53956115                       # nu
 system.cpu.num_mem_refs                      27220755                       # number of memory refs
 system.cpu.num_load_insts                    22475911                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  294082436                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               294082435.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          18732304                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                  63822828     70.09%     70.09% # Class of executed instruction

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 7bd8275ff4174fe594b5811af0bd13cd1179564c..c1c8517049f91a8e0a8370a182db76d49341e134 100644 (file)
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes                  90                       # nu
 system.cpu.num_mem_refs                     105711441                       # number of memory refs
 system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  244431648                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               244431647.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              28877736     11.81%     11.81% # Class of executed instruction
 system.cpu.op_class::IntAlu                 109842388     44.94%     56.75% # Class of executed instruction

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 5117716eea2c88e0cb5cffbf90d15c64ec9484fb..86f47af4e503cd748afb88cdf8deedee40b6dd5a 100644 (file)
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes                  90                       # nu
 system.cpu.num_mem_refs                     105711441                       # number of memory refs
 system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  722977060                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               722977059.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              28877736     11.81%     11.81% # Class of executed instruction
 system.cpu.op_class::IntAlu                 109842388     44.94%     56.75% # Class of executed instruction

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 5a7700eb41fdbf27873eaa93e8875853e252a420..afe4ad98b3490404c4e8c140fa53d590b655db7b 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -313,7 +313,7 @@ system.cpu.fetch.Insts                      201519425                       # Nu
 system.cpu.fetch.Branches                    37414357                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           26823716                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                      94568947                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1664994                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                 1664995                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  796                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles         13919                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
@@ -518,11 +518,11 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts        47392313                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            797958                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    117208009                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    117208008                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     2.373494                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     3.089570                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     52857681     45.10%     45.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     52857680     45.10%     45.10% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1     15964987     13.62%     58.72% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2     10970810      9.36%     68.08% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3      8748486      7.46%     75.54% # Number of insts commited each cycle
@@ -534,7 +534,7 @@ system.cpu.commit.committed_per_cycle::8     23468572     20.02%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    117208009                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    117208008                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -582,8 +582,8 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              23468572                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    419324214                       # The number of ROB reads
-system.cpu.rob.rob_writes                   657627212                       # The number of ROB writes
+system.cpu.rob.rob_reads                    419324213                       # The number of ROB reads
+system.cpu.rob.rob_writes                   657627213                       # The number of ROB writes
 system.cpu.timesIdled                             611                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           58315                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
@@ -592,7 +592,7 @@ system.cpu.cpi                               0.783061                       # CP
 system.cpu.cpi_total                         0.783061                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.277040                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.277040                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                493625450                       # number of integer regfile reads
+system.cpu.int_regfile_reads                493625454                       # number of integer regfile reads
 system.cpu.int_regfile_writes               240898259                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       178                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      135                       # number of floating regfile writes

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 109597618381ce73d1df26c9916abb4e7b7a624e..844bb352ad283e4745d5768a93b3818823f25d18 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes            61764861                       # nu
 system.cpu.num_mem_refs                     122219137                       # number of memory refs
 system.cpu.num_load_insts                    90779385                       # Number of load instructions
 system.cpu.num_store_insts                   31439752                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  337900081                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               337900080.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29309705                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                 16695      0.01%      0.01% # Class of executed instruction
 system.cpu.op_class::IntAlu                 155945354     56.06%     56.06% # Class of executed instruction

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index deb1ad7af8bd2bbfd0cee5b3e046dd40b2879aec..f80736adef05de16802786bd1c60e4f51b24a047 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes            61764861                       # nu
 system.cpu.num_mem_refs                     122219137                       # number of memory refs
 system.cpu.num_load_insts                    90779385                       # Number of load instructions
 system.cpu.num_store_insts                   31439752                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  731978130                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               731978129.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29309705                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                 16695      0.01%      0.01% # Class of executed instruction
 system.cpu.op_class::IntAlu                 155945354     56.06%     56.06% # Class of executed instruction
@@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Cl
 system.cpu.op_class::total                  278192465                       # Class of executed instruction
 system.cpu.icache.tags.replacements                24                       # number of replacements
 system.cpu.icache.tags.tagsinuse           665.632508                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           217695357                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs           217695356                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               808                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          269424.946782                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          269424.945545                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   665.632508                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.325016                       # Average percentage of cache occupancy
@@ -139,14 +139,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           46
 system.cpu.icache.tags.age_task_id_blocks_1024::3           23                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          715                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.382812                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         435393138                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        435393138                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    217695357                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       217695357                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     217695357                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        217695357                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    217695357                       # number of overall hits
-system.cpu.icache.overall_hits::total       217695357                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         435393136                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        435393136                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    217695356                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       217695356                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     217695356                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        217695356                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    217695356                       # number of overall hits
+system.cpu.icache.overall_hits::total       217695356                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           808                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
@@ -159,12 +159,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     44230000
 system.cpu.icache.demand_miss_latency::total     44230000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     44230000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     44230000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    217696165                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    217696165                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    217696165                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    217696165                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    217696165                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    217696165                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    217696164                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    217696164                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    217696164                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    217696164                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    217696164                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    217696164                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 97da265c5f1d0a35b042579929d9fc31af55daa1..e3aeba90b6764ffacfe2ebbaaef28c39ef83a50f 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -409,7 +409,7 @@ system.cpu.fetch.Insts                      731737281                       # Nu
 system.cpu.fetch.Branches                   175071152                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           95967885                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     447534266                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14941834                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                14941835                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                 1659                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            92                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles         5427                       # Number of stall cycles due to full MSHR
@@ -677,7 +677,7 @@ system.cpu.commit.op_class_0::total         548694828                       # Cl
 system.cpu.commit.bw_lim_events              13835955                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   1090469902                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334452491                       # The number of ROB writes
+system.cpu.rob.rob_writes                  1334452492                       # The number of ROB writes
 system.cpu.timesIdled                            9125                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          280326                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
@@ -686,7 +686,7 @@ system.cpu.cpi                               0.916475                       # CP
 system.cpu.cpi_total                         0.916475                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.091137                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.091137                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611059108                       # number of integer regfile reads
+system.cpu.int_regfile_reads                611059162                       # number of integer regfile reads
 system.cpu.int_regfile_writes               328109228                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                2170105339                       # number of cc regfile reads

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 867fb0d1df863231bb38088b2461e4dbbe3ffe82..aa15282555578f7ea66f37a6b67ce3df901eb4e6 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes           344080722                       # nu
 system.cpu.num_mem_refs                     172745235                       # number of memory refs
 system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  558724596                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               558724595.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         121548301                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 375610921     68.46%     68.46% # Class of executed instruction

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 2190fa891c52b089bddbde439b02637e9f90f781..a70fb0c6bdbc299f9645d0143ef7817fea3da13f 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes           344080722                       # nu
 system.cpu.num_mem_refs                     172745235                       # number of memory refs
 system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1415078046                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               1415078045.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         121548301                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 375610921     68.46%     68.46% # Class of executed instruction

diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index d2976812f0150a0130ebf63c2a7600c6a0f02ee7..666f127d92278312e15f0d4277baa12c0ae65e9c 100644 (file)
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -332,7 +332,7 @@ system.cpu.fetch.Insts                     1278658073                       # Nu
 system.cpu.fetch.Branches                   231811700                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches          157369245                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     706106364                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                20239876                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                20239877                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                       1021                       # Number of cycles fetch has spent waiting for tlb
 system.cpu.fetch.MiscStallCycles                98431                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles        825605                       # Number of stall cycles due to pending traps
@@ -539,11 +539,11 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts       584047933                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           9837228                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    824173639                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    824173638                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     1.855178                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     2.504108                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    355774645     43.17%     43.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    355774644     43.17%     43.17% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1    174944190     21.23%     64.39% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2     57267566      6.95%     71.34% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3     86311577     10.47%     81.82% # Number of insts commited each cycle
@@ -555,7 +555,7 @@ system.cpu.commit.committed_per_cycle::8     76959576      9.34%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    824173639                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    824173638                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -603,8 +603,8 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              76959576                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2860250697                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4305432555                       # The number of ROB writes
+system.cpu.rob.rob_reads                   2860250696                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4305432556                       # The number of ROB writes
 system.cpu.timesIdled                            2603                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          181705                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
@@ -613,7 +613,7 @@ system.cpu.cpi                               1.092700                       # CP
 system.cpu.cpi_total                         1.092700                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.915164                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.915164                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2763452160                       # number of integer regfile reads
+system.cpu.int_regfile_reads               2763452214                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1467518123                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      6756                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      202                       # number of floating regfile writes

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 4f2dbc45e574dcd4650e902427d27db9217fc0b5..9a6a9e0dc5d314c862335b5ee0cadc6eb0b35e57 100644 (file)
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes           376685745                       # nu
 system.cpu.num_mem_refs                     533262343                       # number of memory refs
 system.cpu.num_load_insts                   384102157                       # Number of load instructions
 system.cpu.num_store_insts                  149160186                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1770458657                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               1770458656.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               1819099      0.12%      0.12% # Class of executed instruction
 system.cpu.op_class::IntAlu                 989721890     64.73%     64.85% # Class of executed instruction

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index bcff242c04e0d95ad89cca9835b0d2eb3acd439b..81d0742cffedfef43abeb70e212ee6ac0247f25e 100644 (file)
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes           376685745                       # nu
 system.cpu.num_mem_refs                     533262343                       # number of memory refs
 system.cpu.num_load_insts                   384102157                       # Number of load instructions
 system.cpu.num_store_insts                  149160186                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3295745698                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               3295745697.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               1819099      0.12%      0.12% # Class of executed instruction
 system.cpu.op_class::IntAlu                 989721890     64.73%     64.85% # Class of executed instruction
@@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Cl
 system.cpu.op_class::total                 1528988702                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           881.356491                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs          1068344252                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs          1068344251                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              2814                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          379653.252310                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          379653.251955                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   881.356491                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.430350                       # Average percentage of cache occupancy
@@ -141,14 +141,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2            7
 system.cpu.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1507                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.762207                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        2136696946                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       2136696946                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1068344252                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    1068344252                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       1068344252                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1068344252                       # number of overall hits
-system.cpu.icache.overall_hits::total      1068344252                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        2136696944                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       2136696944                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst   1068344251                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1068344251                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1068344251                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1068344251                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1068344251                       # number of overall hits
+system.cpu.icache.overall_hits::total      1068344251                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
@@ -161,12 +161,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst    115806000
 system.cpu.icache.demand_miss_latency::total    115806000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst    115806000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total    115806000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1068347066                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1068347066                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   1068347066                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   1068347066                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1068347066                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1068347066                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   1068347065                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1068347065                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1068347065                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1068347065                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1068347065                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1068347065                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 373457bb016c2c8e8d32f2f16097fddc3765666a..784b1e77a92ad51578570e579fe3c3089931bbe6 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -377,7 +377,7 @@ system.cpu.fetch.Insts                      334152318                       # Nu
 system.cpu.fetch.Branches                    37763717                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           24530963                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     210956137                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3511516                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                 3511517                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  130                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            11                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles          514                       # Number of stall cycles due to full MSHR
@@ -646,7 +646,7 @@ system.cpu.commit.op_class_0::total         327812213                       # Cl
 system.cpu.commit.bw_lim_events              10367243                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    561656707                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705358338                       # The number of ROB writes
+system.cpu.rob.rob_writes                   705358339                       # The number of ROB writes
 system.cpu.timesIdled                           49342                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          139797                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037219                       # Number of Instructions Simulated
@@ -655,7 +655,7 @@ system.cpu.cpi                               0.824361                       # CP
 system.cpu.cpi_total                         0.824361                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.213060                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.213060                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331187238                       # number of integer regfile reads
+system.cpu.int_regfile_reads                331187240                       # number of integer regfile reads
 system.cpu.int_regfile_writes               136909181                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                 187100304                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                132166714                       # number of floating regfile writes

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 2a622c7e9cdb7da239044aa016e1ddf5486156a4..607680a6d6fff78a57dbd33646008bf00c8e2f85 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes            76361749                       # nu
 system.cpu.num_mem_refs                     168107829                       # number of memory refs
 system.cpu.num_load_insts                    85732235                       # Number of load instructions
 system.cpu.num_store_insts                   82375594                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  403434628                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               403434627.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          30563490                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 104312492     31.82%     31.82% # Class of executed instruction

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 46629c208121fcf1c3333cfcf364a9ca796eb34e..09b69e57560b2e83dd33f5d2ba03a0ded682cd1e 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes            76361814                       # nu
 system.cpu.num_mem_refs                     168107847                       # number of memory refs
 system.cpu.num_load_insts                    85732248                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1034470822                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               1034470821.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          30563502                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 104312543     31.82%     31.82% # Class of executed instruction

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index b4b37847eda85dae0a3959a01009763d414fc34d..ed6189e7153d418db487144f4d919eb983256f3c 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -420,11 +420,11 @@ system.cpu.numCycles                        815767570                       # nu
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.fetch.icacheStallCycles           84062545                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1200075863                       # Number of instructions fetch has processed
+system.cpu.fetch.Insts                     1200075862                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                   233961455                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches          133292629                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     716015819                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31064710                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                31064711                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  216                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles         1031                       # Number of stall cycles due to full MSHR
@@ -692,7 +692,7 @@ system.cpu.commit.op_class_0::total         788730069                       # Cl
 system.cpu.commit.bw_lim_events              22360845                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   1888573713                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343133825                       # The number of ROB writes
+system.cpu.rob.rob_writes                  2343133826                       # The number of ROB writes
 system.cpu.timesIdled                          646395                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          155573                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649298                       # Number of Instructions Simulated
@@ -701,7 +701,7 @@ system.cpu.cpi                               1.273345                       # CP
 system.cpu.cpi_total                         1.273345                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.785333                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.785333                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995802638                       # number of integer regfile reads
+system.cpu.int_regfile_reads                995802642                       # number of integer regfile reads
 system.cpu.int_regfile_writes               567917186                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                  31889847                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                 22959506                       # number of floating regfile writes

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index ffaf59dc8580df31eef1d77880ed30c963ab7884..b5ba9b69fe8e25fbb41835bf777676ee5ad57912 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes           351919006                       # nu
 system.cpu.num_mem_refs                     381221435                       # number of memory refs
 system.cpu.num_load_insts                   252240938                       # Number of load instructions
 system.cpu.num_store_insts                  128980497                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  791453557                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               791453556.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         137364859                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 385757466     48.91%     48.91% # Class of executed instruction

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 6d64061d2452bcccc6cc656fc8de47746588dc49..b1098c721e7e45b3ec8751e3f53b7ad684094d6c 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes           351919006                       # nu
 system.cpu.num_mem_refs                     381221435                       # number of memory refs
 system.cpu.num_load_insts                   252240938                       # Number of load instructions
 system.cpu.num_store_insts                  128980497                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 2087390168                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               2087390167.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         137364859                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 385757466     48.91%     48.91% # Class of executed instruction

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 5624de336fca2489b6d5e42576628e9e4dff297c..d04d5cf1bbc213c53b8f3fd081e82a3afabd130f 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -409,7 +409,7 @@ system.cpu.fetch.Insts                       88199449                       # Nu
 system.cpu.fetch.Branches                    17209876                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches            9548195                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                      59293355                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1322460                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                 1322461                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                 1971                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            42                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles         4935                       # Number of stall cycles due to full MSHR
@@ -677,7 +677,7 @@ system.cpu.commit.op_class_0::total          90688136                       # Cl
 system.cpu.commit.bw_lim_events               3803570                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    157213253                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195483387                       # The number of ROB writes
+system.cpu.rob.rob_writes                   195483388                       # The number of ROB writes
 system.cpu.timesIdled                           20301                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          345307                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
@@ -686,7 +686,7 @@ system.cpu.cpi                               0.919935                       # CP
 system.cpu.cpi_total                         0.919935                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.087033                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.087033                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102236516                       # number of integer regfile reads
+system.cpu.int_regfile_reads                102236524                       # number of integer regfile reads
 system.cpu.int_regfile_writes                56794814                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index b83d9722bde624257491485cb0a6662aa0ac5a93..b1db163929f30ee613d099801d628cb2c8d07482 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes            36877020                       # nu
 system.cpu.num_mem_refs                      43422001                       # number of memory refs
 system.cpu.num_load_insts                    22866262                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                   97920023                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               97920022.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          13741485                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                  47187956     52.03%     52.03% # Class of executed instruction

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 8fb00c46a51a5aed5a980142f5c6344dad1609e9..baa7e06318a1a7a2c7dd071e61fe6da56bbea95a 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes            36877020                       # nu
 system.cpu.num_mem_refs                      43422001                       # number of memory refs
 system.cpu.num_load_insts                    22866262                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  254587966                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               254587965.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          13741485                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                  47187956     52.03%     52.03% # Class of executed instruction

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 0f1a40d442f9af1ce13e60b6e25b98baa714786e..9acb631e887921f8727624f1bc9e9f98ce9db57e 100644 (file)
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes             1150968                       # nu
 system.cpu.num_mem_refs                      58160248                       # number of memory refs
 system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  136297345                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               136297344.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
 system.cpu.op_class::IntAlu                  66342070     48.68%     57.07% # Class of executed instruction

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 024e347b93ac5eb09105989478ff2fef11554361..3c1945f38a519fc8945e00f076ff469b77dee7d4 100644 (file)
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes             1150968                       # nu
 system.cpu.num_mem_refs                      58160248                       # number of memory refs
 system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  404484520                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               404484519.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
 system.cpu.op_class::IntAlu                  66342070     48.68%     57.07% # Class of executed instruction

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 20a214b430bd32e99b39a40c7134e37908379d89..dd7b09a8e31edaf82b7aaa75f6f107bdeee732b1 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -424,7 +424,7 @@ system.cpu.fetch.Insts                     2067206547                       # Nu
 system.cpu.fetch.Branches                   286237274                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches          166967181                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                    1477423210                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29286858                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                29286859                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   38                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.IcacheWaitRetryStallCycles          232                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                 656844028                       # Number of cache lines fetched
@@ -691,7 +691,7 @@ system.cpu.commit.op_class_0::total        1664032433                       # Cl
 system.cpu.commit.bw_lim_events              58313739                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   3330084063                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883248691                       # The number of ROB writes
+system.cpu.rob.rob_writes                  3883248692                       # The number of ROB writes
 system.cpu.timesIdled                             433                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           24299                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563023                       # Number of Instructions Simulated
@@ -700,7 +700,7 @@ system.cpu.cpi                               0.975038                       # CP
 system.cpu.cpi_total                         0.975038                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.025601                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.025601                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2176017050                       # number of integer regfile reads
+system.cpu.int_regfile_reads               2176017062                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1261587528                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       49                       # number of floating regfile writes

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index ca7d8e82bc02304883dab35126d83b1db144937f..fc3ec094ea5e65110cd807241ce0f5cad34d45cc 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes           518236214                       # nu
 system.cpu.num_mem_refs                     633153380                       # number of memory refs
 system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1664034981                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               1664034980.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         213462426                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                1030178775     61.91%     61.91% # Class of executed instruction

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 249435dd71604a5d07d58dc0b21bc8236b3c71fa..1aeb45981687d9d5d8103762044fde38c37c1a18 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes           518236214                       # nu
 system.cpu.num_mem_refs                     633153380                       # number of memory refs
 system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4727341996                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               4727341995.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         213462426                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                1030178775     61.91%     61.91% # Class of executed instruction

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 7956102ad0f0e419e28e556803f957d241dc0938..566338996af425b99591d217f076e0a2fc340edf 100644 (file)
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes          1355930461                       # nu
 system.cpu.num_mem_refs                    1677713084                       # number of memory refs
 system.cpu.num_load_insts                  1239184746                       # Number of load instructions
 system.cpu.num_store_insts                  438528338                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5692014456                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               5692014455.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         248500691                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               2494522      0.05%      0.05% # Class of executed instruction
 system.cpu.op_class::IntAlu                3006647871     64.15%     64.20% # Class of executed instruction

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index a2f8fddf2ffb0ca55997d7ef41c917f3ff9bbbc8..310a8da1fc780d615ce7e677bb95403654b84e3c 100644 (file)
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes          1355930461                       # nu
 system.cpu.num_mem_refs                    1677713084                       # number of memory refs
 system.cpu.num_load_insts                  1239184746                       # Number of load instructions
 system.cpu.num_store_insts                  438528338                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                11765161052                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               11765161051.998001                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         248500691                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               2494522      0.05%      0.05% # Class of executed instruction
 system.cpu.op_class::IntAlu                3006647871     64.15%     64.20% # Class of executed instruction
@@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Cl
 system.cpu.op_class::total                 4686862596                       # Class of executed instruction
 system.cpu.icache.tags.replacements                10                       # number of replacements
 system.cpu.icache.tags.tagsinuse           555.705054                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs          4013232208                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs          4013232207                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               675                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          5945529.197037                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          5945529.195556                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   555.705054                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.271340                       # Average percentage of cache occupancy
@@ -138,14 +138,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024          665
 system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.324707                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        8026466441                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       8026466441                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      4013232208                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    4013232208                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       4013232208                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   4013232208                       # number of overall hits
-system.cpu.icache.overall_hits::total      4013232208                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        8026466439                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       8026466439                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst   4013232207                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      4013232207                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    4013232207                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       4013232207                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   4013232207                       # number of overall hits
+system.cpu.icache.overall_hits::total      4013232207                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           675                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
@@ -158,12 +158,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     37156000
 system.cpu.icache.demand_miss_latency::total     37156000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     37156000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     37156000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   4013232883                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   4013232883                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   4013232883                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   4013232883                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   4013232883                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   4013232883                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   4013232882                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   4013232882                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   4013232882                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   4013232882                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   4013232882                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   4013232882                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 613bdf71b93ba8512e6e2920398863ea164acee0..eede9a19d5fcb04befe8cff1b393c8f20daf6173 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -375,7 +375,7 @@ system.cpu.fetch.Insts                      349266175                       # Nu
 system.cpu.fetch.Branches                    85925623                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           42726403                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     158254745                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12044332                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                12044333                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  129                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           37                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles          592                       # Number of stall cycles due to full MSHR
@@ -644,7 +644,7 @@ system.cpu.commit.op_class_0::total         181650341                       # Cl
 system.cpu.commit.bw_lim_events               3353878                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    406255589                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513821131                       # The number of ROB writes
+system.cpu.rob.rob_writes                   513821132                       # The number of ROB writes
 system.cpu.timesIdled                            2630                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           38922                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
@@ -653,7 +653,7 @@ system.cpu.cpi                               0.986122                       # CP
 system.cpu.cpi_total                         0.986122                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.014073                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.014073                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218958563                       # number of integer regfile reads
+system.cpu.int_regfile_reads                218958580                       # number of integer regfile reads
 system.cpu.int_regfile_writes               114511116                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   2904510                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                  2441819                       # number of floating regfile writes

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 472f06dc1d66f1ff0aa5c5162f622a7ea86c710c..b068c4279012f3302beacb03a10e2cfb7e47ee55 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes           190815535                       # nu
 system.cpu.num_mem_refs                      40540779                       # number of memory refs
 system.cpu.num_load_insts                    27896144                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  199192983                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               199192982.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 138988212     76.51%     76.51% # Class of executed instruction

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 085a5b238abb4004bd96707fe9920cf3f4f7ab49..394a8f6cf1ff2c4ea17044d89f7bedd9ff146aaf 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes           190815535                       # nu
 system.cpu.num_mem_refs                      40540779                       # number of memory refs
 system.cpu.num_load_insts                    27896144                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  460346714                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               460346713.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 138988212     76.51%     76.51% # Class of executed instruction

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 306fece1f0c3cf1dd90ae680fdbddfcf257297eb..aa452dcbd92dc69bfaa55e5416d0158f5c11596e 100644 (file)
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes             2974850                       # nu
 system.cpu.num_mem_refs                      76733958                       # number of memory refs
 system.cpu.num_load_insts                    57735091                       # Number of load instructions
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  193445891                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               193445890.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          15132745                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              13329871      6.89%      6.89% # Class of executed instruction
 system.cpu.op_class::IntAlu                 102506896     52.99%     59.88% # Class of executed instruction

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index a6897afb38c521d2af9b725985756a46d0538dd0..66a194e38f8212bfb81c5d22d5200c4a9b79dec8 100644 (file)
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes             2974850                       # nu
 system.cpu.num_mem_refs                      76733958                       # number of memory refs
 system.cpu.num_load_insts                    57735091                       # Number of load instructions
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  541126164                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               541126163.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          15132745                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              13329871      6.89%      6.89% # Class of executed instruction
 system.cpu.op_class::IntAlu                 102506896     52.99%     59.88% # Class of executed instruction

diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 55e2f8708c218ed6d7dd1ce643e1a1b5e59d05af..c2d74a54c9713269e24afdfc532ac0da48738349 100644 (file)
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -292,7 +292,7 @@ system.cpu.fetch.Insts                      249058784                       # Nu
 system.cpu.fetch.Branches                    22382097                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           14763235                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     267434691                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3695048                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                 3695049                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                         15                       # Number of cycles fetch has spent waiting for tlb
 system.cpu.fetch.MiscStallCycles                 4561                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles         42381                       # Number of stall cycles due to pending traps
@@ -499,11 +499,11 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts       119784082                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           1557714                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    280934179                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    280934178                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     0.787955                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     1.593006                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    181002456     64.43%     64.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    181002455     64.43%     64.43% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1     57799506     20.57%     85.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2     14236358      5.07%     90.07% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3     11930779      4.25%     94.32% # Number of insts commited each cycle
@@ -515,7 +515,7 @@ system.cpu.commit.committed_per_cycle::8      6891030      2.45%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    280934179                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    280934178                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -563,8 +563,8 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               6891030                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    615190615                       # The number of ROB reads
-system.cpu.rob.rob_writes                   698614568                       # The number of ROB writes
+system.cpu.rob.rob_reads                    615190614                       # The number of ROB reads
+system.cpu.rob.rob_writes                   698614569                       # The number of ROB writes
 system.cpu.timesIdled                            3122                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          178726                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
@@ -573,7 +573,7 @@ system.cpu.cpi                               2.251725                       # CP
 system.cpu.cpi_total                         2.251725                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.444104                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.444104                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                456361988                       # number of integer regfile reads
+system.cpu.int_regfile_reads                456362005                       # number of integer regfile reads
 system.cpu.int_regfile_writes               239113538                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   3275482                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                  2058196                       # number of floating regfile writes

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 7d0cfab72bf03826f0e988cff91427239fabe6a4..7b91ddd8b6d3bc0c2aff953457f50310b4633eea 100644 (file)
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes            56242058                       # nu
 system.cpu.num_mem_refs                      77165304                       # number of memory refs
 system.cpu.num_load_insts                    56649587                       # Number of load instructions
 system.cpu.num_store_insts                   20515717                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  262786559                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               262786558.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          12326938                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               1176721      0.53%      0.53% # Class of executed instruction
 system.cpu.op_class::IntAlu                 134111833     60.58%     61.12% # Class of executed instruction

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 79eb88ee578b955a23b8865a6cd0a247db65e5b6..d20d5099368086751af3a822730f120f51391a12 100644 (file)
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -77,10 +77,10 @@ system.cpu.num_cc_register_writes            56242058                       # nu
 system.cpu.num_mem_refs                      77165304                       # number of memory refs
 system.cpu.num_load_insts                    56649587                       # Number of load instructions
 system.cpu.num_store_insts                   20515717                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  501907914                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               501907913.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          12326938                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               1176721      0.53%      0.53% # Class of executed instruction
 system.cpu.op_class::IntAlu                 134111833     60.58%     61.12% # Class of executed instruction
@@ -119,9 +119,9 @@ system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Cl
 system.cpu.op_class::total                  221363385                       # Class of executed instruction
 system.cpu.icache.tags.replacements              2836                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1455.296642                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           173489674                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs           173489673                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              4694                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          36959.879421                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          36959.879207                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst  1455.296642                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.710594                       # Average percentage of cache occupancy
@@ -133,14 +133,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          498
 system.cpu.icache.tags.age_task_id_blocks_1024::3          394                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          869                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.907227                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         346993430                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        346993430                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    173489674                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       173489674                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     173489674                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        173489674                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    173489674                       # number of overall hits
-system.cpu.icache.overall_hits::total       173489674                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         346993428                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        346993428                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    173489673                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       173489673                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     173489673                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        173489673                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    173489673                       # number of overall hits
+system.cpu.icache.overall_hits::total       173489673                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         4694                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          4694                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         4694                       # number of demand (read+write) misses
@@ -153,12 +153,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst    180319000
 system.cpu.icache.demand_miss_latency::total    180319000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst    180319000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total    180319000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    173494368                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    173494368                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    173494368                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    173494368                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    173494368                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    173494368                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    173494367                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    173494367                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    173494367                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    173494367                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    173494367                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    173494367                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000027                       # miss rate for demand accesses

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index d8727c54418576c610825d367b9664a2032b5437..c9776266fc2f2bae8f6a23c51e603e644e01400c 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -599,7 +599,7 @@ system.cpu.cpi                               6.446328                       # CP
 system.cpu.cpi_total                         6.446328                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.155127                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.155127                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12991                       # number of integer regfile reads
+system.cpu.int_regfile_reads                    12992                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7455                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes

diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 54adfc503741a8601bcc9aea871f10339fef5d42..d08d4e917ab11b737db1d73932a5d96007a8c28f 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -371,9 +371,9 @@ system.cpu.tickCycles                           10521                       # Nu
 system.cpu.idleCycles                           45301                       # Total number of cycles that the object has spent stopped
 system.cpu.icache.tags.replacements                 3                       # number of replacements
 system.cpu.icache.tags.tagsinuse           162.201432                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1919                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs                1918                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               321                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.978193                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.975078                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   162.201432                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.079200                       # Average percentage of cache occupancy
@@ -382,14 +382,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024          318
 system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.155273                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4801                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4801                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1919                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1919                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1919                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1919                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1919                       # number of overall hits
-system.cpu.icache.overall_hits::total            1919                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              4799                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4799                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1918                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1918                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1918                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1918                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1918                       # number of overall hits
+system.cpu.icache.overall_hits::total            1918                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          321                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           321                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          321                       # number of demand (read+write) misses
@@ -402,18 +402,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     21503250
 system.cpu.icache.demand_miss_latency::total     21503250                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     21503250                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     21503250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2240                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2240                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2240                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2240                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143304                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.143304                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.143304                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.143304                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.143304                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.143304                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         2239                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2239                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2239                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2239                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2239                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2239                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143368                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.143368                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.143368                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.143368                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.143368                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.143368                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757                       # average overall miss latency
@@ -440,12 +440,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20730750
 system.cpu.icache.demand_mshr_miss_latency::total     20730750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20730750                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     20730750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143304                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143304                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143304                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.143304                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143304                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.143304                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143368                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143368                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143368                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.143368                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143368                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.143368                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701                       # average overall mshr miss latency

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 092386ab8a890e341a6966d71421d0c718c604e4..62f6dcd2bfcc64cf21b422f9ec67f8db965c0ea3 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -457,7 +457,7 @@ system.cpu.fetch.Insts                          12484                       # Nu
 system.cpu.fetch.Branches                        2638                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               1137                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          4850                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1010                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                    1011                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           259                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
@@ -728,7 +728,7 @@ system.cpu.commit.op_class_0::total              5377                       # Cl
 system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        22692                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21719                       # The number of ROB writes
+system.cpu.rob.rob_writes                       21720                       # The number of ROB writes
 system.cpu.timesIdled                             209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           19014                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
@@ -737,7 +737,7 @@ system.cpu.cpi                               7.067523                       # CP
 system.cpu.cpi_total                         7.067523                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.141492                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.141492                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     7944                       # number of integer regfile reads
+system.cpu.int_regfile_reads                     7945                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    4420                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        31                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                     28734                       # number of cc regfile reads

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index ce3916e9316e9ff5548d8f8e9d1470b537246cff..6fc5d6de3f06fc00d5c45e52584ff8cf678a7124 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -375,7 +375,7 @@ system.cpu.fetch.Insts                          12370                       # Nu
 system.cpu.fetch.Branches                        2560                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                794                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                         11397                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1062                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                    1063                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   19                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           322                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           84                       # Number of stall cycles due to full MSHR
@@ -643,7 +643,7 @@ system.cpu.commit.op_class_0::total              5377                       # Cl
 system.cpu.commit.bw_lim_events                    52                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        24066                       # The number of ROB reads
-system.cpu.rob.rob_writes                       16749                       # The number of ROB writes
+system.cpu.rob.rob_writes                       16750                       # The number of ROB writes
 system.cpu.timesIdled                             138                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                            6973                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
@@ -652,7 +652,7 @@ system.cpu.cpi                               5.166630                       # CP
 system.cpu.cpi_total                         5.166630                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.193550                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.193550                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     6786                       # number of integer regfile reads
+system.cpu.int_regfile_reads                     6787                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    3839                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                     24301                       # number of cc regfile reads

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 9b7b2bcb643f7dcc2df01c2c74ff30a7c7f14614..3983747233e474658184b38a4c7de38e9c9879f7 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -256,10 +256,10 @@ system.cpu.num_cc_register_writes                2432                       # nu
 system.cpu.num_mem_refs                          1965                       # number of memory refs
 system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5390                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles                5389.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 73cde8525741667512bc490b41f236f80b1fe089..d2d36b7228e3a9da373e2d3d13639ebf07e1593a 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -169,10 +169,10 @@ system.cpu.num_cc_register_writes                2432                       # nu
 system.cpu.num_mem_refs                          1965                       # number of memory refs
 system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5390                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles                5389.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 8f2c9257fc538f298fa44314d6746cb41afc8881..83a7fcb5fcb38928a21163ced29c5b16f52f6a71 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes                2432                       # nu
 system.cpu.num_mem_refs                          1965                       # number of memory refs
 system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      51630                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               51629.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index beeb90a4c7fba63c8b3e134fb260efb5be027517..1593f969f26e8f03e527775d685afabecc07c383 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,55 +1,55 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    24907000                       # Number of ticks simulated
-final_tick                                   24907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000024                       # Number of seconds simulated
+sim_ticks                                    24417000                       # Number of ticks simulated
+final_tick                                   24417000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46022                       # Simulator instruction rate (inst/s)
-host_op_rate                                    46018                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              197122402                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234444                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-sim_insts                                        5814                       # Number of instructions simulated
-sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  26948                       # Simulator instruction rate (inst/s)
+host_op_rate                                    26945                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              116974890                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277212                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+sim_insts                                        5624                       # Number of instructions simulated
+sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                29120                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        20288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           20288                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            814550126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            354599109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1169149235                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       814550126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          814550126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           814550126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           354599109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1169149235                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           455                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8768                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28800                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        20032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           20032                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                137                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   450                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            820412008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            359094074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1179506082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       820412008                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          820412008                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           820412008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           359094074                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1179506082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           450                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         455                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         450                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    29120                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    28800                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     29120                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     28800                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  28                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  27                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                   8                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                   3                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  12                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  51                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  59                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  56                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  75                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 36                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 19                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24826000                       # Total gap between requests
+system.physmem.totGap                        24336000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     455                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     450                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       303                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       299                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       121                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        23                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
@@ -186,97 +186,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          106                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      268.075472                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.680617                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     244.800860                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             25     23.58%     23.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           40     37.74%     61.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           14     13.21%     74.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           10      9.43%     83.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            7      6.60%     90.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      1.89%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      2.83%     95.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      4.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            106                       # Bytes accessed per row activation
-system.physmem.totQLat                        4936500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13467750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2275000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10849.45                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          103                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      276.504854                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     191.986288                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.190297                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             25     24.27%     24.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           37     35.92%     60.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           14     13.59%     73.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      7.77%     81.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            8      7.77%     89.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      1.94%     91.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      2.91%     94.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      0.97%     95.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      4.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            103                       # Bytes accessed per row activation
+system.physmem.totQLat                        4914500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13352000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2250000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10921.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29599.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1169.15                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29671.11                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1179.51                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1169.15                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1179.51                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.13                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.21                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.21                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.51                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.52                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        344                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.60                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54562.64                       # Average gap between requests
-system.physmem.pageHitRate                      75.60                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        54080.00                       # Average gap between requests
+system.physmem.pageHitRate                      76.44                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            780000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          22841500                       # Time in different power states
+system.physmem.memoryStateTime::ACT          22851000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    196560                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::0                    181440                       # Energy for activate commands per rank (pJ)
 system.physmem.actEnergy::1                    582120                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    107250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::0                     99000                       # Energy for precharge commands per rank (pJ)
 system.physmem.preEnergy::1                    317625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                   756600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  2644200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::0                   772200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                  2652000                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
 system.physmem.refreshEnergy::0               1525680                       # Energy for refresh commands per rank (pJ)
 system.physmem.refreshEnergy::1               1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              14747040                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              16041510                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::0              14753880                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1              16048350                       # Energy for active background per rank (pJ)
 system.physmem.preBackEnergy::0               1235250                       # Energy for precharge background per rank (pJ)
 system.physmem.preBackEnergy::1                 99750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                18568380                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                21210885                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             786.171156                       # Core power per rank (mW)
-system.physmem.averagePower::1             898.052818                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 404                       # Transaction distribution
-system.membus.trans_dist::ReadResp                404                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               51                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        29120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   29120                       # Cumulative packet size per connected master and slave (bytes)
+system.physmem.totalEnergy::0                18567450                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1                21225525                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             785.799080                       # Core power per rank (mW)
+system.physmem.averagePower::1             898.292335                       # Core power per rank (mW)
+system.membus.trans_dist::ReadReq                 400                       # Transaction distribution
+system.membus.trans_dist::ReadResp                400                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   28800                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               455                       # Request fanout histogram
+system.membus.snoop_fanout::samples               450                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     455    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     450    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 455                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              552000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 450                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              545500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4259500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             17.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4210750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             17.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    1156                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               861                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               603                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  879                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     339                       # Number of BTB hits
+system.cpu.branchPred.lookups                    1124                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               833                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               586                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  850                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     329                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             38.566553                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                      86                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 32                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             38.705882                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                      84                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 31                       # Number of incorrect RAS predictions.
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -295,118 +296,118 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            49815                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                    7                       # Number of system calls
+system.cpu.numCycles                            48835                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken          432                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken          724                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5088                       # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites         3396                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         8484                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.branch_predictor.predictedTaken          421                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken          703                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         4929                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites         3280                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         8209                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           1328                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       2229                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect          274                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect          320                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted            594                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted               321                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     64.918033                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions             3133                       # Number of Instructions Executed.
-system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
+system.cpu.regfile_manager.regForwards           1292                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       2173                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect          263                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect          315                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted            578                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted               305                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     65.458664                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions             3019                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies                 2                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9484                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9295                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             462                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           44434                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             5381                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         10.801967                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              1163                       # Number of Load instructions committed
-system.cpu.comStores                              925                       # Number of Store instructions committed
-system.cpu.comBranches                            915                       # Number of Branches instructions committed
-system.cpu.comNops                                657                       # Number of Nop instructions committed
-system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               2144                       # Number of Integer instructions committed
+system.cpu.timesIdled                             454                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           43587                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             5248                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         10.746391                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              1132                       # Number of Load instructions committed
+system.cpu.comStores                              901                       # Number of Store instructions committed
+system.cpu.comBranches                            883                       # Number of Branches instructions committed
+system.cpu.comNops                                637                       # Number of Nop instructions committed
+system.cpu.comNonSpec                               9                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                               2062                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5814                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          5814                       # Number of Ops committed (Per-Thread)
+system.cpu.committedInsts                        5624                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5624                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  5814                       # Number of Instructions committed (Total)
-system.cpu.cpi                               8.568111                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.committedInsts_total                  5624                       # Number of Instructions committed (Total)
+system.cpu.cpi                               8.683321                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         8.568111                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.116712                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         8.683321                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.115163                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.116712                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    46168                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      3647                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                7.321088                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    47003                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      2812                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                5.644886                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    47048                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      2767                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                5.554552                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    48577                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      1238                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.485195                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    46929                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      2886                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                5.793436                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.115163                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    45291                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      3544                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization                7.257090                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    46099                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      2736                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                5.602539                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    46145                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      2690                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                5.508344                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    47641                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1194                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                2.444968                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    46041                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      2794                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                5.721306                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                13                       # number of replacements
-system.cpu.icache.tags.tagsinuse           150.581339                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 428                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               319                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              1.341693                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           147.900639                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 418                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               315                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              1.326984                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   150.581339                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.073526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.073526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          306                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.149414                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              1875                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             1875                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          428                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             428                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           428                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              428                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          428                       # number of overall hits
-system.cpu.icache.overall_hits::total             428                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          350                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           350                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          350                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
-system.cpu.icache.overall_misses::total           350                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25285250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25285250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25285250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25285250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25285250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25285250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          778                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          778                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          778                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          778                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          778                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          778                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.449871                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.449871                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.449871                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.449871                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.449871                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.449871                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72243.571429                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72243.571429                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72243.571429                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72243.571429                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72243.571429                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72243.571429                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst   147.900639                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.072217                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.072217                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.147461                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              1839                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             1839                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst          418                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             418                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           418                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              418                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          418                       # number of overall hits
+system.cpu.icache.overall_hits::total             418                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           344                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            344                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          344                       # number of overall misses
+system.cpu.icache.overall_misses::total           344                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25151000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25151000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25151000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25151000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25151000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25151000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          762                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          762                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          762                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          762                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          762                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          762                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.451444                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.451444                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.451444                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.451444                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.451444                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.451444                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73113.372093                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73113.372093                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -415,143 +416,143 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           31                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           31                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           31                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           31                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           31                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           31                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          319                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          319                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          319                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22950250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22950250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22950250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22950250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22950250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22950250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.410026                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.410026                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.410026                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71944.357367                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71944.357367                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71944.357367                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71944.357367                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71944.357367                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71944.357367                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           29                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           29                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           29                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           29                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          315                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          315                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22975000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22975000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22975000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22975000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22975000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22975000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.413386                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.413386                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.413386                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           406                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           51                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          638                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               914                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              29248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq            402                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           402                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          630                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          274                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               904                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              28928                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          457                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          452                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                457    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                452    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            457                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         228500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            452                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         226000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        538750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        532000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        226250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        224750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          208.342392                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          204.797884                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              404                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.004950                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              400                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.005000                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.263135                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    56.079256                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004647                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001711                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006358                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012329                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4111                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4111                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   149.365797                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    55.432088                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004558                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001692                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006250                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012207                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4066                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4066                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          317                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          313                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          404                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          317                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           455                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22604750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6885000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     29489750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3812750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3812750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22604750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10697750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     33302500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22604750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10697750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     33302500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22634000                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          319                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          457                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          319                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993730                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_accesses::total          402                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993651                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.995074                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.995025                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993730                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993651                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995624                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995575                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993651                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71308.359621                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79137.931034                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72994.430693                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74759.803922                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74759.803922                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71308.359621                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77519.927536                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73192.307692                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71308.359621                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77519.927536                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73192.307692                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.995575                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        74470                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        74470                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -560,114 +561,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          317                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          404                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          317                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          455                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18622750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5806500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24429250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3169250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3169250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18622750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8975750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27598500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18622750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8975750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27598500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::total          400                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          450                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          450                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18704000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5530750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24234750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3093000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3093000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18704000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8623750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     27327750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18704000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8623750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27327750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995575                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58746.845426                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66741.379310                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60468.440594                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62142.156863                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62142.156863                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58746.845426                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65041.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.043956                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58746.845426                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65041.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60656.043956                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995575                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        61860                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        61860                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            90.295130                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1638                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.869565                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            89.129655                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1596                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.649635                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    90.295130                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022045                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022045                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    89.129655                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021760                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021760                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4314                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4314                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1066                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1066                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          572                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            572                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1638                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1638                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1638                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1638                       # number of overall hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033447                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4203                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4203                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1035                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1035                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          561                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            561                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1596                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1596                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1596                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1596                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          353                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          353                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          450                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            450                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          450                       # number of overall misses
-system.cpu.dcache.overall_misses::total           450                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7642750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7642750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     21639750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     21639750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29282500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29282500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29282500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29282500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083405                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.083405                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.381622                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.381622                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.215517                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.215517                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.215517                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.215517                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78791.237113                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 78791.237113                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61302.407932                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61302.407932                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65072.222222                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65072.222222                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65072.222222                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65072.222222                       # average overall miss latency
+system.cpu.dcache.WriteReq_misses::cpu.data          340                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          340                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          437                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            437                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          437                       # number of overall misses
+system.cpu.dcache.overall_misses::total           437                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7368000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7368000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20584000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20584000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     27952000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     27952000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     27952000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     27952000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2033                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2033                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2033                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2033                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085689                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.085689                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.377358                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.377358                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.214953                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.214953                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.214953                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.214953                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63963.386728                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63963.386728                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
@@ -678,44 +679,44 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          302                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          302                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          312                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          312                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          312                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          312                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          290                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          290                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          300                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          300                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          300                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          300                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6978500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6978500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3866750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3866750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10845250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10845250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10845250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10845250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80212.643678                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80212.643678                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75818.627451                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75818.627451                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78588.768116                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78588.768116                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78588.768116                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78588.768116                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6703250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6703250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3776500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3776500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10479750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10479750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10479750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10479750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076855                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076855                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.067388                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.067388                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        75530                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        75530                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 83678472abbc1e6d2474501b63386b0a747d9bff..61d4efb5af16345ba09a56567edba8b4fcd92730 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,56 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21611500                       # Number of ticks simulated
-final_tick                                   21611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000021                       # Number of seconds simulated
+sim_ticks                                    21163500                       # Number of ticks simulated
+final_tick                                   21163500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52948                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52941                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              221880610                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236528                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-sim_insts                                        5156                       # Number of instructions simulated
-sim_ops                                          5156                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  24711                       # Simulator instruction rate (inst/s)
+host_op_rate                                    24708                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              104867636                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278232                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+sim_insts                                        4986                       # Number of instructions simulated
+sim_ops                                          4986                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             21568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9088                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30656                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21568                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21568                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                337                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   479                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            997987183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            420516854                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1418504037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       997987183                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          997987183                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           997987183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           420516854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1418504037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           479                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             21120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                30144                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21120                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                330                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   471                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            997944574                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            426394500                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1424339074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       997944574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          997944574                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           997944574                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           426394500                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1424339074                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           471                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         479                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         471                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    30656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    30144                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     30656                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     30144                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  30                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  29                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                   1                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                   7                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                   3                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  13                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  54                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  64                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  77                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  53                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  59                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  76                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 43                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 20                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 51                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21538500                       # Total gap between requests
+system.physmem.totGap                        21083000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     479                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     471                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        42                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       277                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       134                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        39                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,41 +186,42 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          109                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      255.412844                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.780194                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     251.892291                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             32     29.36%     29.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           38     34.86%     64.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           15     13.76%     77.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           11     10.09%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      2.75%     90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      2.75%     93.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      1.83%     95.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      4.59%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            109                       # Bytes accessed per row activation
-system.physmem.totQLat                        5601000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  14582250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2395000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11693.11                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          105                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      262.095238                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.705030                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     253.763121                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             30     28.57%     28.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           34     32.38%     60.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           17     16.19%     77.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           10      9.52%     86.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      3.81%     90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      0.95%     91.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      1.90%     93.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      1.90%     95.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      4.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            105                       # Bytes accessed per row activation
+system.physmem.totQLat                        5392000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  14223250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2355000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11447.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30443.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1418.50                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30197.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1424.34                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1418.50                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1424.34                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.08                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.08                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.75                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        360                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        356                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.16                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   75.58                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        44965.55                       # Average gap between requests
-system.physmem.pageHitRate                      75.16                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        44762.21                       # Average gap between requests
+system.physmem.pageHitRate                      75.58                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
@@ -244,39 +245,39 @@ system.physmem.totalEnergy::0                12518970                       # To
 system.physmem.totalEnergy::1                14949930                       # Total energy per rank (pJ)
 system.physmem.averagePower::0             790.713406                       # Core power per rank (mW)
 system.physmem.averagePower::1             944.255803                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 428                       # Transaction distribution
-system.membus.trans_dist::ReadResp                428                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               51                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          958                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    958                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   30656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq                 421                       # Transaction distribution
+system.membus.trans_dist::ReadResp                421                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   30144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               479                       # Request fanout histogram
+system.membus.snoop_fanout::samples               471                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     479    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     471    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 479                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              605500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 471                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              594000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4492250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             20.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4415500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             20.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2196                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1454                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               435                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1700                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     564                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2146                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1406                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               427                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1636                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     528                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             33.176471                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     277                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 69                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             32.273839                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     284                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 68                       # Number of incorrect RAS predictions.
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -295,495 +296,495 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            43224                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                    7                       # Number of system calls
+system.cpu.numCycles                            42328                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               9138                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13312                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2196                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                841                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4920                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     886                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               8967                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13064                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2146                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                812                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4771                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     872                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.PendingTrapStallCycles           202                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2068                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   269                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.905393                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.198604                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2037                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   262                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14376                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.908737                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.207470                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11282     76.73%     76.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1513     10.29%     87.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      130      0.88%     87.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      159      1.08%     88.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      291      1.98%     90.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       99      0.67%     91.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      152      1.03%     92.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      125      0.85%     93.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      952      6.47%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11035     76.76%     76.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1473     10.25%     87.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      126      0.88%     87.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      160      1.11%     89.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      283      1.97%     90.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       90      0.63%     91.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      137      0.95%     92.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      121      0.84%     93.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      951      6.62%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.050805                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.307977                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8679                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2634                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2860                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   130                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    400                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  179                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    47                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12297                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   180                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    400                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8850                       # Number of cycles rename is idle
+system.cpu.fetch.rateDist::total                14376                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.050699                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.308637                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8549                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2515                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2791                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   126                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    395                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  174                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    43                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12032                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   172                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    395                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8711                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     502                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            975                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2807                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1169                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11801                       # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles            944                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2743                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1081                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11544                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    281                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.LQFullEvents                    196                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                    868                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                7107                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13927                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13678                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                6963                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13597                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13345                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 3                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  3398                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3709                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 16                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       307                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2543                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1213                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.CommittedMaps                  3282                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     3681                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 13                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts              9                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       298                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2503                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1169                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       9299                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  12                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8548                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                29                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3486                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1874                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                       9029                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8280                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                31                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3419                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1838                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14703                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.581378                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.331585                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14376                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.575960                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.325471                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11282     76.73%     76.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1346      9.15%     85.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 761      5.18%     91.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 427      2.90%     93.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 364      2.48%     96.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 316      2.15%     98.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 114      0.78%     99.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  65      0.44%     99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  28      0.19%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11054     76.89%     76.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1314      9.14%     86.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 739      5.14%     91.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 413      2.87%     94.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 345      2.40%     96.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 315      2.19%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 104      0.72%     99.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  66      0.46%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  26      0.18%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14376                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       8      3.96%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    135     66.83%     70.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    59     29.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       8      4.06%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    131     66.50%     70.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    58     29.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5034     58.89%     58.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.06%     58.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2396     28.03%     87.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1109     12.97%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4865     58.76%     58.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2336     28.21%     87.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1072     12.95%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8548                       # Type of FU issued
-system.cpu.iq.rate                           0.197761                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         202                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023631                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              32026                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             12803                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7708                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8280                       # Type of FU issued
+system.cpu.iq.rate                           0.195615                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         197                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023792                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31160                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             12466                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7466                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8748                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8475                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               86                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               82                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1380                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1371                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          288                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          268                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    400                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     479                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     9                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10879                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               152                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2543                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1213                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 12                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles                    395                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     475                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    11                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10593                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               153                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2503                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1169                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 11                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    13                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            105                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          359                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  464                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8213                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2257                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               335                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             98                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          354                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  452                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7957                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2194                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               323                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1568                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3348                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1425                       # Number of branches executed
-system.cpu.iew.exec_stores                       1091                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.190010                       # Inst execution rate
-system.cpu.iew.wb_sent                           7817                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7710                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2989                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4523                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1553                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3252                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1379                       # Number of branches executed
+system.cpu.iew.exec_stores                       1058                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.187984                       # Inst execution rate
+system.cpu.iew.wb_sent                           7571                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7468                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2915                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      4399                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.178373                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660845                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.176432                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.662651                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            5063                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               392                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13824                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.420501                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.238844                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts            4969                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls               9                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts               386                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13506                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.416333                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.231872                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11590     83.84%     83.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          886      6.41%     90.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          537      3.88%     94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          260      1.88%     96.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          148      1.07%     97.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          189      1.37%     98.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           68      0.49%     98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           40      0.29%     99.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          106      0.77%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11333     83.91%     83.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          875      6.48%     90.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          515      3.81%     94.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          250      1.85%     96.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          149      1.10%     97.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          177      1.31%     98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           64      0.47%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.30%     99.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          102      0.76%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13824                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                 5813                       # Number of instructions committed
-system.cpu.commit.committedOps                   5813                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        13506                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts                 5623                       # Number of instructions committed
+system.cpu.commit.committedOps                   5623                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2088                       # Number of memory references committed
-system.cpu.commit.loads                          1163                       # Number of loads committed
+system.cpu.commit.refs                           2033                       # Number of memory references committed
+system.cpu.commit.loads                          1132                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                        915                       # Number of branches committed
+system.cpu.commit.branches                        883                       # Number of branches committed
 system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      5111                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                   87                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass          657     11.30%     11.30% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu             3062     52.68%     63.98% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult               3      0.05%     64.03% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                1      0.02%     64.05% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              2      0.03%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.08% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead            1163     20.01%     84.09% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite            925     15.91%    100.00% # Class of committed instruction
+system.cpu.commit.int_insts                      4942                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                   85                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass          637     11.33%     11.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             2949     52.45%     63.77% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               2      0.04%     63.81% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     63.81% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              2      0.04%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1132     20.13%     83.98% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            901     16.02%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total              5813                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total              5623                       # Class of committed instruction
+system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        24581                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22642                       # The number of ROB writes
-system.cpu.timesIdled                             280                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           28521                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        5156                       # Number of Instructions Simulated
-system.cpu.committedOps                          5156                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               8.383243                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         8.383243                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.119286                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.119286                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    11114                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5412                       # number of integer regfile writes
+system.cpu.rob.rob_reads                        23983                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22065                       # The number of ROB writes
+system.cpu.timesIdled                             275                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           27952                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                        4986                       # Number of Instructions Simulated
+system.cpu.committedOps                          4986                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               8.489370                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.489370                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.117794                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.117794                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10767                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5247                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                     164                       # number of misc regfile reads
-system.cpu.toL2Bus.trans_dist::ReadReq            431                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           431                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           51                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          680                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          284                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               964                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              30848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq            424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          666                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30336                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          482                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          474                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                482    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                474    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            482                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         241000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            474                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         237000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        575000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        562000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        228250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        227000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.371303                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1615                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               340                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.750000                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           158.344728                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1593                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               333                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.783784                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.371303                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078795                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078795                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          323                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.157715                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4476                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4476                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1615                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1615                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1615                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1615                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1615                       # number of overall hits
-system.cpu.icache.overall_hits::total            1615                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          453                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           453                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          453                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            453                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          453                       # number of overall misses
-system.cpu.icache.overall_misses::total           453                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31446500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31446500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31446500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31446500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31446500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31446500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2068                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2068                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2068                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2068                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2068                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2068                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.219052                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.219052                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.219052                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.219052                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.219052                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.219052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69418.322296                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69418.322296                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   158.344728                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077317                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077317                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          316                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          165                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.154297                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4407                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4407                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1593                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1593                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1593                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1593                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1593                       # number of overall hits
+system.cpu.icache.overall_hits::total            1593                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          444                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           444                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          444                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            444                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          444                       # number of overall misses
+system.cpu.icache.overall_misses::total           444                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30764750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30764750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30764750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     30764750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30764750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     30764750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2037                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2037                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2037                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2037                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2037                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2037                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.217968                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.217968                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.217968                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.217968                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.217968                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.217968                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69289.977477                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69289.977477                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           48                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          113                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          113                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          113                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          113                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          113                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          340                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          340                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          340                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          340                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          340                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          340                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24622500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24622500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24622500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24622500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24622500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24622500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.164410                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.164410                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.164410                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.164410                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.164410                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.164410                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          111                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          111                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          111                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          111                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          111                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          111                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          333                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          333                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          333                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          333                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          333                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          333                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24043500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24043500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24043500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24043500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24043500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24043500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.163476                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.163476                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.163476                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.163476                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.163476                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.163476                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          222.296900                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          218.292920                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              428                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.007009                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              421                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.007126                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.611488                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    58.685412                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004993                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001791                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006784                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          428                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013062                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4335                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4335                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.335208                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.957712                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004893                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006662                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012848                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4263                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4263                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          337                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          330                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          428                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          337                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           479                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          337                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          479                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24252500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7286250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     31538750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4056000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4056000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     24252500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11342250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     35594750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     24252500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11342250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     35594750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          340                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_misses::total          421                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23680500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7216500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     30897000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3981500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.data     11198000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     34878500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23680500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11198000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     34878500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          333                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           91                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          431                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          340                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          142                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          482                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          340                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          482                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991176                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.demand_accesses::total          474                       # number of demand (read+write) accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.990991                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.993039                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.992925                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991176                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.990991                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.993776                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991176                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.993671                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990991                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.993776                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        79875                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        79875                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.993671                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        79630                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        79630                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -792,114 +793,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          330                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          479                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          479                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19997500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6166250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     26163750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3421500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3421500                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9587750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     29585250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19997500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9587750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     29585250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991176                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6096000                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9455000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993039                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.992925                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991176                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.993776                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991176                       # mshr miss rate for overall accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.993776                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        67180                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        67180                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            92.429669                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2508                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             17.661972                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            91.168146                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2445                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.340426                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    92.429669                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022566                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022566                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.034668                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              6220                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             6220                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1945                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1945                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          563                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            563                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2508                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2508                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2508                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2508                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          169                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           169                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          362                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          362                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          531                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            531                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          531                       # number of overall misses
-system.cpu.dcache.overall_misses::total           531                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11707000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11707000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     23264249                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     23264249                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     34971249                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     34971249                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     34971249                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     34971249                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2114                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2114                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         3039                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         3039                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         3039                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         3039                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079943                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.079943                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.391351                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.391351                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.174729                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.174729                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.174729                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.174729                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65859.225989                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65859.225989                       # average overall miss latency
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.168146                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022258                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022258                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              6061                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             6061                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1893                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1893                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          552                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            552                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2445                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2445                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2445                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2445                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          166                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           166                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          349                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          349                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          515                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            515                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          515                       # number of overall misses
+system.cpu.dcache.overall_misses::total           515                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11320500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11320500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22383749                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22383749                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33704249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33704249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33704249                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33704249                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2059                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2059                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2960                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2960                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2960                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2960                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080622                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.080622                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.387347                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.387347                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.173986                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.173986                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.173986                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.173986                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65445.143689                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65445.143689                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          573                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
@@ -908,46 +909,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.090909
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          311                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          311                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          389                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          389                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          389                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          389                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           75                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          299                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          299                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7380750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7380750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4107999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4107999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11488749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11488749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11488749                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11488749                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.043046                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.043046                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.046726                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.046726                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.046726                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.046726                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        80549                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        80549                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4032499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4032499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11343499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11343499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11343499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11343499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044196                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044196                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.047635                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.047635                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.047635                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.047635                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 49c05c732df2c98cf1695d7853c1b2db862d634b..87429446a3783949b96b84b9f55b21d14a34bd48 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2907000                       # Number of ticks simulated
-final_tick                                    2907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     2812000                       # Number of ticks simulated
+final_tick                                    2812000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 972729                       # Simulator instruction rate (inst/s)
-host_op_rate                                   970456                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              484177215                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275596                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        5814                       # Number of instructions simulated
-sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  65844                       # Simulator instruction rate (inst/s)
+host_op_rate                                    65830                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               32908431                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267356                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+sim_insts                                        5624                       # Number of instructions simulated
+sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             23260                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              4374                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                27634                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23260                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23260                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data           3658                       # Number of bytes written to this memory
-system.physmem.bytes_written::total              3658                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5815                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1163                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  6978                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data               925                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  925                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           8001375989                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1504643963                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9506019952                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      8001375989                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         8001375989                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1258341933                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1258341933                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          8001375989                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2762985896                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10764361885                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                6978                       # Transaction distribution
-system.membus.trans_dist::ReadResp               6978                       # Transaction distribution
-system.membus.trans_dist::WriteReq                925                       # Transaction distribution
-system.membus.trans_dist::WriteResp               925                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port        11630                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         4176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15806                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        23260                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   31292                       # Cumulative packet size per connected master and slave (bytes)
+system.physmem.bytes_read::cpu.inst             22500                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4289                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26789                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        22500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           22500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           3601                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              3601                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5625                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1132                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6757                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               901                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  901                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           8001422475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1525248933                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9526671408                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      8001422475                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         8001422475                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1280583215                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1280583215                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          8001422475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2805832148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10807254623                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq                6757                       # Transaction distribution
+system.membus.trans_dist::ReadResp               6757                       # Transaction distribution
+system.membus.trans_dist::WriteReq                901                       # Transaction distribution
+system.membus.trans_dist::WriteResp               901                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port        11250                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         4066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15316                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        22500                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         7890                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   30390                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7903                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.735797                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.440936                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7658                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.734526                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.441614                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    2088     26.42%     26.42% # Request fanout histogram
-system.membus.snoop_fanout::1                    5815     73.58%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    2033     26.55%     26.55% # Request fanout histogram
+system.membus.snoop_fanout::1                    5625     73.45%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total                7903                       # Request fanout histogram
+system.membus.snoop_fanout::total                7658                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -75,64 +75,64 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                             5815                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                    7                       # Number of system calls
+system.cpu.numCycles                             5625                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5814                       # Number of instructions committed
-system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
+system.cpu.committedInsts                        5624                       # Number of instructions committed
+system.cpu.committedOps                          5624                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4944                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
-system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5113                       # number of integer instructions
+system.cpu.num_func_calls                         190                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          649                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4944                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7054                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3281                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2089                       # number of memory refs
-system.cpu.num_load_insts                        1163                       # Number of load instructions
-system.cpu.num_store_insts                        926                       # Number of store instructions
+system.cpu.num_mem_refs                          2034                       # number of memory refs
+system.cpu.num_load_insts                        1132                       # Number of load instructions
+system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5815                       # Number of busy cycles
+system.cpu.num_busy_cycles                       5625                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                               915                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                   657     11.30%     11.30% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3063     52.67%     63.97% # Class of executed instruction
-system.cpu.op_class::IntMult                        3      0.05%     64.02% # Class of executed instruction
-system.cpu.op_class::IntDiv                         1      0.02%     64.04% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::MemRead                     1163     20.00%     84.08% # Class of executed instruction
-system.cpu.op_class::MemWrite                     926     15.92%    100.00% # Class of executed instruction
+system.cpu.Branches                               883                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   637     11.32%     11.32% # Class of executed instruction
+system.cpu.op_class::IntAlu                      2950     52.44%     63.77% # Class of executed instruction
+system.cpu.op_class::IntMult                        2      0.04%     63.80% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.80% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.04%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1132     20.12%     83.96% # Class of executed instruction
+system.cpu.op_class::MemWrite                     902     16.04%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5815                       # Class of executed instruction
+system.cpu.op_class::total                       5625                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 88e0b5c68d630145d63f4bd45c3cac07bcffb74d..e8e105f9d88979d91f3ce326a090efeccc4cb4fe 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000125                       # Number of seconds simulated
-sim_ticks                                      125334                       # Number of ticks simulated
-final_tick                                     125334                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000123                       # Number of seconds simulated
+sim_ticks                                      122907                       # Number of ticks simulated
+final_tick                                     122907                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56489                       # Simulator instruction rate (inst/s)
-host_op_rate                                    56481                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1217426                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 162604                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-sim_insts                                        5814                       # Number of instructions simulated
-sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  19204                       # Simulator instruction rate (inst/s)
+host_op_rate                                    19202                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 419624                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 174296                       # Number of bytes of host memory used
+host_seconds                                     0.29                       # Real time elapsed on the host
+sim_insts                                        5624                       # Number of instructions simulated
+sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   2982                       # delay histogram for all message
-system.ruby.delayHist                    |        2982    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     2982                       # delay histogram for all message
+system.ruby.delayHist::samples                   2936                       # delay histogram for all message
+system.ruby.delayHist                    |        2936    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     2936                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         7904                      
+system.ruby.outstanding_req_hist::samples         7659                      
 system.ruby.outstanding_req_hist::mean              1                      
 system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        7904    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          7904                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        7659    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          7659                      
 system.ruby.latency_hist::bucket_size              16                      
 system.ruby.latency_hist::max_bucket              159                      
-system.ruby.latency_hist::samples                7903                      
-system.ruby.latency_hist::mean              14.859041                      
-system.ruby.latency_hist::gmean              5.372254                      
-system.ruby.latency_hist::stdev             24.716041                      
-system.ruby.latency_hist                 |        6410     81.11%     81.11% |           0      0.00%     81.11% |           0      0.00%     81.11% |         328      4.15%     85.26% |        1088     13.77%     99.03% |          74      0.94%     99.96% |           3      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  7903                      
+system.ruby.latency_hist::samples                7658                      
+system.ruby.latency_hist::mean              15.049491                      
+system.ruby.latency_hist::gmean              5.422767                      
+system.ruby.latency_hist::stdev             24.869733                      
+system.ruby.latency_hist                 |        6188     80.80%     80.80% |           0      0.00%     80.80% |           0      0.00%     80.80% |         330      4.31%     85.11% |        1061     13.85%     98.97% |          77      1.01%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  7658                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            6410                      
+system.ruby.hit_latency_hist::samples            6188                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6410    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              6410                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6188    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              6188                      
 system.ruby.miss_latency_hist::bucket_size           16                      
 system.ruby.miss_latency_hist::max_bucket          159                      
-system.ruby.miss_latency_hist::samples           1493                      
-system.ruby.miss_latency_hist::mean         65.774280                      
-system.ruby.miss_latency_hist::gmean        65.543617                      
-system.ruby.miss_latency_hist::stdev         6.088981                      
-system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         328     21.97%     21.97% |        1088     72.87%     94.84% |          74      4.96%     99.80% |           3      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total             1493                      
-system.ruby.Directory.incomplete_times           1492                      
+system.ruby.miss_latency_hist::samples           1470                      
+system.ruby.miss_latency_hist::mean         65.772109                      
+system.ruby.miss_latency_hist::gmean        65.537231                      
+system.ruby.miss_latency_hist::stdev         6.143987                      
+system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         330     22.45%     22.45% |        1061     72.18%     94.63% |          77      5.24%     99.86% |           2      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total             1470                      
+system.ruby.Directory.incomplete_times           1469                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.cacheMemory.demand_hits         6410                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses         1493                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses         7903                       # Number of cache demand accesses
-system.ruby.network.routers0.percent_links_utilized     5.948107                      
-system.ruby.network.routers0.msg_count.Control::2         1493                      
-system.ruby.network.routers0.msg_count.Data::2         1489                      
-system.ruby.network.routers0.msg_count.Response_Data::4         1493                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3         1489                      
-system.ruby.network.routers0.msg_bytes.Control::2        11944                      
-system.ruby.network.routers0.msg_bytes.Data::2       107208                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4       107496                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3        11912                      
-system.ruby.dir_cntrl0.memBuffer.memReq          2982                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead         1493                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite         1489                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh          871                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles         2125                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ            5                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls         2130                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.714286                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy          839                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy         1172                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           34                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait           80                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |         236      7.91%      7.91% |         108      3.62%     11.54% |          74      2.48%     14.02% |          51      1.71%     15.73% |          26      0.87%     16.60% |         104      3.49%     20.09% |          18      0.60%     20.69% |          38      1.27%     21.97% |          16      0.54%     22.50% |          52      1.74%     24.25% |         154      5.16%     29.41% |          50      1.68%     31.09% |          22      0.74%     31.82% |          70      2.35%     34.17% |          30      1.01%     35.18% |         220      7.38%     42.56% |          80      2.68%     45.24% |          58      1.95%     47.18% |          80      2.68%     49.87% |         118      3.96%     53.82% |          42      1.41%     55.23% |          52      1.74%     56.98% |          82      2.75%     59.73% |         168      5.63%     65.36% |         116      3.89%     69.25% |          80      2.68%     71.93% |         138      4.63%     76.56% |         110      3.69%     80.25% |         208      6.98%     87.22% |         273      9.15%     96.38% |          40      1.34%     97.72% |          68      2.28%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total         2982                       # Number of accesses per bank
-system.ruby.network.routers1.percent_links_utilized     5.948107                      
-system.ruby.network.routers1.msg_count.Control::2         1493                      
-system.ruby.network.routers1.msg_count.Data::2         1489                      
-system.ruby.network.routers1.msg_count.Response_Data::4         1493                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3         1489                      
-system.ruby.network.routers1.msg_bytes.Control::2        11944                      
-system.ruby.network.routers1.msg_bytes.Data::2       107208                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4       107496                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3        11912                      
-system.ruby.network.routers2.percent_links_utilized     5.948107                      
-system.ruby.network.routers2.msg_count.Control::2         1493                      
-system.ruby.network.routers2.msg_count.Data::2         1489                      
-system.ruby.network.routers2.msg_count.Response_Data::4         1493                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3         1489                      
-system.ruby.network.routers2.msg_bytes.Control::2        11944                      
-system.ruby.network.routers2.msg_bytes.Data::2       107208                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4       107496                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3        11912                      
-system.ruby.network.msg_count.Control            4479                      
-system.ruby.network.msg_count.Data               4467                      
-system.ruby.network.msg_count.Response_Data         4479                      
-system.ruby.network.msg_count.Writeback_Control         4467                      
-system.ruby.network.msg_byte.Control            35832                      
-system.ruby.network.msg_byte.Data              321624                      
-system.ruby.network.msg_byte.Response_Data       322488                      
-system.ruby.network.msg_byte.Writeback_Control        35736                      
+system.ruby.l1_cntrl0.cacheMemory.demand_hits         6188                       # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses         1470                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses         7658                       # Number of cache demand accesses
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     5.971995                      
+system.ruby.network.routers0.msg_count.Control::2         1470                      
+system.ruby.network.routers0.msg_count.Data::2         1466                      
+system.ruby.network.routers0.msg_count.Response_Data::4         1470                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3         1466                      
+system.ruby.network.routers0.msg_bytes.Control::2        11760                      
+system.ruby.network.routers0.msg_bytes.Data::2       105552                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4       105840                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3        11728                      
+system.ruby.dir_cntrl0.memBuffer.memReq          2936                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead         1470                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite         1466                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh          854                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles         2108                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ            2                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls         2110                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.718665                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          845                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy         1147                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           40                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait           76                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |         232      7.90%      7.90% |         108      3.68%     11.58% |          64      2.18%     13.76% |          51      1.74%     15.50% |          26      0.89%     16.38% |         106      3.61%     19.99% |          20      0.68%     20.67% |          38      1.29%     21.97% |          16      0.54%     22.51% |          52      1.77%     24.28% |         138      4.70%     28.99% |          48      1.63%     30.62% |          16      0.54%     31.16% |          70      2.38%     33.55% |          30      1.02%     34.57% |         220      7.49%     42.06% |          80      2.72%     44.79% |          60      2.04%     46.83% |          80      2.72%     49.56% |         118      4.02%     53.58% |          46      1.57%     55.14% |          52      1.77%     56.91% |          84      2.86%     59.78% |         180      6.13%     65.91% |         108      3.68%     69.58% |          74      2.52%     72.10% |         140      4.77%     76.87% |         112      3.81%     80.69% |         198      6.74%     87.43% |         261      8.89%     96.32% |          40      1.36%     97.68% |          68      2.32%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         2936                       # Number of accesses per bank
+system.ruby.network.routers1.percent_links_utilized     5.971995                      
+system.ruby.network.routers1.msg_count.Control::2         1470                      
+system.ruby.network.routers1.msg_count.Data::2         1466                      
+system.ruby.network.routers1.msg_count.Response_Data::4         1470                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3         1466                      
+system.ruby.network.routers1.msg_bytes.Control::2        11760                      
+system.ruby.network.routers1.msg_bytes.Data::2       105552                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4       105840                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3        11728                      
+system.ruby.network.routers2.percent_links_utilized     5.971995                      
+system.ruby.network.routers2.msg_count.Control::2         1470                      
+system.ruby.network.routers2.msg_count.Data::2         1466                      
+system.ruby.network.routers2.msg_count.Response_Data::4         1470                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3         1466                      
+system.ruby.network.routers2.msg_bytes.Control::2        11760                      
+system.ruby.network.routers2.msg_bytes.Data::2       105552                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4       105840                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3        11728                      
+system.ruby.network.msg_count.Control            4410                      
+system.ruby.network.msg_count.Data               4398                      
+system.ruby.network.msg_count.Response_Data         4410                      
+system.ruby.network.msg_count.Writeback_Control         4398                      
+system.ruby.network.msg_byte.Control            35280                      
+system.ruby.network.msg_byte.Data              316656                      
+system.ruby.network.msg_byte.Response_Data       317520                      
+system.ruby.network.msg_byte.Writeback_Control        35184                      
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -122,182 +122,182 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                           125334                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                    7                       # Number of system calls
+system.cpu.numCycles                           122907                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5814                       # Number of instructions committed
-system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
+system.cpu.committedInsts                        5624                       # Number of instructions committed
+system.cpu.committedOps                          5624                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4944                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
-system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5113                       # number of integer instructions
+system.cpu.num_func_calls                         190                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          649                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4944                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7054                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3281                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2089                       # number of memory refs
-system.cpu.num_load_insts                        1163                       # Number of load instructions
-system.cpu.num_store_insts                        926                       # Number of store instructions
+system.cpu.num_mem_refs                          2034                       # number of memory refs
+system.cpu.num_load_insts                        1132                       # Number of load instructions
+system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     125334                       # Number of busy cycles
+system.cpu.num_busy_cycles                     122907                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                               915                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                   657     11.30%     11.30% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3063     52.67%     63.97% # Class of executed instruction
-system.cpu.op_class::IntMult                        3      0.05%     64.02% # Class of executed instruction
-system.cpu.op_class::IntDiv                         1      0.02%     64.04% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::MemRead                     1163     20.00%     84.08% # Class of executed instruction
-system.cpu.op_class::MemWrite                     926     15.92%    100.00% # Class of executed instruction
+system.cpu.Branches                               883                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   637     11.32%     11.32% # Class of executed instruction
+system.cpu.op_class::IntAlu                      2950     52.44%     63.77% # Class of executed instruction
+system.cpu.op_class::IntMult                        2      0.04%     63.80% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.80% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.04%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1132     20.12%     83.96% # Class of executed instruction
+system.cpu.op_class::MemWrite                     902     16.04%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5815                       # Class of executed instruction
-system.ruby.network.routers0.throttle0.link_utilization     5.954490                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1493                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1489                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       107496                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        11912                      
-system.ruby.network.routers0.throttle1.link_utilization     5.941724                      
-system.ruby.network.routers0.throttle1.msg_count.Control::2         1493                      
-system.ruby.network.routers0.throttle1.msg_count.Data::2         1489                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2        11944                      
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2       107208                      
-system.ruby.network.routers1.throttle0.link_utilization     5.941724                      
-system.ruby.network.routers1.throttle0.msg_count.Control::2         1493                      
-system.ruby.network.routers1.throttle0.msg_count.Data::2         1489                      
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2        11944                      
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2       107208                      
-system.ruby.network.routers1.throttle1.link_utilization     5.954490                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1493                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1489                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       107496                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        11912                      
-system.ruby.network.routers2.throttle0.link_utilization     5.954490                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1493                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1489                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       107496                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        11912                      
-system.ruby.network.routers2.throttle1.link_utilization     5.941724                      
-system.ruby.network.routers2.throttle1.msg_count.Control::2         1493                      
-system.ruby.network.routers2.throttle1.msg_count.Data::2         1489                      
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2        11944                      
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2       107208                      
+system.cpu.op_class::total                       5625                       # Class of executed instruction
+system.ruby.network.routers0.throttle0.link_utilization     5.978504                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1470                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1466                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       105840                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        11728                      
+system.ruby.network.routers0.throttle1.link_utilization     5.965486                      
+system.ruby.network.routers0.throttle1.msg_count.Control::2         1470                      
+system.ruby.network.routers0.throttle1.msg_count.Data::2         1466                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2        11760                      
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2       105552                      
+system.ruby.network.routers1.throttle0.link_utilization     5.965486                      
+system.ruby.network.routers1.throttle0.msg_count.Control::2         1470                      
+system.ruby.network.routers1.throttle0.msg_count.Data::2         1466                      
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2        11760                      
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2       105552                      
+system.ruby.network.routers1.throttle1.link_utilization     5.978504                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1470                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1466                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       105840                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        11728                      
+system.ruby.network.routers2.throttle0.link_utilization     5.978504                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1470                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1466                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       105840                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        11728                      
+system.ruby.network.routers2.throttle1.link_utilization     5.965486                      
+system.ruby.network.routers2.throttle1.msg_count.Control::2         1470                      
+system.ruby.network.routers2.throttle1.msg_count.Data::2         1466                      
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2        11760                      
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2       105552                      
 system.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples          1493                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |        1493    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total            1493                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples          1470                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |        1470    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total            1470                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples          1489                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |        1489    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total            1489                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples          1466                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |        1466    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total            1466                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size           16                      
 system.ruby.LD.latency_hist::max_bucket           159                      
-system.ruby.LD.latency_hist::samples             1163                      
-system.ruby.LD.latency_hist::mean           39.248495                      
-system.ruby.LD.latency_hist::gmean          17.996261                      
-system.ruby.LD.latency_hist::stdev          30.948505                      
-system.ruby.LD.latency_hist              |         486     41.79%     41.79% |           0      0.00%     41.79% |           0      0.00%     41.79% |         147     12.64%     54.43% |         509     43.77%     98.19% |          19      1.63%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total               1163                      
+system.ruby.LD.latency_hist::samples             1132                      
+system.ruby.LD.latency_hist::mean           39.690813                      
+system.ruby.LD.latency_hist::gmean          18.392553                      
+system.ruby.LD.latency_hist::stdev          30.890580                      
+system.ruby.LD.latency_hist              |         465     41.08%     41.08% |           0      0.00%     41.08% |           0      0.00%     41.08% |         147     12.99%     54.06% |         497     43.90%     97.97% |          22      1.94%     99.91% |           1      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total               1132                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples          486                      
+system.ruby.LD.hit_latency_hist::samples          465                      
 system.ruby.LD.hit_latency_hist::mean               3                      
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         486    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total            486                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         465    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total            465                      
 system.ruby.LD.miss_latency_hist::bucket_size           16                      
 system.ruby.LD.miss_latency_hist::max_bucket          159                      
-system.ruby.LD.miss_latency_hist::samples          677                      
-system.ruby.LD.miss_latency_hist::mean      65.270310                      
-system.ruby.LD.miss_latency_hist::gmean     65.122528                      
-system.ruby.LD.miss_latency_hist::stdev      4.861017                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         147     21.71%     21.71% |         509     75.18%     96.90% |          19      2.81%     99.70% |           2      0.30%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total           677                      
+system.ruby.LD.miss_latency_hist::samples          667                      
+system.ruby.LD.miss_latency_hist::mean      65.269865                      
+system.ruby.LD.miss_latency_hist::gmean     65.112332                      
+system.ruby.LD.miss_latency_hist::stdev      5.027167                      
+system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         147     22.04%     22.04% |         497     74.51%     96.55% |          22      3.30%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total           667                      
 system.ruby.ST.latency_hist::bucket_size           16                      
 system.ruby.ST.latency_hist::max_bucket           159                      
-system.ruby.ST.latency_hist::samples              925                      
-system.ruby.ST.latency_hist::mean           17.897297                      
-system.ruby.ST.latency_hist::gmean           6.243616                      
-system.ruby.ST.latency_hist::stdev          26.860092                      
-system.ruby.ST.latency_hist              |         705     76.22%     76.22% |           0      0.00%     76.22% |           0      0.00%     76.22% |          49      5.30%     81.51% |         158     17.08%     98.59% |          13      1.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total                925                      
+system.ruby.ST.latency_hist::samples              901                      
+system.ruby.ST.latency_hist::mean           18.103219                      
+system.ruby.ST.latency_hist::gmean           6.303338                      
+system.ruby.ST.latency_hist::stdev          27.010521                      
+system.ruby.ST.latency_hist              |         684     75.92%     75.92% |           0      0.00%     75.92% |           0      0.00%     75.92% |          46      5.11%     81.02% |         158     17.54%     98.56% |          13      1.44%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total                901                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
-system.ruby.ST.hit_latency_hist::samples          705                      
+system.ruby.ST.hit_latency_hist::samples          684                      
 system.ruby.ST.hit_latency_hist::mean               3                      
 system.ruby.ST.hit_latency_hist::gmean       3.000000                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         705    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total            705                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         684    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total            684                      
 system.ruby.ST.miss_latency_hist::bucket_size           16                      
 system.ruby.ST.miss_latency_hist::max_bucket          159                      
-system.ruby.ST.miss_latency_hist::samples          220                      
-system.ruby.ST.miss_latency_hist::mean      65.636364                      
-system.ruby.ST.miss_latency_hist::gmean     65.386932                      
-system.ruby.ST.miss_latency_hist::stdev      6.334983                      
-system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          49     22.27%     22.27% |         158     71.82%     94.09% |          13      5.91%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total           220                      
+system.ruby.ST.miss_latency_hist::samples          217                      
+system.ruby.ST.miss_latency_hist::mean      65.709677                      
+system.ruby.ST.miss_latency_hist::gmean     65.456791                      
+system.ruby.ST.miss_latency_hist::stdev      6.376574                      
+system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          46     21.20%     21.20% |         158     72.81%     94.01% |          13      5.99%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total           217                      
 system.ruby.IFETCH.latency_hist::bucket_size           16                      
 system.ruby.IFETCH.latency_hist::max_bucket          159                      
-system.ruby.IFETCH.latency_hist::samples         5815                      
-system.ruby.IFETCH.latency_hist::mean        9.497850                      
-system.ruby.IFETCH.latency_hist::gmean       4.118767                      
-system.ruby.IFETCH.latency_hist::stdev      19.364276                      
-system.ruby.IFETCH.latency_hist          |        5219     89.75%     89.75% |           0      0.00%     89.75% |           0      0.00%     89.75% |         132      2.27%     92.02% |         421      7.24%     99.26% |          42      0.72%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total           5815                      
+system.ruby.IFETCH.latency_hist::samples         5625                      
+system.ruby.IFETCH.latency_hist::mean        9.601422                      
+system.ruby.IFETCH.latency_hist::gmean       4.140083                      
+system.ruby.IFETCH.latency_hist::stdev      19.494566                      
+system.ruby.IFETCH.latency_hist          |        5039     89.58%     89.58% |           0      0.00%     89.58% |           0      0.00%     89.58% |         137      2.44%     92.02% |         406      7.22%     99.24% |          42      0.75%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total           5625                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
-system.ruby.IFETCH.hit_latency_hist::samples         5219                      
+system.ruby.IFETCH.hit_latency_hist::samples         5039                      
 system.ruby.IFETCH.hit_latency_hist::mean            3                      
 system.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        5219    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total         5219                      
+system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        5039    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total         5039                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size           16                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          159                      
-system.ruby.IFETCH.miss_latency_hist::samples          596                      
-system.ruby.IFETCH.miss_latency_hist::mean    66.397651                      
-system.ruby.IFETCH.miss_latency_hist::gmean    66.083596                      
-system.ruby.IFETCH.miss_latency_hist::stdev     7.118063                      
-system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         132     22.15%     22.15% |         421     70.64%     92.79% |          42      7.05%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total          596                      
+system.ruby.IFETCH.miss_latency_hist::samples          586                      
+system.ruby.IFETCH.miss_latency_hist::mean    66.366894                      
+system.ruby.IFETCH.miss_latency_hist::gmean    66.054272                      
+system.ruby.IFETCH.miss_latency_hist::stdev     7.096661                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         137     23.38%     23.38% |         406     69.28%     92.66% |          42      7.17%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total          586                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size           16                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          159                      
-system.ruby.Directory.miss_mach_latency_hist::samples         1493                      
-system.ruby.Directory.miss_mach_latency_hist::mean    65.774280                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    65.543617                      
-system.ruby.Directory.miss_mach_latency_hist::stdev     6.088981                      
-system.ruby.Directory.miss_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         328     21.97%     21.97% |        1088     72.87%     94.84% |          74      4.96%     99.80% |           3      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total         1493                      
+system.ruby.Directory.miss_mach_latency_hist::samples         1470                      
+system.ruby.Directory.miss_mach_latency_hist::mean    65.772109                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    65.537231                      
+system.ruby.Directory.miss_mach_latency_hist::stdev     6.143987                      
+system.ruby.Directory.miss_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         330     22.45%     22.45% |        1061     72.18%     94.63% |          77      5.24%     99.86% |           2      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total         1470                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            1                      
@@ -326,51 +326,51 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion |
 system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            1                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           16                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          159                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          677                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    65.270310                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    65.122528                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev     4.861017                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         147     21.71%     21.71% |         509     75.18%     96.90% |          19      2.81%     99.70% |           2      0.30%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total          677                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples          667                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean    65.269865                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    65.112332                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev     5.027167                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         147     22.04%     22.04% |         497     74.51%     96.55% |          22      3.30%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total          667                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           16                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          159                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          220                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    65.636364                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    65.386932                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev     6.334983                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          49     22.27%     22.27% |         158     71.82%     94.09% |          13      5.91%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total          220                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          217                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean    65.709677                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    65.456791                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev     6.376574                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          46     21.20%     21.20% |         158     72.81%     94.01% |          13      5.99%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total          217                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           16                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          159                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          596                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    66.397651                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    66.083596                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev     7.118063                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         132     22.15%     22.15% |         421     70.64%     92.79% |          42      7.05%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          596                      
-system.ruby.L1Cache_Controller.Load              1163      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch            5815      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              925      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data              1493      0.00%      0.00%
-system.ruby.L1Cache_Controller.Replacement         1489      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack         1489      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Load             677      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch           596      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            220      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Load             486      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch          5219      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Store            705      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Replacement         1489      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack         1489      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data           1273      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data            220      0.00%      0.00%
-system.ruby.Directory_Controller.GETX            1493      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX            1489      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1493      0.00%      0.00%
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-system.ruby.Directory_Controller.I.GETX          1493      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX          1489      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data         1493      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack         1489      0.00%      0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          586                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    66.366894                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    66.054272                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev     7.096661                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         137     23.38%     23.38% |         406     69.28%     92.66% |          42      7.17%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          586                      
+system.ruby.L1Cache_Controller.Load              1132      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch            5625      0.00%      0.00%
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+system.ruby.L1Cache_Controller.Replacement         1466      0.00%      0.00%
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+system.ruby.L1Cache_Controller.I.Load             667      0.00%      0.00%
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+system.ruby.Directory_Controller.GETX            1470      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX            1466      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data         1470      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack         1466      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX          1470      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX          1466      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data         1470      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack         1466      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index a40ed7ca51bec59ff2f056272f7890c53b2e81c7..84d2a731d0e9f0aab1f606d2c8bbd80c4e727829 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,56 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000032                       # Number of seconds simulated
-sim_ticks                                    31633000                       # Number of ticks simulated
-final_tick                                   31633000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000031                       # Number of seconds simulated
+sim_ticks                                    30902000                       # Number of ticks simulated
+final_tick                                   30902000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 442331                       # Simulator instruction rate (inst/s)
-host_op_rate                                   441894                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2401898254                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 285092                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        5814                       # Number of instructions simulated
-sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 104539                       # Simulator instruction rate (inst/s)
+host_op_rate                                   104503                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              574021463                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 276192                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+sim_insts                                        5624                       # Number of instructions simulated
+sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19264                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            608984289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            279202099                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               888186388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       608984289                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          608984289                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           608984289                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           279202099                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              888186388                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                 388                       # Transaction distribution
-system.membus.trans_dist::ReadResp                388                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               51                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          878                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    878                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   28096                       # Cumulative packet size per connected master and slave (bytes)
+system.physmem.bytes_read::cpu.inst             18752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8768                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                27520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        18752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           18752                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                293                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                137                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   430                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            606821565                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            283735681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               890557245                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       606821565                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          606821565                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           606821565                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           283735681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              890557245                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq                 380                       # Transaction distribution
+system.membus.trans_dist::ReadResp                380                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          860                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    860                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        27520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   27520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               439                       # Request fanout histogram
+system.membus.snoop_fanout::samples               430                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     439    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     430    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 439                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              439000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 430                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              430000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3951000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            3870000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -71,116 +71,116 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            63266                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                    7                       # Number of system calls
+system.cpu.numCycles                            61804                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5814                       # Number of instructions committed
-system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
+system.cpu.committedInsts                        5624                       # Number of instructions committed
+system.cpu.committedOps                          5624                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4944                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
-system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5113                       # number of integer instructions
+system.cpu.num_func_calls                         190                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          649                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4944                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7054                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3281                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2089                       # number of memory refs
-system.cpu.num_load_insts                        1163                       # Number of load instructions
-system.cpu.num_store_insts                        926                       # Number of store instructions
+system.cpu.num_mem_refs                          2034                       # number of memory refs
+system.cpu.num_load_insts                        1132                       # Number of load instructions
+system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      63266                       # Number of busy cycles
+system.cpu.num_busy_cycles                      61804                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                               915                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                   657     11.30%     11.30% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3063     52.67%     63.97% # Class of executed instruction
-system.cpu.op_class::IntMult                        3      0.05%     64.02% # Class of executed instruction
-system.cpu.op_class::IntDiv                         1      0.02%     64.04% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.08% # Class of executed instruction
-system.cpu.op_class::MemRead                     1163     20.00%     84.08% # Class of executed instruction
-system.cpu.op_class::MemWrite                     926     15.92%    100.00% # Class of executed instruction
+system.cpu.Branches                               883                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   637     11.32%     11.32% # Class of executed instruction
+system.cpu.op_class::IntAlu                      2950     52.44%     63.77% # Class of executed instruction
+system.cpu.op_class::IntMult                        2      0.04%     63.80% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.80% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.04%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1132     20.12%     83.96% # Class of executed instruction
+system.cpu.op_class::MemWrite                     902     16.04%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5815                       # Class of executed instruction
+system.cpu.op_class::total                       5625                       # Class of executed instruction
 system.cpu.icache.tags.replacements                13                       # number of replacements
-system.cpu.icache.tags.tagsinuse           132.545353                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                5513                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               303                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.194719                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           129.108186                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                5331                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               295                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.071186                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   132.545353                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.064719                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.064719                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.141602                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11935                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11935                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         5513                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5513                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5513                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5513                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5513                       # number of overall hits
-system.cpu.icache.overall_hits::total            5513                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          303                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           303                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          303                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            303                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          303                       # number of overall misses
-system.cpu.icache.overall_misses::total           303                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16581000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16581000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16581000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16581000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16581000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16581000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5816                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5816                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5816                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5816                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5816                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5816                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052098                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.052098                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.052098                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.052098                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.052098                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.052098                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54722.772277                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54722.772277                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst   129.108186                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063041                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063041                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          282                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.137695                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11547                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11547                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         5331                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5331                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5331                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5331                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5331                       # number of overall hits
+system.cpu.icache.overall_hits::total            5331                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          295                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           295                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          295                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            295                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          295                       # number of overall misses
+system.cpu.icache.overall_misses::total           295                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16141000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16141000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16141000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16141000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16141000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16141000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5626                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5626                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5626                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5626                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5626                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5626                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052435                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.052435                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.052435                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.052435                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.052435                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.052435                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54715.254237                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54715.254237                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -189,98 +189,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          303                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          303                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          303                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          303                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          303                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          303                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15975000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     15975000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15975000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     15975000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15975000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     15975000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.052098                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.052098                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          295                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          295                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          295                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          295                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          295                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          295                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15551000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15551000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15551000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15551000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15551000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15551000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052435                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052435                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052435                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.052435                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052435                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.052435                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          188.114191                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          183.724070                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              388                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.005155                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              380                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.005263                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   133.890657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    54.223533                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004086                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001655                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005741                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011841                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3967                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3967                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.264551                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    53.459518                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003975                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001631                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005607                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          380                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011597                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3886                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3886                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          301                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          293                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          388                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          301                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           439                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          439                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15652000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_misses::total          380                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
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+system.cpu.l2cache.overall_misses::total          430                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15236000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4524000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     20176000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2652000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2652000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15652000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7176000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     22828000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15652000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7176000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     22828000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          303                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::total     19760000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2600000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2600000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15236000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7124000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst     15236000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7124000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22360000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          295                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          390                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          303                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          441                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          303                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          441                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993399                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_accesses::total          382                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          295                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          137                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          432                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          295                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          137                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          432                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993220                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.994872                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.994764                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993399                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993220                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995465                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993399                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995370                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993220                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995465                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995370                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
@@ -300,39 +300,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          293                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          388                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          439                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          439                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_misses::total          380                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          293                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          293                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          430                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11720000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3480000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15520000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12040000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5520000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17560000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12040000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5520000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17560000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5480000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5480000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994872                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994764                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995465                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995370                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993220                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995465                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995370                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
@@ -346,60 +346,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.492114                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1950                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.130435                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            86.158665                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1896                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.839416                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.492114                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021360                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021360                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4314                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4314                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            874                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1950                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1950                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1950                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1950                       # number of overall hits
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.158665                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021035                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021035                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          111                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033447                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4203                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4203                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1045                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1045                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          851                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            851                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1896                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1896                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1896                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1896                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           51                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           51                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.dcache.overall_misses::total           138                       # number of overall misses
+system.cpu.dcache.WriteReq_misses::cpu.data           50                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           50                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          137                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            137                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          137                       # number of overall misses
+system.cpu.dcache.overall_misses::total           137                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data      4785000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      4785000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2805000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2805000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7590000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7590000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074807                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.074807                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.066092                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.066092                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.066092                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.066092                       # miss rate for overall accesses
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2750000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2750000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7535000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7535000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7535000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7535000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2033                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2033                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2033                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2033                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076855                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076855                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055494                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.055494                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.067388                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.067388                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.067388                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.067388                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
@@ -418,28 +418,28 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4611000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      4611000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2703000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2703000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2650000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2650000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7261000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7261000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7261000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7261000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076855                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076855                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.067388                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.067388                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -449,33 +449,33 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            390                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           390                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           51                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          606                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               882                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq            382                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           382                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          590                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          274                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               864                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              27648                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          441                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          432                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                441    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                432    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            441                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            432                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         216000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        454500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        442500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        207000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        205500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 8d84a5cfe90d23c8c77e4bbef2400e919f9aec50..b652069eee4ee2357834d77342742a5cd3c6be14 100644 (file)
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -305,7 +305,7 @@ system.cpu.fetch.Insts                          13500                       # Nu
 system.cpu.fetch.Branches                        2332                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                880                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          3710                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     864                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                     865                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           159                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
@@ -511,13 +511,13 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts            4587                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               277                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11593                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.499612                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.370164                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11592                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.499655                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.370216                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9440     81.43%     81.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          839      7.24%     88.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          524      4.52%     93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9439     81.43%     81.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          839      7.24%     88.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          524      4.52%     93.18% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          224      1.93%     95.12% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::4          167      1.44%     96.56% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          112      0.97%     97.52% # Number of insts commited each cycle
@@ -527,7 +527,7 @@ system.cpu.commit.committed_per_cycle::8          111      0.96%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11593                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11592                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -575,8 +575,8 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   111                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21861                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21469                       # The number of ROB writes
+system.cpu.rob.rob_reads                        21860                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21470                       # The number of ROB writes
 system.cpu.timesIdled                             245                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           25413                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
@@ -585,7 +585,7 @@ system.cpu.cpi                               6.511740                       # CP
 system.cpu.cpi_total                         6.511740                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.153569                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.153569                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13743                       # number of integer regfile reads
+system.cpu.int_regfile_reads                    13744                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7176                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes

diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 080dd7c2e36cd08216b01896e9ec462abb59bf4c..d419dc80f71b7ed4ea8eb9361e61a441240b8fc6 100644 (file)
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -94,10 +94,10 @@ system.cpu.num_fp_register_writes                   2                       # nu
 system.cpu.num_mem_refs                          2007                       # number of memory refs
 system.cpu.num_load_insts                         961                       # Number of load instructions
 system.cpu.num_store_insts                       1046                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5793                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles                5792.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1037                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3784     65.32%     65.32% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index e454f5068310d5abf82155b134fe80842c897989..b7a6e558ab4d6d5a04220a6b0109964a8864a260 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -76,10 +76,10 @@ system.cpu.num_fp_register_writes                   0                       # nu
 system.cpu.num_mem_refs                          1401                       # number of memory refs
 system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5390                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles                5389.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                   173      3.22%      3.22% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3796     70.69%     73.91% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 0f04f976034b30a978de2e9d7391145a898ffff2..88154b71d8cda6d100abaa3889a488c7f84d7e59 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -123,10 +123,10 @@ system.cpu.num_fp_register_writes                   0                       # nu
 system.cpu.num_mem_refs                          1401                       # number of memory refs
 system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     107952                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.999991                       # Number of idle cycles
+system.cpu.num_busy_cycles               107951.000009                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.999991                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000009                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                   173      3.22%      3.22% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3796     70.69%     73.91% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 706af6d1d454f5d381764009dd8ef5872d1da90a..52edf7aee790222dcc843c6a00949486ef746b94 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes                   0                       # nu
 system.cpu.num_mem_refs                          1401                       # number of memory refs
 system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      55600                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               55599.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                   173      3.22%      3.22% # Class of executed instruction
 system.cpu.op_class::IntAlu                      3796     70.69%     73.91% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index a38f35e7a4913f9d15e35cb8aa81e8e8048be73d..83799ecfde6613240a1a8636c2d988e8b32c8dcb 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -288,7 +288,7 @@ system.cpu.fetch.Insts                          15528                       # Nu
 system.cpu.fetch.Branches                        3423                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               1111                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          9222                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1202                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                    1203                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   54                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1088                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
@@ -491,11 +491,11 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts           11720                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               588                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        19925                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.489184                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.394250                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        19924                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.489209                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.394281                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        16685     83.74%     83.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        16684     83.74%     83.74% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1         1003      5.03%     88.77% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2          547      2.75%     91.52% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          737      3.70%     95.22% # Number of insts commited each cycle
@@ -507,7 +507,7 @@ system.cpu.commit.committed_per_cycle::8          260      1.30%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        19925                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        19924                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -555,8 +555,8 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   260                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        41132                       # The number of ROB reads
-system.cpu.rob.rob_writes                       44928                       # The number of ROB writes
+system.cpu.rob.rob_reads                        41131                       # The number of ROB reads
+system.cpu.rob.rob_writes                       44929                       # The number of ROB writes
 system.cpu.timesIdled                             158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           17464                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
@@ -565,7 +565,7 @@ system.cpu.cpi                               7.315428                       # CP
 system.cpu.cpi_total                         7.315428                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.136697                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.136697                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    21340                       # number of integer regfile reads
+system.cpu.int_regfile_reads                    21341                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   13120                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                      8069                       # number of cc regfile reads

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index baff573185170ea68f91573b3223cdde87e73017..3bcc97a186bf7397654c64f067034c7c38f156c6 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes                3536                       # nu
 system.cpu.num_mem_refs                          1988                       # number of memory refs
 system.cpu.num_load_insts                        1053                       # Number of load instructions
 system.cpu.num_store_insts                        935                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      11231                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               11230.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
 system.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index be3906efe09c338361c944d528ba2a7df5e56ceb..cdd2719ec120a844f1223e708474a11a94b7802f 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -21,11 +21,11 @@ system.ruby.delayHist                    |        2750    100.00%    100.00% |
 system.ruby.delayHist::total                     2750                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         8853                      
+system.ruby.outstanding_req_hist::samples         8852                      
 system.ruby.outstanding_req_hist::mean              1                      
 system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8853    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          8853                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8852    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          8852                      
 system.ruby.latency_hist::bucket_size              16                      
 system.ruby.latency_hist::max_bucket              159                      
 system.ruby.latency_hist::samples                8852                      
@@ -126,10 +126,10 @@ system.cpu.num_cc_register_writes                3536                       # nu
 system.cpu.num_mem_refs                          1988                       # number of memory refs
 system.cpu.num_load_insts                        1053                       # Number of load instructions
 system.cpu.num_store_insts                        935                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     121759                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.999992                       # Number of idle cycles
+system.cpu.num_busy_cycles               121758.000008                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.999992                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000008                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
 system.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 8118efe8c8341054ad9c6a78b43995bc5d669c88..b43d6cab2ed73c7d6732d9b3a0c1e86980f962d1 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -77,10 +77,10 @@ system.cpu.num_cc_register_writes                3536                       # nu
 system.cpu.num_mem_refs                          1988                       # number of memory refs
 system.cpu.num_load_insts                        1053                       # Number of load instructions
 system.cpu.num_store_insts                        935                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      56716                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               56715.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
 system.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction
@@ -119,9 +119,9 @@ system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Cl
 system.cpu.op_class::total                       9748                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           105.550219                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                6637                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs                6636                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               228                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             29.109649                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             29.105263                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   105.550219                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.051538                       # Average percentage of cache occupancy
@@ -130,14 +130,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024          228
 system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.111328                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             13958                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            13958                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         6637                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6637                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6637                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6637                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6637                       # number of overall hits
-system.cpu.icache.overall_hits::total            6637                       # number of overall hits
+system.cpu.icache.tags.tag_accesses             13956                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            13956                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         6636                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            6636                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          6636                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             6636                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         6636                       # number of overall hits
+system.cpu.icache.overall_hits::total            6636                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          228                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           228                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          228                       # number of demand (read+write) misses
@@ -150,18 +150,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     12498000
 system.cpu.icache.demand_miss_latency::total     12498000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     12498000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     12498000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6865                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6865                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6865                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6865                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6865                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6865                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.033212                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.033212                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.033212                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.033212                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.033212                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.033212                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         6864                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6864                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6864                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6864                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6864                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6864                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.033217                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.033217                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.033217                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.033217                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.033217                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.033217                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474                       # average overall miss latency
@@ -188,12 +188,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12042000
 system.cpu.icache.demand_mshr_miss_latency::total     12042000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12042000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12042000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.033212                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.033212                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.033212                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.033217                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.033217                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.033217                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.033217                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.033217                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.033217                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index c3dfe7f26a453b33ee1f21f4875b17e30f2c8b64..390228fe98b791a1a960dcf1b1c4a483a1c2f960 100644 (file)
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -745,7 +745,7 @@ system.cpu.cpi_total                         3.619272                       # CP
 system.cpu.ipc::0                            0.138149                       # IPC: Instructions Per Cycle
 system.cpu.ipc::1                            0.138149                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.276299                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    26323                       # number of integer regfile reads
+system.cpu.int_regfile_reads                    26325                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   14897                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 118b6451da13e462379cdc9f996353add7978161..9c69b73119a1c637def14ed764efcc88cb4d40df 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -287,7 +287,7 @@ system.cpu.fetch.Insts                          40300                       # Nu
 system.cpu.fetch.Branches                        8578                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               3653                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                         16187                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2310                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                    2311                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1000                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
@@ -553,7 +553,7 @@ system.cpu.commit.op_class_0::total             15162                       # Cl
 system.cpu.commit.bw_lim_events                   273                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        54809                       # The number of ROB reads
-system.cpu.rob.rob_writes                       52996                       # The number of ROB writes
+system.cpu.rob.rob_writes                       52997                       # The number of ROB writes
 system.cpu.timesIdled                             204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           19379                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
@@ -562,7 +562,7 @@ system.cpu.cpi                               3.594417                       # CP
 system.cpu.cpi_total                         3.594417                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.278209                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.278209                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    33400                       # number of integer regfile reads
+system.cpu.int_regfile_reads                    33401                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   18599                       # number of integer regfile writes
 system.cpu.misc_regfile_reads                    7136                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 8d8eb59bccf676fb1f476625522c4180b7d3926d..aaa43757c250e63c1ea952b27f55c0c930c9a2af 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes                   0                       # nu
 system.cpu.num_mem_refs                          3683                       # number of memory refs
 system.cpu.num_load_insts                        2231                       # Number of load instructions
 system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      15225                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               15224.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              3363                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                   726      4.77%      4.77% # Class of executed instruction
 system.cpu.op_class::IntAlu                     10798     71.01%     75.78% # Class of executed instruction

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 6363c4d14d6993250af3f7b86625573faad52512..5faa1ad2c0d67ecdb223186e75026ac3a183c9da 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes                   0                       # nu
 system.cpu.num_mem_refs                          3683                       # number of memory refs
 system.cpu.num_load_insts                        2231                       # Number of load instructions
 system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      82736                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               82735.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              3363                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                   726      4.77%      4.77% # Class of executed instruction
 system.cpu.op_class::IntAlu                     10798     71.01%     75.78% # Class of executed instruction

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 759a62336d56917150f7ff39f8564497811dfb44..994a2ff39167fec29611a3ab3f5ae0b8c84ca94b 100644 (file)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -792,7 +792,7 @@ system.cpu0.fetch.Insts                        481063                       # Nu
 system.cpu0.fetch.Branches                      81418                       # Number of branches that fetch encountered
 system.cpu0.fetch.predictedBranches             76128                       # Number of branches that fetch has predicted taken
 system.cpu0.fetch.Cycles                       164143                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   2674                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.SquashCycles                   2675                       # Number of cycles fetch has spent squashing
 system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu0.fetch.PendingTrapStallCycles         1880                       # Number of stall cycles due to pending traps
 system.cpu0.fetch.CacheLines                     7123                       # Number of cache lines fetched
@@ -1058,7 +1058,7 @@ system.cpu0.commit.op_class_0::total           449934                       # Cl
 system.cpu0.commit.bw_lim_events                  488                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                      646710                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     929756                       # The number of ROB writes
+system.cpu0.rob.rob_writes                     929757                       # The number of ROB writes
 system.cpu0.timesIdled                            318                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu0.idleCycles                          23966                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu0.committedInsts                     377666                       # Number of Instructions Simulated
@@ -1067,7 +1067,7 @@ system.cpu0.cpi                              0.559735                       # CP
 system.cpu0.cpi_total                        0.559735                       # CPI: Total CPI of All Threads
 system.cpu0.ipc                              1.786559                       # IPC: Instructions Per Cycle
 system.cpu0.ipc_total                        1.786559                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  689341                       # number of integer regfile reads
+system.cpu0.int_regfile_reads                  689346                       # number of integer regfile reads
 system.cpu0.int_regfile_writes                 310987                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
 system.cpu0.misc_regfile_reads                 224004                       # number of misc regfile reads

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index f16a9829df9a1ec8a639c62fe0f501006638809b..833acaaf7b4e3debc356e1726e312f1788bbf362 100644 (file)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -327,10 +327,10 @@ system.cpu0.num_fp_register_writes                  0                       # nu
 system.cpu0.num_mem_refs                        82397                       # number of memory refs
 system.cpu0.num_load_insts                      54591                       # Number of load instructions
 system.cpu0.num_store_insts                     27806                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    175415                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
+system.cpu0.num_busy_cycles              175414.998000                       # Number of busy cycles
+system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
 system.cpu0.Branches                            29689                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                26416     15.06%     15.06% # Class of executed instruction
 system.cpu0.op_class::IntAlu                    66491     37.91%     52.97% # Class of executed instruction

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 1641360b2d45b2c120dd533963ba5ac2ea12059e..564228327a578986952a6ea69227570aa27ad773 100644 (file)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -579,10 +579,10 @@ system.cpu0.num_fp_register_writes                  0                       # nu
 system.cpu0.num_mem_refs                        74021                       # number of memory refs
 system.cpu0.num_load_insts                      49007                       # Number of load instructions
 system.cpu0.num_store_insts                     25014                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    525587                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
+system.cpu0.num_busy_cycles              525586.998000                       # Number of busy cycles
+system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
 system.cpu0.Branches                            26897                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                23624     14.89%     14.89% # Class of executed instruction
 system.cpu0.op_class::IntAlu                    60907     38.39%     53.29% # Class of executed instruction