+1998-06-18 Ulrich Drepper <drepper@cygnus.com>
+
+ * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
+
+start-sanitize-am33
+Wed Jun 17 17:54:08 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.h (MN10300_OPERAND_USP): Define.
+ (MN10300_OPERAND_SSP, MN10300_OPERAND_MSP): Likewise.
+ (MN10300_OPERAND_PC, MN10300_OPERAND_EPSW): Likewise.
+ (MN10300_OPERAND_RREG): Likewise.
+
+end-sanitize-am33
Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386.h (i386_optab): Add general form of aad and aam. Add ud2a
Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com>
- * cgen.h: Formatting changes to improve readability.
+ * cgen.h: Formatting changes to improve readability.
Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com>
start-sanitize-tx49
Wed Oct 29 17:33:37 1997 Gavin Koch <gavin@cygnus.com>
- * mips.h (INSN_4900): Added.
+ * mips.h (INSN_4900): Added.
end-sanitize-tx49
Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com>
Merge changes from Martin Hunt:
- * d30v.h: Allow up to 64 control registers. Add
+ * d30v.h: Allow up to 64 control registers. Add
SHORT_A5S format.
* d30v.h (LONG_Db): New form for delayed branches.
* d30v.h (SHORT_D2B): New form.
- * d30v.h (SHORT_A2): New form.
+ * d30v.h (SHORT_A2): New form.
- * d30v.h (OPERAND_2REG): Add new operand to indicate 2
+ * d30v.h (OPERAND_2REG): Add new operand to indicate 2
registers are used. Needed for VLIW optimization.
end-sanitize-d30v
Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com>
- * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
+ * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com>
Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com>
- * v850.h (struct v850_opcode): Remove flags field.
+ * v850.h (struct v850_opcode): Remove flags field.
Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com>
* v850.h (struct v850_opcode): Add flags field.
(struct v850_operand): Extend meaning of 'bits' and 'shift'
- fields.
+ fields.
start-sanitize-v850e
(V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v.h: Change pre_defined_registers to
+ * d10v.h: Change pre_defined_registers to
d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
* mips.h: Add macros for cop0, cop1 cop2 and cop3.
- Change mips_opcodes from const array to a pointer,
+ Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
- so that we can increase the size of the mips opcodes table
+ so that we can increase the size of the mips opcodes table
dynamically.
-
+
start-sanitize-d30v
Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
end-sanitize-tic80
start-sanitize-r5900
Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
-
+
* mips.h: add r5900.
-
+
end-sanitize-r5900
start-sanitize-tic80
Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com>
(TIC80_VECTOR): Define a flag bit for the flags. This one means
that the opcode can have two vector instructions in a single
32 bit word and we have to encode/decode both.
-
+
Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com>
* tic80.h (TIC80_OPERAND_PCREL): Renamed from
* mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
* mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
* v850.h: Fix comment, v850_operand not powerpc_operand.
-
+
Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com)
* mn10200.h: Flesh out structures and definitions needed by
Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v.h: New file.
+ * d10v.h: New file.
Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com)
(EBITOP): Likewise.
(O_LAST): Bump.
(ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
-
+
* h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
(O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
(BITOP, EBITOP): Handle new H8/S addressing modes for
(UNOP3): Handle new shift/rotate insns on the H8/S.
(insns using exr): New instructions.
(tas, mac, ldmac, clrmac, ldm, stm): New instructions.
-
+
Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com)
* h8300.h (add.l): Undo Apr 5th change. The manual I had
Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com)
- * h8300.h (xor.l) :fix bit pattern.
+ * h8300.h (xor.l) :fix bit pattern.
(L_2): New size of operand.
(trapa): Use it.
Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu)
- * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>
+ * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>
* hppa.h: #undef NONE to avoid conflict with hiux include files.
Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu)
Patches from Jeff Law, law@cs.utah.edu:
* hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
Make the tables be the same for the following instructions:
- "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
+ "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
"sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
- "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
- "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
- "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
+ "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
+ "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
+ "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
"fcmp", and "ftest".
* hppa.h: Make new and old tables the same for "break", "mtctl",
Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com)
* Patches from Jeffrey Law <law@cs.utah.edu>.
- * hppa.h: Rework single precision FP
+ * hppa.h: Rework single precision FP
instructions so that they correctly disassemble code
PA1.1 code.
* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
allows callers to break up the large initialized struct full of
- opcodes into two half-sized ones. This permits GCC to compile
+ opcodes into two half-sized ones. This permits GCC to compile
this module, since it takes exponential space for initializers.
(numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com)
- * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
+ * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
vax.h, ChangeLog: renamed from ../<foo>-opcode.h
+1998-06-18 Ulrich Drepper <drepper@cygnus.com>
+
+ * i386-dis.c: Add support for fxsave, fxrstor, sysenter and
+ sysexit.
+
Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com>
* mips-dis.c (print_insn_little_mips): Previously, instruction
end-sanitize-r5900
start-sanitize-vr5400
Thu May 28 08:46:09 1998 Catherine Moore <clm@cygnus.com>
-
+
* mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu):
Change pinfo to use WR_HILO.
-end-sanitize-vr5400
+end-sanitize-vr5400
start-sanitize-d30v
Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com>
* d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
and SHORT_B3b formats to use Rb instead of Ra.
-
+
Add FLAG_MUL16 to MUL2XH opcode.
Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
Tue May 12 13:39:51 1998 Nick Clifton <nickc@cygnus.com>
* m32r-opc.c: Regenerated - SPECIAL attribute added to some
- insns.
+ insns.
* m32r-opc.h: Regenerated - SPECIAL attribute added to some
insns.
-
+
end-sanitize-m32rx
start-sanitize-d30v
Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com>
end-sanitize-d30v
start-sanitize-r5900
Mon May 11 13:12:15 1998 Frank Ch. Eigler <fche@cygnus.com>
-
+
* mips-opc.c (break): Added 20-bit single-operand break
instruction for R5900 only.
* dis-buf.c: Internationalised.
start-sanitize-sky
* dvp-dis.c: Internationalised.
- * dvp-opc.c: Internationalised.
+ * dvp-opc.c: Internationalised.
end-sanitize-sky
* h8300-dis.c: Internationalised.
* h8500-dis.c: Internationalised.
Mon Apr 13 16:59:39 1998 Nick Clifton <nickc@cygnus.com>
* arm-dis.c (print_insn_arm): Add "_all" extension to 'C'
- operator.
+ operator.
Mon Apr 13 16:50:27 1998 Ian Lance Taylor <ian@cygnus.com>
* ns32k-dis.c (bit_extract_simple): New function to extract bits
from an arbitrary valid buffer instead of fetching them on demand
- using fetch_data().
+ using fetch_data().
(invalid_float): use bit_extract_simple() instead of bit_extract().
start-sanitize-m32rx
Wed Apr 1 14:57:54 1998 Nick Clifton <nickc@cygnus.com>
- * m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
- * m32r-opc.h: Add extra control registers.
+ * m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
+ * m32r-opc.h: Add extra control registers.
end-sanitize-m32rx
Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com>
These patches are courtesy of Jonathan Walton and Tony Thompson
(athompso@cambridge.arm.com).
-
+
* arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC
relative addresses.
Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com>
- * m32r-opc.c: Regenerate.
- * m32r-opc.h: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com>
* arm-dis.c (print_insn_little_arm): Prevent examination of stored
symbol if none is present.
(print_insn_big_arm): Prevent examination of stored symbol if
- none is present.
+ none is present.
Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com>
-
+
* d10v-opc.c (d10v_opcodes): Correct entry for RTE.
-
+
Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com>
* disassemble.c: Remove disasm_symaddr() function.
start-sanitize-tx49
Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
- * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
+ * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
Add tx49 insns and configury.
end-sanitize-tx49
Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com>
- * v850-opc.c (v850_opcodes): Further rearrangements.
+ * v850-opc.c (v850_opcodes): Further rearrangements.
start-sanitize-d30v
Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com>
and cmp instructions.
* d30v-opc.c: Correct entries for repeat*, and sat*.
- Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
+ Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
types. Correct several formats.
* d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
New form: SHORT_A2; a SHORT_A form that needs an even
register as the first operand.
- * d30v-dis.c (print_insn_d30v): Fix problem where the last
+ * d30v-dis.c (print_insn_d30v): Fix problem where the last
instruction was not being disassembled if there were an odd
number of instructions.
start-sanitize-v850e
* v850-dis.c (disassemble): Add support for v850EA instructions.
-
+
* v850-opc.c (insert_i5div, extract_i5div): New Functions.
(v850_opcodes): Add v850EA instructions.
* v850-dis.c (disassemble): Add support for v850E instructions.
-
+
* v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
insert_spe, extract_spe): New Functions.
(v850_opcodes): Add v850E instructions.
end-sanitize-v850e
-
+
* v850-opc.c: Reorganised and re-layed out to improve readability
and portability.
negating it.
(UNUSED): remove one level of parens, so MSVC doesn't choke on
nesting depth when all the macros are expanded.
-
+
Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com>
* sparc-opc.c: The fcmp v9a instructions take an integer register
Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com>
- * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
+ * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
field membership.
* mips16-opc.c (mip16_opcodes): same.
* m68k-opc.c (m68k_opcodes): Provide coldfire division module
instructions.
-
+
end-sanitize-coldfire
Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com)
* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
mulul insns on the coldfire.
-
+
Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com>
* arm-dis.c (print_insn_arm): Don't print instruction bytes.
* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
the mc68000.
-
+
Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
* m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
+ * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
start-sanitize-tic80
Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
* mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
- Change mips_opcodes from const array to a pointer,
+ Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
- so that we can increase the size of the mips opcodes table
+ so that we can increase the size of the mips opcodes table
dynamically.
start-sanitize-tic80
* d30v-opc.c: Removed references to FLAG_X.
-end-sanitize-d30v
+end-sanitize-d30v
Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com>
* Makefile.in: Add dependencies on ../bfd/bfd.h as required.
* d30v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d30v.
-end-sanitize-d30v
+end-sanitize-d30v
start-sanitize-tic80
Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com>
- * tic80-opc.c (tic80_predefined_symbols): Add symbolic
+ * tic80-opc.c (tic80_predefined_symbols): Add symbolic
representations for the floating point BITNUM values.
Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com>
start-sanitize-r5900
Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
-
+
* mips-opc.c: add r5900.
-
+
end-sanitize-r5900
start-sanitize-tic80
Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com>
* m68k-opc.c (m68k_opcodes): Changed operand specifier for the
coldfire moveb instruction to not allow an address register as
destination. Although the documentation does not indicate that
- this is invalid, experiments uncovered unexpected behavior.
+ this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation. Thanks to Andreas
Schwab for pointing this out to me.
entries are presorted so that entries with the same mnemonic are
adjacent to each other in the table. Sort the entries for each
instruction so that this is true.
-
+
end-sanitize-tic80
Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
"vsub", "vst", "xnor", and "xor" instructions.
(V_a1): Renamed from V_a, msb of accumulator reg number.
(V_a0): Add macro, lsb of accumulator reg number.
-
+
Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (print_insn_tic80): Broke excessively long
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
-
+
end-sanitize-tic80
Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com>
- * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
+ * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
move insns to handle immediate operands.
-
+
Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
Remove some opcodes that are possible, but illegal, such
as long immediate instructions with doubles for immediate
values. Add "vadd" and "vld" instructions.
-
+
Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com>
* tic80-opc.c (tic80_operands): Reorder some table entries to make
followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
than old TIC80_OPERAND_RELATIVE. Add support for new
TIC80_OPERAND_BASEREL flag bit.
-
+
Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (print_insn_tic80): Print floating point operands
(P2): Macro for the 'P2' field.
(P1): Macro for the 'P1' field.
(tic80_opcodes): Add entries for "exts", "extu", "fadd",
- "fcmp", and "fdiv".
-
+ "fcmp", and "fdiv".
+
end-sanitize-tic80
Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com)
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
- (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
+ (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
REG_BASE_M_SI, REG_BASE_M_LI respectively.
(REG_SCALED, LSI_SCALED): New operand types.
(E): New macro for 'E' bit at bit 27.
(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
opcodes, including the various size flavors (b,h,w,d) for
the direct load and store instructions.
-
+
Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
masks with "MASK_* & ~M_*" to get the M bit reset.
(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
-
+
Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
start-sanitize-tic80
(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
end-sanitize-tic80
-
+
Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com>
* mips16-opc.c: Add "abs".
* configure: Regenerate with autoconf.
* tic80-dis.c: Add file.
* tic80-opc.c: Add file.
-
+
end-sanitize-tic80
Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
-
+
* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
specifier of the effective-address operand in immediate forms of
arithmetic instructions. The specifier for the immediate operand
* mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
opcode.
- * mn10300-dis.c (disassemble): Use '$' instead of '%' for
+ * mn10300-dis.c (disassemble): Use '$' instead of '%' for
register prefix.
* mn10300-dis.c (disassemble): Prefix registers with '%'.
* mn10300-opc.c (mn10300_operands): Add "REGS" for a register
list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-
+
Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
* mn10300-opc.c (mn10300_operands): Hijack "bits" field
in MN10300_OPERAND_SPLIT operands for how many bits
appear in the basic insn word. Add IMM32_HIGH24,
- IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
+ IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
(mn10300_opcodes): Use new operands as needed.
* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
standard disassembly.
* alpha-opc.c (alpha_operands): Rearrange flags slot.
- (alpha_opcodes): Add new BWX, CIX, and MAX instructions.
+ (alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
-
+
Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
Update many operand fields to deal with signed vs unsigned
issues. Fix one or two typos in the "mov" instruction
opcode, mask and/or operand fields.
-
+
Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
-
+
Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com>
* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
* sh-opc.h (sh_arg_type): Add F_FR0.
(sh_table, case fmac): Add F_FR0 as first argument.
-
+
Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com>
* sh-opc.h (sh_opcode_info): Increase arg array size to 4.
* sh-opc.h: Added bsrf and braf.
-Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
+Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
* arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete
bogus [ls]fm{ea,fd} patterns.
* mpw-config.in (target_arch): Compute from canonical target.
(m68k, mips, powerpc, sparc): Add architectures.
* mpw-make.in (disassemble.c.o): Add.
- (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
+ (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
* mpw-config.in (BFD_MACHINES): Set to a default value.
* mpw-make.in (BFD_MACHINES): Remove wired-in value.
Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu)
* hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template.
- No space before 'u', 'f', or 'N'.
+ No space before 'u', 'f', or 'N'.
Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com)
Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de)
* alpha-opc.h, alpha-dis.c (print_insn_alpha): Add
- FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
+ FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
FLOAT_FORMAT_CODE to put out floating point register names.
Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
defined, since gdb has been fixed.
Changes from Jeff Law, law@cs.utah.edu:
- * hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
+ * hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
fput_reg_r, fput_creg, fput_const, and fputs_filtered should
be a *disassemble_info, not a *FILE.
* hppa-dis.c: Support 'd', '!', and 'a'.
projects / binutils-gdb.git / commitdiff