radeonsi: don't set vs.epilog.export_prim_id if TES is bound

there is no VS epilog in this case

Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 9df8f47e6243c7f79a2519eeb9fac9b5ecd34283..72d0518c6bde502abaae410fd9073e747a3f7abc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -881,10 +881,10 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
                        key->as_ls = 1;
                else if (sctx->gs_shader.cso)
                        key->as_es = 1;
-
-               if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
-                   sctx->ps_shader.cso->info.uses_primid)
-                       key->part.vs.epilog.export_prim_id = 1;
+               else {
+                       if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
+                               key->part.vs.epilog.export_prim_id = 1;
+               }
                break;
        case PIPE_SHADER_TESS_CTRL:
                key->part.tcs.epilog.prim_mode =