soc: add cpu rom/sram check

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 696375f0617f51e360eed60bb932e7c77af939aa..eb2cfbbb59eb94e5715da93e7faf615ab1a7177d 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -816,6 +816,15 @@ class SoC(Module):
                 masters = list(self.csr.masters.values()),
                 slaves  = self.csr_bankarray.get_buses())
 
+        # SoC CPU Check ----------------------------------------------------------------------------
+        if not isinstance(self.cpu, cpu.CPUNone):
+            for name in ["rom", "sram"]:
+                if name not in list(self.bus.regions.keys()) + list(self.bus.ld_regions.keys()):
+                    self.logger.error("CPU needs {} Region to be defined as Bus or Linker Region.".format(
+                        colorer(name, color="red")))
+                    self.logger.error(self.bus)
+                    raise
+
         # SoC IRQ Interconnect ---------------------------------------------------------------------
         if hasattr(self, "cpu"):
             if hasattr(self.cpu, "interrupt"):

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 5417479cf1c15c1b2f39b3cff933e0302ff9a7c0..5f9c2e29f0ee1abccbc61ab1fc0f74168c32a137 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -202,12 +202,6 @@ class SoCCore(SoC):
             region.length = region.size
             region.type   = "cached" if region.cached else "io"
 
-        # Verify CPU has required memories
-        if not isinstance(self.cpu, cpu.CPUNone):
-            for name in ["rom", "sram"]:
-                if name not in self.bus.regions.keys():
-                    raise FinalizeError("CPU needs \"{}\" to be defined as memory or linker region".format(name))
-
         SoC.do_finalize(self)
 
         # Add CSRs regions