if (!r300->ctx)
goto fail;
- r300->cs = rws->cs_create(r300->ctx, RING_GFX, r300_flush_callback, r300);
+ r300->cs = rws->cs_create(r300->ctx, RING_GFX, r300_flush_callback, r300, false);
if (r300->cs == NULL)
goto fail;
}
rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
- r600_context_gfx_flush, rctx);
+ r600_context_gfx_flush, rctx, false);
rctx->b.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader =
if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
r600_flush_dma_ring,
- rctx);
+ rctx, false);
rctx->dma.flush = r600_flush_dma_ring;
}
dec->stream_handle = rvid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
- dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL);
+ dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL, false);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
enc->screen = context->screen;
enc->ws = ws;
- enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc);
+ enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
dec->stream_handle = si_vid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
- dec->cs = ws->cs_create(sctx->ctx, RING_UVD, NULL, NULL);
+ dec->cs = ws->cs_create(sctx->ctx, RING_UVD, NULL, NULL, false);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
enc->screen = context->screen;
enc->ws = ws;
enc->cs =
- ws->cs_create(sctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc);
+ ws->cs_create(sctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
enc->screen = context->screen;
enc->ws = ws;
- enc->cs = ws->cs_create(sctx->ctx, RING_VCE, rvce_cs_flush, enc);
+ enc->cs = ws->cs_create(sctx->ctx, RING_VCE, rvce_cs_flush, enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
dec->stream_handle = si_vid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
- dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL);
+ dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL, false);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
enc->bits_in_shifter = 0;
enc->screen = context->screen;
enc->ws = ws;
- enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc);
+ enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush,
+ enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
* \param user User pointer that will be passed to the flush callback.
*/
struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx,
- enum ring_type ring_type,
- void (*flush)(void *ctx, unsigned flags,
- struct pipe_fence_handle **fence),
- void *flush_ctx);
+ enum ring_type ring_type,
+ void (*flush)(void *ctx, unsigned flags,
+ struct pipe_fence_handle **fence),
+ void *flush_ctx,
+ bool stop_exec_on_failure);
/**
* Destroy a command stream.
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->ws;
int shader, i;
+ bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
if (!sctx)
return NULL;
if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
- (void*)si_flush_dma_cs,
- sctx);
+ (void*)si_flush_dma_cs,
+ sctx, stop_exec_on_failure);
}
si_init_buffer_functions(sctx);
}
sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX,
- (void*)si_flush_gfx_cs, sctx);
+ (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
- void *flush_ctx)
+ void *flush_ctx,
+ bool stop_exec_on_failure)
{
struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
struct amdgpu_cs *cs;
cs->flush_cs = flush;
cs->flush_data = flush_ctx;
cs->ring_type = ring_type;
+ cs->stop_exec_on_failure = stop_exec_on_failure;
struct amdgpu_cs_fence_info fence_info;
fence_info.handle = cs->ctx->user_fence_bo;
if (acs->ring_type == RING_GFX)
ws->gfx_bo_list_counter += cs->num_real_buffers;
- if (acs->ctx->num_rejected_cs) {
+ if (acs->stop_exec_on_failure && acs->ctx->num_rejected_cs) {
r = -ECANCELED;
} else {
struct drm_amdgpu_cs_chunk chunks[6];
/* Flush CS. */
void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
void *flush_data;
+ bool stop_exec_on_failure;
struct util_queue_fence flush_completed;
struct pipe_fence_handle *next_fence;
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
- void *flush_ctx)
+ void *flush_ctx,
+ bool stop_exec_on_failure)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)ctx;
struct radeon_drm_cs *cs;