*last_inst(c) = qpu_set_cond_add(*last_inst(c), cond);
}
+/**
+ * Some special registers can be read from either file, which lets us resolve
+ * raddr conflicts without extra MOVs.
+ */
+static bool
+swap_file(struct qpu_reg *src)
+{
+ switch (src->addr) {
+ case QPU_R_UNIF:
+ case QPU_R_VARY:
+ if (src->mux == QPU_MUX_A)
+ src->mux = QPU_MUX_B;
+ else
+ src->mux = QPU_MUX_A;
+ return true;
+
+ default:
+ return false;
+ }
+}
+
/**
* This is used to resolve the fact that we might register-allocate two
* different operands of an instruction to the same physical register file
*/
static void
fixup_raddr_conflict(struct vc4_compile *c,
- struct qpu_reg src0, struct qpu_reg *src1)
+ struct qpu_reg *src0, struct qpu_reg *src1)
{
- if ((src0.mux != QPU_MUX_A && src0.mux != QPU_MUX_B) ||
- src0.mux != src1->mux ||
- src0.addr == src1->addr) {
+ if ((src0->mux != QPU_MUX_A && src0->mux != QPU_MUX_B) ||
+ src0->mux != src1->mux ||
+ src0->addr == src1->addr) {
return;
}
+ if (swap_file(src0) || swap_file(src1))
+ return;
+
queue(c, qpu_a_MOV(qpu_r3(), *src1));
*src1 = qpu_r3();
}
if (qir_get_op_nsrc(qinst->op) == 1)
src[1] = src[0];
- fixup_raddr_conflict(c, src[0], &src[1]);
+ fixup_raddr_conflict(c, &src[0], &src[1]);
if (translate[qinst->op].is_mul) {
queue(c, qpu_m_alu2(translate[qinst->op].op,