Do not compute sign bit if result is zero

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index b745547a8385e77f16162e87fe0680955c211f6f..bfd216fbf06b616c81e78d68e899913569839fa9 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -69,7 +69,6 @@ module \$mul (A, B, Y);
                );\r
        else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin\r
                wire _;\r
-               assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1];\r
                \$__mul #(\r
                        .A_SIGNED(A_SIGNED),\r
                        .B_SIGNED(B_SIGNED),\r
@@ -81,6 +80,8 @@ module \$mul (A, B, Y);
                        .B(B),\r
                        .Y({_,Y[Y_WIDTH-2:0]})\r
                );\r
+               // For non-zero results, recompute sign bit\r
+               assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]);\r
        end\r
        else\r
                \$__mul #(\r