asmicon: various fixes. Now produces convincing refresh/read sequences.

diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py
index f0b8ac5c729dcb0da0ae52f15218734d5bbe0a01..12022b23c436da3f3b755db73d856d7cacbb8189 100644 (file)
--- a/milkymist/asmicon/bankmachine.py
+++ b/milkymist/asmicon/bankmachine.py
@@ -119,11 +119,13 @@ class _Selector:
                        for slot in self.slots]
                comb += multimux(rr.grant, mux_inputs, mux_outputs)
                comb += [
-                       self.stb.eq(state == SLOT_PENDING),
+                       self.stb.eq(
+                               (self.slicer.bank(self.adr) == self.bankn) \
+                               & (state == SLOT_PENDING)),
                        rr.ce.eq(self.ack),
                        self.tag.eq(rr.grant)
                ]
-               comb += [slot.process.eq((rr.grant == i) & self.stb & self.ack)
+               comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
                        for i, slot in enumerate(self.slots)]
                
                return Fragment(comb, sync) + rr.get_fragment()

diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py
index da1818b5cd2c83cbe20af15aff043b24b7766c63..6b459262ac9cf1e1624c0445d10e95618292877f 100644 (file)
--- a/milkymist/asmicon/multiplexer.py
+++ b/milkymist/asmicon/multiplexer.py
@@ -53,11 +53,11 @@ class _CommandChooser:
                outputs_filtered = [self.cmd.cas_n, self.cmd.ras_n, self.cmd.we_n]
                ms = multimux(rr.grant, inputs_filtered, outputs_filtered)
                comb += [
-                       self.cmd.stb.eq(stb & ((self.cmd.is_read == self.want_reads) | (self.cmd.is_write == self.want_writes))),
+                       self.cmd.stb.eq(stb & (self.cmd.is_read == self.want_reads) & (self.cmd.is_write == self.want_writes)),
                        If(self.cmd.stb, *ms)
                ]
                
-               comb += [req.ack.eq(self.cmd.stb & self.cmd.ack & rr.grant == i)
+               comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
                        for i, req in enumerate(self.requests)]
                comb.append(rr.ce.eq(self.cmd.ack))