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* mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1
authorJeff Law <law@redhat.com>
Mon, 1 Jun 1998 16:28:52 +0000 (16:28 +0000)
committerJeff Law <law@redhat.com>
Mon, 1 Jun 1998 16:28:52 +0000 (16:28 +0000)
        (sqrt.s): Likewise.

opcodes/ChangeLog patch | blob | history
opcodes/mips-opc.c patch | blob | history

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3ada20e2a8727e2de2c77ca735e0cfc63cec84f7..c2d39a0bbe61420ba9f335253547f16ca57ad267 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,24 @@
+start-sanitize-r5900
+Mon Jun  1 10:27:26 1998  Jeffrey A Law  (law@cygnus.com)
+
+        * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1
+        (sqrt.s): Likewise.
+
+end-sanitize-r5900
+start-sanitize-vr5400
+Thu May 28 08:46:09 1998  Catherine Moore <clm@cygnus.com>
+ 
+       * mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu):
+       Change pinfo to use WR_HILO.
+
+end-sanitize-vr5400 
+start-sanitize-d30v
+Wed May 27 15:29:13 1998  Nick Clifton  <nickc@cygnus.com>
+
+       * d30v-opc.c: Add new operand: Ra3.  Change SHORT_B3, SHORT_B3b,
+       LONG_2, LONG_2b formats to use this new operand.
+
+end-sanitize-d30v
 Tue May 26 20:47:48 1998  Stan Cox  <scox@cygnus.com>
 
        * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le.
@@ -7,6 +28,7 @@ Tue May 26 20:45:33 1998  Mark Alexander  <marka@cygnus.com>
        * sparc-dis.c (print_insn_sparc): big endian instruction / little
        endian data support.
 
+start-sanitize-d30v
 Tue May 26 16:14:39 1998  Nick Clifton  <nickc@cygnus.com>
 
        * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
@@ -17,6 +39,7 @@ Tue May 26 16:14:39 1998  Nick Clifton  <nickc@cygnus.com>
        Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
        to existing 1.1.1 parallelisation prohibition procedure.
 
+end-sanitize-d30v
 Fri May 22 16:00:00 1998  Doug Evans  <devans@canuck.cygnus.com>
 
        * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.
@@ -80,10 +103,12 @@ Tue May 12 13:39:51 1998  Nick Clifton  <nickc@cygnus.com>
        insns.
        
 end-sanitize-m32rx
+start-sanitize-d30v
 Tue May 12 11:46:31 1998  Richard Henderson  <rth@cygnus.com>
 
        * d30v-opc.c (pre_defined_register): Remove alias for r0.
 
+end-sanitize-d30v
 start-sanitize-r5900
 Mon May 11 13:12:15 1998  Frank Ch. Eigler  <fche@cygnus.com>
        
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index d346afdc12e721e8178b503a3f77cd9636a47a68..fb499a97e6a2fa0478f6c886e04faa41567b4705 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -548,25 +548,25 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"macc",    "d,s,t",   0x000000A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
   /* end-sanitize-vr4320 */
   /* start-sanitize-vr5400 */
-{"macc",    "d,s,t",   0x00000158, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
+{"macc",    "d,s,t",   0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
   /* end-sanitize-vr5400 */
   /* start-sanitize-vr4320 */
 {"maccu",   "d,s,t",   0x000000E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
   /* end-sanitize-vr4320 */
   /* start-sanitize-vr5400 */
-{"maccu",   "d,s,t",   0x00000159, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
+{"maccu",   "d,s,t",   0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
   /* end-sanitize-vr5400 */
   /* start-sanitize-vr4320 */
 {"macchi",  "d,s,t",   0x000002A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
   /* end-sanitize-vr4320 */
   /* start-sanitize-vr5400 */
-{"macchi",  "d,s,t",   0x00000358, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
+{"macchi",  "d,s,t",   0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
   /* end-sanitize-vr5400 */
   /* start-sanitize-vr4320 */
 {"macchiu", "d,s,t",   0x000002E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
   /* end-sanitize-vr4320 */
   /* start-sanitize-vr5400 */
-{"macchiu", "d,s,t",   0x00000359, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
+{"macchiu", "d,s,t",   0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
   /* end-sanitize-vr5400 */
 {"mad",            "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
 {"madu",    "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
@@ -677,10 +677,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"movz.d",  "D,S,t",   0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4      },
 {"movz.s",  "D,S,t",   0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4      },
   /* start-sanitize-vr5400 */
-{"msac",    "d,s,t",   0x000001d8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,        N5      },
-{"msacu",   "d,s,t",   0x000001d9, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,        N5      },
-{"msachi",  "d,s,t",   0x000003d8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,        N5      },
-{"msachiu", "d,s,t",   0x000003d9, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,        N5      },
+{"msac",    "d,s,t",   0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
+{"msacu",   "d,s,t",   0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
+{"msachi",  "d,s,t",   0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
+{"msachiu", "d,s,t",   0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
   /* end-sanitize-vr5400 */
 /* move is at the top of the table.  */
 {"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
@@ -757,6 +757,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"multu",   "s,t",     0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,      I1},
 {"multu",   "d,s,t",   0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1},
   /* start-sanitize-r5900 */
+{"multu1",  "s,t",     0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,      T5},
 {"multu1",  "d,s,t",   0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
   /* end-sanitize-r5900 */
 {"neg",     "d,w",     0x00000022, 0xffe007ff, WR_d|RD_t,      I1      }, /* sub 0 */
@@ -932,7 +933,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4      },
 {"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4      },
 /* start-sanitize-r5900 */
-{"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S, T5      },
+{"rsqrt.s", "D,S,T",   0x46000016, 0xffe0003f, WR_D|RD_S|FP_S, T5      },
 /* end-sanitize-r5900 */
 {"sb",      "t,o(b)",  0xa0000000, 0xfc000000, SM|RD_t|RD_b,   I1      },
 {"sb",      "t,A(b)",  0,    (int) M_SB_AB,    INSN_MACRO,     I1      },
@@ -995,6 +996,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"sq",     "t,o(b)",   0x7c000000, 0xfc000000, SM|RD_t|RD_b,   T5      },
   /* end-sanitize-r5900 */
 {"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2      },
+/* start-sanitize-r5900 */
+{"sqrt.s",  "D,T",     0x46000004, 0xffe0f83f, WR_D|RD_S|FP_S, T5      },
+/* end-sanitize-r5900 */
 {"sqrt.s",  "D,S",     0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2      },
 {"srav",    "d,t,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1      },
 {"sra",     "d,w,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1      }, /* srav */